clock_manager_arria10.h 7.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2016-2017 Intel Corporation
  4. */
  5. #ifndef CLOCK_MANAGER_ARRIA10
  6. #define CLOCK_MANAGER_ARRIA10
  7. #ifndef __ASSEMBLY__
  8. /* Clock manager group */
  9. #define CLKMGR_A10_CTRL 0x00
  10. #define CLKMGR_A10_INTR 0x04
  11. #define CLKMGR_A10_STAT 0x1c
  12. /* MainPLL group */
  13. #define CLKMGR_A10_MAINPLL_VCO0 0x40
  14. #define CLKMGR_A10_MAINPLL_VCO1 0x44
  15. #define CLKMGR_A10_MAINPLL_EN 0x48
  16. #define CLKMGR_A10_MAINPLL_ENS 0x4c
  17. #define CLKMGR_A10_MAINPLL_ENR 0x50
  18. #define CLKMGR_A10_MAINPLL_BYPASS 0x54
  19. #define CLKMGR_A10_MAINPLL_BYPASSS 0x58
  20. #define CLKMGR_A10_MAINPLL_BYPASSR 0x5c
  21. #define CLKMGR_A10_MAINPLL_MPUCLK 0x60
  22. #define CLKMGR_A10_MAINPLL_NOCCLK 0x64
  23. #define CLKMGR_A10_MAINPLL_CNTR2CLK 0x68
  24. #define CLKMGR_A10_MAINPLL_CNTR3CLK 0x6c
  25. #define CLKMGR_A10_MAINPLL_CNTR4CLK 0x70
  26. #define CLKMGR_A10_MAINPLL_CNTR5CLK 0x74
  27. #define CLKMGR_A10_MAINPLL_CNTR6CLK 0x78
  28. #define CLKMGR_A10_MAINPLL_CNTR7CLK 0x7c
  29. #define CLKMGR_A10_MAINPLL_CNTR8CLK 0x80
  30. #define CLKMGR_A10_MAINPLL_CNTR9CLK 0x84
  31. #define CLKMGR_A10_MAINPLL_CNTR15CLK 0x9c
  32. #define CLKMGR_A10_MAINPLL_NOCDIV 0xa8
  33. /* Peripheral PLL group */
  34. #define CLKMGR_A10_PERPLL_VCO0 0xc0
  35. #define CLKMGR_A10_PERPLL_VCO1 0xc4
  36. #define CLKMGR_A10_PERPLL_EN 0xc8
  37. #define CLKMGR_A10_PERPLL_ENS 0xcc
  38. #define CLKMGR_A10_PERPLL_ENR 0xd0
  39. #define CLKMGR_A10_PERPLL_BYPASS 0xd4
  40. #define CLKMGR_A10_PERPLL_BYPASSS 0xd8
  41. #define CLKMGR_A10_PERPLL_BYPASSR 0xdc
  42. #define CLKMGR_A10_PERPLL_CNTR2CLK 0xe8
  43. #define CLKMGR_A10_PERPLL_CNTR3CLK 0xec
  44. #define CLKMGR_A10_PERPLL_CNTR4CLK 0xf0
  45. #define CLKMGR_A10_PERPLL_CNTR5CLK 0xf4
  46. #define CLKMGR_A10_PERPLL_CNTR6CLK 0xf8
  47. #define CLKMGR_A10_PERPLL_CNTR7CLK 0xfc
  48. #define CLKMGR_A10_PERPLL_CNTR8CLK 0x100
  49. #define CLKMGR_A10_PERPLL_CNTR9CLK 0x104
  50. #define CLKMGR_A10_PERPLL_EMACCTL 0x128
  51. #define CLKMGR_A10_PERPLL_GPIOFIV 0x12c
  52. /* Altera group */
  53. #define CLKMGR_A10_ALTR_MPUCLK 0x140
  54. #define CLKMGR_A10_ALTR_NOCCLK 0x144
  55. #define CLKMGR_STAT CLKMGR_A10_STAT
  56. #define CLKMGR_INTER CLKMGR_A10_INTER
  57. #define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN
  58. #ifdef CONFIG_SPL_BUILD
  59. int cm_basic_init(const void *blob);
  60. #endif
  61. unsigned int cm_get_l4_sp_clk_hz(void);
  62. unsigned long cm_get_mpu_clk_hz(void);
  63. unsigned int cm_get_qspi_controller_clk_hz(void);
  64. #endif /* __ASSEMBLY__ */
  65. #define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
  66. CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
  67. /* value */
  68. #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
  69. #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
  70. #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
  71. #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
  72. #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
  73. #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
  74. #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
  75. #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
  76. #define CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2
  77. #define CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0
  78. #define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1
  79. #define CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2
  80. #define CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3
  81. /* mask */
  82. #define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK BIT(6)
  83. #define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK BIT(7)
  84. #define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK BIT(8)
  85. #define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK BIT(9)
  86. #define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK BIT(17)
  87. #define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
  88. #define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK BIT(1)
  89. #define CLKMGR_MAINPLL_VCO0_EN_SET_MSK BIT(2)
  90. #define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
  91. #define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
  92. #define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
  93. #define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK BIT(1)
  94. #define CLKMGR_PERPLL_VCO0_EN_SET_MSK BIT(2)
  95. #define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
  96. #define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
  97. #define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK BIT(0)
  98. #define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK BIT(1)
  99. #define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK BIT(2)
  100. #define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK BIT(3)
  101. #define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK BIT(8)
  102. #define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK BIT(9)
  103. #define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK BIT(10)
  104. #define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK BIT(11)
  105. #define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK BIT(0)
  106. #define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300
  107. #define CLKMGR_PERPLL_EN_RESET 0x00000f7f
  108. #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
  109. #define CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003
  110. #define CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff
  111. #define CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f
  112. #define CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff
  113. #define CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003
  114. #define CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff
  115. #define CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f
  116. #define CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff
  117. #define CLKMGR_MAINPLL_MPUCLK_SRC_MSK 0x00000007
  118. #define CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff
  119. #define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0
  120. #define CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1
  121. #define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2
  122. #define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3
  123. #define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4
  124. #define CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003
  125. #define CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff
  126. #define CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007
  127. #define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0
  128. #define CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1
  129. #define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2
  130. #define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3
  131. #define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4
  132. #define CLKMGR_PERPLLGRP_SRC_MSK 0x00000007
  133. #define CLKMGR_PERPLLGRP_SRC_MAIN 0
  134. #define CLKMGR_PERPLLGRP_SRC_PERI 1
  135. #define CLKMGR_PERPLLGRP_SRC_OSC1 2
  136. #define CLKMGR_PERPLLGRP_SRC_INTOSC 3
  137. #define CLKMGR_PERPLLGRP_SRC_FPGA 4
  138. /* bit shifting macro */
  139. #define CLKMGR_MAINPLL_VCO0_PSRC_LSB 8
  140. #define CLKMGR_PERPLL_VCO0_PSRC_LSB 8
  141. #define CLKMGR_MAINPLL_VCO1_DENOM_LSB 16
  142. #define CLKMGR_PERPLL_VCO1_DENOM_LSB 16
  143. #define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16
  144. #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
  145. #define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
  146. #define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
  147. #define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
  148. #define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
  149. #define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
  150. #define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
  151. #define CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
  152. #define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16
  153. #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
  154. #define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
  155. #define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16
  156. #define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
  157. #define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
  158. #define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
  159. #define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
  160. #define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
  161. #define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
  162. #define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
  163. #define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
  164. #define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
  165. /* PLL ramping work around */
  166. #define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000
  167. #define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000
  168. #define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000
  169. #define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000
  170. #define CLKMGR_STAT_BUSY BIT(0)
  171. #endif /* CLOCK_MANAGER_ARRIA10 */