clock_manager.h 722 B

123456789101112131415161718192021222324252627
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
  4. */
  5. #ifndef _CLOCK_MANAGER_H_
  6. #define _CLOCK_MANAGER_H_
  7. phys_addr_t socfpga_get_clkmgr_addr(void);
  8. #ifndef __ASSEMBLY__
  9. void cm_wait_for_lock(u32 mask);
  10. int cm_wait_for_fsm(void);
  11. void cm_print_clock_quick_summary(void);
  12. #endif
  13. #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  14. #include <asm/arch/clock_manager_gen5.h>
  15. #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  16. #include <asm/arch/clock_manager_arria10.h>
  17. #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
  18. #include <asm/arch/clock_manager_s10.h>
  19. #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
  20. #include <asm/arch/clock_manager_agilex.h>
  21. #endif
  22. #endif /* _CLOCK_MANAGER_H_ */