imx-regs.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013-2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __ASM_ARCH_IMX_REGS_H__
  6. #define __ASM_ARCH_IMX_REGS_H__
  7. #define ARCH_MXC
  8. #define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
  9. #define IRAM_SIZE 0x00080000 /* 512 KB */
  10. #define AIPS0_BASE_ADDR 0x40000000
  11. #define AIPS1_BASE_ADDR 0x40080000
  12. /* AIPS 0 */
  13. #define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
  14. #define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
  15. #define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
  16. #define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
  17. #define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
  18. #define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
  19. #define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
  20. #define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
  21. #define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
  22. #define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000)
  23. #define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
  24. #define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000)
  25. #define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000)
  26. #define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
  27. #define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000)
  28. #define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000)
  29. #define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000)
  30. #define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000)
  31. #define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000)
  32. #define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000)
  33. #define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000)
  34. #define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000)
  35. #define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000)
  36. #define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000)
  37. #define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000)
  38. #define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000)
  39. #define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000)
  40. #define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000)
  41. #define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000)
  42. #define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000)
  43. #define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000)
  44. #define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000)
  45. #define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
  46. #define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
  47. #define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
  48. #define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
  49. #define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
  50. #define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
  51. #define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
  52. #define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
  53. #define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
  54. #define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000)
  55. #define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000)
  56. #define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
  57. #define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000)
  58. #define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
  59. #define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000)
  60. #define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
  61. #define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
  62. #define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
  63. #define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
  64. #define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
  65. #define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
  66. #define DCU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00058000)
  67. #define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
  68. #define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
  69. #define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
  70. #define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
  71. #define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
  72. #define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
  73. #define I2C2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00067000)
  74. #define I2C3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E6000)
  75. #define I2C4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E7000)
  76. #define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
  77. #define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
  78. #define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
  79. #define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
  80. #define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
  81. #define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
  82. #define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000)
  83. #define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040)
  84. #define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080)
  85. #define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0)
  86. #define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100)
  87. /* AIPS 1 */
  88. #define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)
  89. #define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
  90. #define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
  91. #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
  92. #define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
  93. #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
  94. #define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
  95. #define DCU1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00058000)
  96. #define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000)
  97. #define QSPI0_AMBA_BASE 0x20000000
  98. /* MUX mode and PAD ctrl are in one register */
  99. #define CONFIG_IOMUX_SHARE_CONF_REG
  100. #define FEC_QUIRK_ENET_MAC
  101. #define I2C_QUIRK_REG
  102. /* MSCM interrupt rounter */
  103. #define MSCM_IRSPRC_CP0_EN 1
  104. #define MSCM_IRSPRC_NUM 112
  105. /* DDRMC */
  106. #define DDRMC_PHY_DQ_TIMING 0x00002613
  107. #define DDRMC_PHY_DQS_TIMING 0x00002615
  108. #define DDRMC_PHY_CTRL 0x00210000
  109. #define DDRMC_PHY_MASTER_CTRL 0x0001012a
  110. #define DDRMC_PHY_SLAVE_CTRL 0x00002000
  111. #define DDRMC_PHY_OFF 0x00000000
  112. #define DDRMC_PHY_PROC_PAD_ODT 0x00010101
  113. #define DDRMC_PHY50_DDR3_MODE (1 << 12)
  114. #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8)
  115. #define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8)
  116. #define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8)
  117. #define DDRMC_CR00_START 1
  118. #define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff)
  119. #define DDRMC_CR10_TRST_PWRON(v) (v)
  120. #define DDRMC_CR11_CKE_INACTIVE(v) (v)
  121. #define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8)
  122. #define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f)
  123. #define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24)
  124. #define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16)
  125. #define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8)
  126. #define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7)
  127. #define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24)
  128. #define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16)
  129. #define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8)
  130. #define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff)
  131. #define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24)
  132. #define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16)
  133. #define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8)
  134. #define DDRMC_CR17_TMOD(v) ((v) & 0xff)
  135. #define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8)
  136. #define DDRMC_CR18_TCKE(v) ((v) & 0x7)
  137. #define DDRMC_CR20_AP_EN (1 << 24)
  138. #define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
  139. #define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8)
  140. #define DDRMC_CR21_CCMAP_EN 1
  141. #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
  142. #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
  143. #define DDRMC_CR23_TDLL(v) ((v) & 0xffff)
  144. #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f)
  145. #define DDRMC_CR25_TREF_EN (1 << 16)
  146. #define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16)
  147. #define DDRMC_CR26_TRFC(v) ((v) & 0x3ff)
  148. #define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff)
  149. #define DDRMC_CR29_TPDEX(v) ((v) & 0xffff)
  150. #define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff)
  151. #define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16)
  152. #define DDRMC_CR31_TXSR(v) ((v) & 0xffff)
  153. #define DDRMC_CR33_EN_QK_SREF (1 << 16)
  154. #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16)
  155. #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8)
  156. #define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8)
  157. #define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16)
  158. #define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8)
  159. #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3)
  160. #define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1
  161. #define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16)
  162. #define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff)
  163. #define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16)
  164. #define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff)
  165. #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff)
  166. #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8)
  167. #define DDRMC_CR70_REF_PER_ZQ(v) (v)
  168. #define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24)
  169. #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24)
  170. #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16)
  171. #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8)
  172. #define DDRMC_CR74_BANKSPLT_EN (1 << 24)
  173. #define DDRMC_CR74_ADDR_CMP_EN (1 << 16)
  174. #define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8)
  175. #define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff)
  176. #define DDRMC_CR75_RW_PG_EN (1 << 24)
  177. #define DDRMC_CR75_RW_EN (1 << 16)
  178. #define DDRMC_CR75_PRI_EN (1 << 8)
  179. #define DDRMC_CR75_PLEN 1
  180. #define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24)
  181. #define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16)
  182. #define DDRMC_CR76_W2R_SPLT_EN (1 << 8)
  183. #define DDRMC_CR76_CS_EN 1
  184. #define DDRMC_CR77_CS_MAP (1 << 24)
  185. #define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8)
  186. #define DDRMC_CR77_SWAP_EN 1
  187. #define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24)
  188. #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
  189. #define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
  190. #define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8)
  191. #define DDRMC_CR82_INT_MASK (1 << 28)
  192. #define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
  193. #define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
  194. #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
  195. #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
  196. #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
  197. #define DDRMC_CR93_SW_LVL_MODE_OFF (8)
  198. #define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << DDRMC_CR93_SW_LVL_MODE_OFF)
  199. #define DDRMC_CR93_SWLVL_LOAD BIT(16)
  200. #define DDRMC_CR93_SWLVL_START BIT(24)
  201. #define DDRMC_CR94_SWLVL_EXIT BIT(0)
  202. #define DDRMC_CR94_SWLVL_OP_DONE BIT(8)
  203. #define DDRMC_CR94_SWLVL_RESP_0_OFF (24)
  204. #define DDRMC_CR95_SWLVL_RESP_1_OFF (0)
  205. #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8)
  206. #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f)
  207. #define DDRMC_CR97_WRLVL_EN (1 << 24)
  208. #define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff)
  209. #define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff)
  210. #define DDRMC_CR101_PHY_RDLVL_EDGE_OFF (24)
  211. #define DDRMC_CR101_PHY_RDLVL_EDGE BIT(DDRMC_CR101_PHY_RDLVL_EDGE_OFF)
  212. #define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16)
  213. #define DDRMC_CR102_RDLVL_REG_EN (1 << 8)
  214. #define DDRMC_CR105_RDLVL_DL_0_OFF (8)
  215. #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << DDRMC_CR105_RDLVL_DL_0_OFF)
  216. #define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff)
  217. #define DDRMC_CR110_RDLVL_DL_1_OFF (0)
  218. #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff)
  219. #define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16)
  220. #define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8)
  221. #define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff)
  222. #define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8)
  223. #define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3)
  224. #define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24)
  225. #define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16)
  226. #define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24)
  227. #define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16)
  228. #define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8)
  229. #define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf)
  230. #define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24)
  231. #define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16)
  232. #define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff)
  233. #define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8)
  234. #define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf)
  235. #define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16)
  236. #define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff)
  237. #define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8)
  238. #define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8)
  239. #define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f)
  240. #define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16)
  241. #define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16)
  242. #define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x7) << 8)
  243. #define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24)
  244. #define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16)
  245. #define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8)
  246. #define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff)
  247. #define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff)
  248. #define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16)
  249. #define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff)
  250. #define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24)
  251. #define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16)
  252. #define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8)
  253. #define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff)
  254. #define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff)
  255. #define DDRMC_CR146_PHY_RDLVL_RESP(v) (v)
  256. #define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff)
  257. #define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff)
  258. #define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8)
  259. #define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf)
  260. #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27)
  261. #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21)
  262. #define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18)
  263. #define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14)
  264. #define DDRMC_CR155_AXI0_AWCACHE (1 << 10)
  265. #define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3)
  266. #define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7)
  267. #define DDRMC_CR158_TWR(v) ((v) & 0x3f)
  268. #define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16)
  269. #define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8)
  270. #define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf)
  271. /* System Reset Controller (SRC) */
  272. #define SRC_SRSR_SW_RST (0x1 << 18)
  273. #define SRC_SRSR_RESETB (0x1 << 7)
  274. #define SRC_SRSR_JTAG_RST (0x1 << 5)
  275. #define SRC_SRSR_WDOG_M4 (0x1 << 4)
  276. #define SRC_SRSR_WDOG_A5 (0x1 << 3)
  277. #define SRC_SRSR_POR_RST (0x1 << 0)
  278. #define SRC_SBMR1_BOOTCFG1_SDMMC BIT(6)
  279. #define SRC_SBMR1_BOOTCFG1_MMC BIT(4)
  280. #define SRC_SBMR2_BMOD_MASK (0x3 << 24)
  281. #define SRC_SBMR2_BMOD_SHIFT 24
  282. #define SRC_SBMR2_BMOD_FUSES 0x0
  283. #define SRC_SBMR2_BMOD_SERIAL 0x1
  284. #define SRC_SBMR2_BMOD_RCON 0x2
  285. /* Slow Clock Source Controller Module (SCSC) */
  286. #define SCSC_SOSC_CTR_SOSC_EN 0x1
  287. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  288. #include <asm/types.h>
  289. /* System Reset Controller (SRC) */
  290. struct src {
  291. u32 scr;
  292. u32 sbmr1;
  293. u32 srsr;
  294. u32 secr;
  295. u32 gpsr;
  296. u32 sicr;
  297. u32 simr;
  298. u32 sbmr2;
  299. u32 gpr0;
  300. u32 gpr1;
  301. u32 gpr2;
  302. u32 gpr3;
  303. u32 gpr4;
  304. u32 hab0;
  305. u32 hab1;
  306. u32 hab2;
  307. u32 hab3;
  308. u32 hab4;
  309. u32 hab5;
  310. u32 misc0;
  311. u32 misc1;
  312. u32 misc2;
  313. u32 misc3;
  314. };
  315. /* Periodic Interrupt Timer (PIT) */
  316. struct pit_reg {
  317. u32 mcr;
  318. u32 recv0[55];
  319. u32 ltmr64h;
  320. u32 ltmr64l;
  321. u32 recv1[6];
  322. u32 ldval0;
  323. u32 cval0;
  324. u32 tctrl0;
  325. u32 tflg0;
  326. u32 ldval1;
  327. u32 cval1;
  328. u32 tctrl1;
  329. u32 tflg1;
  330. u32 ldval2;
  331. u32 cval2;
  332. u32 tctrl2;
  333. u32 tflg2;
  334. u32 ldval3;
  335. u32 cval3;
  336. u32 tctrl3;
  337. u32 tflg3;
  338. u32 ldval4;
  339. u32 cval4;
  340. u32 tctrl4;
  341. u32 tflg4;
  342. u32 ldval5;
  343. u32 cval5;
  344. u32 tctrl5;
  345. u32 tflg5;
  346. u32 ldval6;
  347. u32 cval6;
  348. u32 tctrl6;
  349. u32 tflg6;
  350. u32 ldval7;
  351. u32 cval7;
  352. u32 tctrl7;
  353. u32 tflg7;
  354. };
  355. /* Watchdog Timer (WDOG) */
  356. struct wdog_regs {
  357. u16 wcr;
  358. u16 wsr;
  359. u16 wrsr;
  360. u16 wicr;
  361. u16 wmcr;
  362. };
  363. /* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */
  364. struct ddrmr_regs {
  365. u32 cr[162];
  366. u32 rsvd[94];
  367. u32 phy[53];
  368. };
  369. /* On-Chip One Time Programmable Controller (OCOTP) */
  370. struct ocotp_regs {
  371. u32 ctrl;
  372. u32 ctrl_set;
  373. u32 ctrl_clr;
  374. u32 ctrl_tog;
  375. u32 timing;
  376. u32 rsvd0[3];
  377. u32 data;
  378. u32 rsvd1[3];
  379. u32 read_ctrl;
  380. u32 rsvd2[3];
  381. u32 read_fuse_data;
  382. u32 rsvd3[7];
  383. u32 scs;
  384. u32 scs_set;
  385. u32 scs_clr;
  386. u32 scs_tog;
  387. u32 crc_addr;
  388. u32 rsvd4[3];
  389. u32 crc_value;
  390. u32 rsvd5[3];
  391. u32 version;
  392. u32 rsvd6[0xdb];
  393. struct fuse_bank {
  394. u32 fuse_regs[0x20];
  395. } bank[16];
  396. };
  397. struct fuse_bank0_regs {
  398. u32 lock;
  399. u32 rsvd0[3];
  400. u32 uid_low;
  401. u32 rsvd1[3];
  402. u32 uid_high;
  403. u32 rsvd2[0x17];
  404. };
  405. struct fuse_bank4_regs {
  406. u32 sjc_resp0;
  407. u32 rsvd0[3];
  408. u32 sjc_resp1;
  409. u32 rsvd1[3];
  410. u32 mac_addr0;
  411. u32 rsvd2[3];
  412. u32 mac_addr1;
  413. u32 rsvd3[3];
  414. u32 mac_addr2;
  415. u32 rsvd4[3];
  416. u32 mac_addr3;
  417. u32 rsvd5[3];
  418. u32 gp1;
  419. u32 rsvd6[3];
  420. u32 gp2;
  421. u32 rsvd7[3];
  422. };
  423. /* MSCM Interrupt Router */
  424. struct mscm_ir {
  425. u32 ircp0ir;
  426. u32 ircp1ir;
  427. u32 rsvd1[6];
  428. u32 ircpgir;
  429. u32 rsvd2[23];
  430. u16 irsprc[112];
  431. u16 rsvd3[848];
  432. };
  433. /* SCSC */
  434. struct scsc_reg {
  435. u32 sirc_ctr;
  436. u32 sosc_ctr;
  437. };
  438. /* MSCM */
  439. struct mscm {
  440. u32 cpxtype;
  441. u32 cpxnum;
  442. u32 cpxmaster;
  443. u32 cpxcount;
  444. u32 cpxcfg0;
  445. u32 cpxcfg1;
  446. u32 cpxcfg2;
  447. u32 cpxcfg3;
  448. };
  449. #endif /* __ASSEMBLY__ */
  450. #endif /* __ASM_ARCH_IMX_REGS_H__ */