imx-regs.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __ASM_ARCH_IMX_REGS_H__
  6. #define __ASM_ARCH_IMX_REGS_H__
  7. #define ARCH_MXC
  8. #define IRAM_BASE_ADDR 0x3E800000 /* internal ram */
  9. #define IRAM_SIZE 0x00400000 /* 4MB */
  10. #define AIPS0_BASE_ADDR (0x40000000UL)
  11. #define AIPS1_BASE_ADDR (0x40080000UL)
  12. /* AIPS 0 */
  13. #define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000)
  14. #define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
  15. #define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
  16. #define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000)
  17. #define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
  18. #define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
  19. #define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
  20. #define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
  21. #define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000)
  22. #define DEC200_DECODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00026000)
  23. #define DEC200_ENCODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00027000)
  24. #define TWOD_ACE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00028000)
  25. #define MIPI_CSI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
  26. #define DMAMUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
  27. #define ENET_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
  28. #define FLEXRAY_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
  29. #define MMDC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
  30. #define MEW0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
  31. #define MONITOR_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
  32. #define MONITOR_CCI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
  33. #define PIT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003A000)
  34. #define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000)
  35. #define MC_CGM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003F000)
  36. #define MC_CGM2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
  37. #define MC_CGM3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00045000)
  38. #define MC_RGM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
  39. #define MC_ME_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004A000)
  40. #define MC_PCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004B000)
  41. #define ADC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004D000)
  42. #define FLEXTIMER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004F000)
  43. #define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00051000)
  44. #define LINFLEXD0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00053000)
  45. #define FLEXCAN0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00055000)
  46. #define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00057000)
  47. #define SPI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00059000)
  48. #define CRC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005B000)
  49. #define USDHC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005D000)
  50. #define OCOTP_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005F000)
  51. #define WKPU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
  52. #define VIU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00064000)
  53. #define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000)
  54. #define SIUL2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
  55. #define SIPI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00074000)
  56. #define LFAST_BASE_ADDR (AIPS0_BASE_ADDR + 0x00078000)
  57. #define SSE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00079000)
  58. #define SRC_SOC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0007C000)
  59. /* AIPS 1 */
  60. #define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000)
  61. #define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000)
  62. #define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000)
  63. #define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000)
  64. #define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000)
  65. #define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000)
  66. #define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000)
  67. #define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000)
  68. #define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000)
  69. #define APB_BASE_ADDR (AIPS1_BASE_ADDR + 0X000009000)
  70. #define XBIC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000012000)
  71. #define MIPI_BASE_ADDR (AIPS1_BASE_ADDR + 0X000020000)
  72. #define DMAMUX1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000021000)
  73. #define MMDC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000022000)
  74. #define MEW1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000023000)
  75. #define DDR1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000024000)
  76. #define CCI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000025000)
  77. #define QUADSPI0_BASE_ADDR (AIPS1_BASE_ADDR + 0X000026000)
  78. #define PIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00002A000)
  79. #define FCCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000030000)
  80. #define FLEXTIMER_FTM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000036000)
  81. #define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000)
  82. #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000)
  83. #define LINFLEXD1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003C000)
  84. #define FLEXCAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003E000)
  85. #define SPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000040000)
  86. #define SPI3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000042000)
  87. #define IPL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000043000)
  88. #define CGM_CMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000044000)
  89. #define PMC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000048000)
  90. #define CRC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004C000)
  91. #define TMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004E000)
  92. #define VIU1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000050000)
  93. #define JPEG_BASE_ADDR (AIPS1_BASE_ADDR + 0X000054000)
  94. #define H264_DEC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000058000)
  95. #define H264_ENC_BASE_ADDR (AIPS1_BASE_ADDR + 0X00005C000)
  96. #define MEMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000060000)
  97. #define STCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000064000)
  98. #define SLFTST_CTRL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000066000)
  99. #define MCT_BASE_ADDR (AIPS1_BASE_ADDR + 0X000068000)
  100. #define REP_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006A000)
  101. #define MBIST_CONTROLLER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006C000)
  102. #define BOOT_LOADER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006F000)
  103. /* TODO Remove this after the IOMUX framework is implemented */
  104. #define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
  105. /* MUX mode and PAD ctrl are in one register */
  106. #define CONFIG_IOMUX_SHARE_CONF_REG
  107. #define FEC_QUIRK_ENET_MAC
  108. #define I2C_QUIRK_REG
  109. /* MSCM interrupt router */
  110. #define MSCM_IRSPRC_CPn_EN 3
  111. #define MSCM_IRSPRC_NUM 176
  112. #define MSCM_CPXTYPE_RYPZ_MASK 0xFF
  113. #define MSCM_CPXTYPE_RYPZ_OFFSET 0
  114. #define MSCM_CPXTYPE_PERS_MASK 0xFFFFFF00
  115. #define MSCM_CPXTYPE_PERS_OFFSET 8
  116. #define MSCM_CPXTYPE_PERS_A53 0x413533
  117. #define MSCM_CPXTYPE_PERS_CM4 0x434d34
  118. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  119. #include <asm/types.h>
  120. /* System Reset Controller (SRC) */
  121. struct src {
  122. u32 bmr1;
  123. u32 bmr2;
  124. u32 gpr1_boot;
  125. u32 reserved_0x00C[61];
  126. u32 gpr1;
  127. u32 gpr2;
  128. u32 gpr3;
  129. u32 gpr4;
  130. u32 gpr5;
  131. u32 gpr6;
  132. u32 gpr7;
  133. u32 reserved_0x11C[1];
  134. u32 gpr9;
  135. u32 gpr10;
  136. u32 gpr11;
  137. u32 gpr12;
  138. u32 gpr13;
  139. u32 gpr14;
  140. u32 gpr15;
  141. u32 gpr16;
  142. u32 reserved_0x140[1];
  143. u32 gpr17;
  144. u32 gpr18;
  145. u32 gpr19;
  146. u32 gpr20;
  147. u32 gpr21;
  148. u32 gpr22;
  149. u32 gpr23;
  150. u32 gpr24;
  151. u32 gpr25;
  152. u32 gpr26;
  153. u32 gpr27;
  154. u32 reserved_0x16C[5];
  155. u32 pcie_config1;
  156. u32 ddr_self_ref_ctrl;
  157. u32 pcie_config0;
  158. u32 reserved_0x18C[4];
  159. u32 soc_misc_config2;
  160. };
  161. /* SRC registers definitions */
  162. /* SRC_GPR1 */
  163. #define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
  164. (SRC_GPR1_PLL_OFFSET + (pll)) )
  165. #define SRC_GPR1_PLL_SOURCE_MASK (0x1)
  166. #define SRC_GPR1_PLL_OFFSET (27)
  167. #define SRC_GPR1_FIRC_CLK_SOURCE (0x0)
  168. #define SRC_GPR1_XOSC_CLK_SOURCE (0x1)
  169. /* Periodic Interrupt Timer (PIT) */
  170. struct pit_reg {
  171. u32 mcr;
  172. u32 recv0[55];
  173. u32 ltmr64h;
  174. u32 ltmr64l;
  175. u32 recv1[6];
  176. u32 ldval0;
  177. u32 cval0;
  178. u32 tctrl0;
  179. u32 tflg0;
  180. u32 ldval1;
  181. u32 cval1;
  182. u32 tctrl1;
  183. u32 tflg1;
  184. u32 ldval2;
  185. u32 cval2;
  186. u32 tctrl2;
  187. u32 tflg2;
  188. u32 ldval3;
  189. u32 cval3;
  190. u32 tctrl3;
  191. u32 tflg3;
  192. u32 ldval4;
  193. u32 cval4;
  194. u32 tctrl4;
  195. u32 tflg4;
  196. u32 ldval5;
  197. u32 cval5;
  198. u32 tctrl5;
  199. u32 tflg5;
  200. };
  201. /* Watchdog Timer (WDOG) */
  202. struct wdog_regs {
  203. u32 cr;
  204. u32 ir;
  205. u32 to;
  206. u32 wn;
  207. u32 sr;
  208. u32 co;
  209. u32 sk;
  210. };
  211. /* UART */
  212. struct linflex_fsl {
  213. u32 lincr1;
  214. u32 linier;
  215. u32 linsr;
  216. u32 linesr;
  217. u32 uartcr;
  218. u32 uartsr;
  219. u32 lintcsr;
  220. u32 linocr;
  221. u32 lintocr;
  222. u32 linfbrr;
  223. u32 linibrr;
  224. u32 lincfr;
  225. u32 lincr2;
  226. u32 bidr;
  227. u32 bdrl;
  228. u32 bdrm;
  229. u32 ifer;
  230. u32 ifmi;
  231. u32 ifmr;
  232. u32 ifcr0;
  233. u32 ifcr1;
  234. u32 ifcr2;
  235. u32 ifcr3;
  236. u32 ifcr4;
  237. u32 ifcr5;
  238. u32 ifcr6;
  239. u32 ifcr7;
  240. u32 ifcr8;
  241. u32 ifcr9;
  242. u32 ifcr10;
  243. u32 ifcr11;
  244. u32 ifcr12;
  245. u32 ifcr13;
  246. u32 ifcr14;
  247. u32 ifcr15;
  248. u32 gcr;
  249. u32 uartpto;
  250. u32 uartcto;
  251. u32 dmatxe;
  252. u32 dmarxe;
  253. };
  254. /* MSCM Interrupt Router */
  255. struct mscm_ir {
  256. u32 cpxtype; /* Processor x Type Register */
  257. u32 cpxnum; /* Processor x Number Register */
  258. u32 cpxmaster; /* Processor x Master Number Register */
  259. u32 cpxcount; /* Processor x Count Register */
  260. u32 cpxcfg0; /* Processor x Configuration 0 Register */
  261. u32 cpxcfg1; /* Processor x Configuration 1 Register */
  262. u32 cpxcfg2; /* Processor x Configuration 2 Register */
  263. u32 cpxcfg3; /* Processor x Configuration 3 Register */
  264. u32 cp0type; /* Processor 0 Type Register */
  265. u32 cp0num; /* Processor 0 Number Register */
  266. u32 cp0master; /* Processor 0 Master Number Register */
  267. u32 cp0count; /* Processor 0 Count Register */
  268. u32 cp0cfg0; /* Processor 0 Configuration 0 Register */
  269. u32 cp0cfg1; /* Processor 0 Configuration 1 Register */
  270. u32 cp0cfg2; /* Processor 0 Configuration 2 Register */
  271. u32 cp0cfg3; /* Processor 0 Configuration 3 Register */
  272. u32 cp1type; /* Processor 1 Type Register */
  273. u32 cp1num; /* Processor 1 Number Register */
  274. u32 cp1master; /* Processor 1 Master Number Register */
  275. u32 cp1count; /* Processor 1 Count Register */
  276. u32 cp1cfg0; /* Processor 1 Configuration 0 Register */
  277. u32 cp1cfg1; /* Processor 1 Configuration 1 Register */
  278. u32 cp1cfg2; /* Processor 1 Configuration 2 Register */
  279. u32 cp1cfg3; /* Processor 1 Configuration 3 Register */
  280. u32 reserved_0x060[232];
  281. u32 ocmdr0; /* On-Chip Memory Descriptor Register */
  282. u32 reserved_0x404[2];
  283. u32 ocmdr3; /* On-Chip Memory Descriptor Register */
  284. u32 reserved_0x410[28];
  285. u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */
  286. u32 reserved_0x490[28];
  287. u32 cpce0; /* Core Parity Checking Enable Register 0 */
  288. u32 reserved_0x504[191];
  289. u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */
  290. u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */
  291. u32 reserved_0x808[6];
  292. u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */
  293. u32 reserved_0x824[23];
  294. u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */
  295. u32 reserved_0x9e0[136];
  296. u32 iahbbe0; /* Gasket Burst Enable Register */
  297. u32 reserved_0xc04[63];
  298. u32 ipcge; /* Interconnect Parity Checking Global Enable Register */
  299. u32 reserved_0xd04[3];
  300. u32 ipce[4]; /* Interconnect Parity Checking Enable Register */
  301. u32 reserved_0xd20[8];
  302. u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */
  303. u32 reserved_0xd44[3];
  304. u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */
  305. };
  306. #endif /* __ASSEMBLY__ */
  307. #endif /* __ASM_ARCH_IMX_REGS_H__ */