imx-regs.h 61 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
  4. */
  5. #ifndef __ASM_ARCH_MX7_IMX_REGS_H__
  6. #define __ASM_ARCH_MX7_IMX_REGS_H__
  7. #define ARCH_MXC
  8. #define ROM_SW_INFO_ADDR 0x000001E8
  9. #define ROMCP_ARB_BASE_ADDR 0x00000000
  10. #define ROMCP_ARB_END_ADDR 0x00017FFF
  11. #define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR
  12. #define CAAM_ARB_BASE_ADDR 0x00100000
  13. #define CAAM_ARB_END_ADDR 0x00107FFF
  14. #define GIC400_ARB_BASE_ADDR 0x31000000
  15. #define GIC400_ARB_END_ADDR 0x31007FFF
  16. #define APBH_DMA_ARB_BASE_ADDR 0x33000000
  17. #define APBH_DMA_ARB_END_ADDR 0x33007FFF
  18. #define M4_BOOTROM_BASE_ADDR 0x00180000
  19. #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
  20. #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
  21. #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
  22. /* GPV - PL301 configuration ports */
  23. #define GPV0_BASE_ADDR 0x32000000
  24. #define GPV1_BASE_ADDR 0x32100000
  25. #define GPV2_BASE_ADDR 0x32200000
  26. #define GPV3_BASE_ADDR 0x32300000
  27. #define GPV4_BASE_ADDR 0x32400000
  28. #define GPV5_BASE_ADDR 0x32500000
  29. #define GPV6_BASE_ADDR 0x32600000
  30. #define GPV7_BASE_ADDR 0x32700000
  31. #define OCRAM_ARB_BASE_ADDR 0x00900000
  32. #define OCRAM_ARB_END_ADDR 0x0091FFFF
  33. #define OCRAM_EPDC_BASE_ADDR 0x00920000
  34. #define OCRAM_EPDC_END_ADDR 0x0093FFFF
  35. #define OCRAM_PXP_BASE_ADDR 0x00940000
  36. #define OCRAM_PXP_END_ADDR 0x00947FFF
  37. #define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR
  38. #define IRAM_SIZE 0x00020000
  39. #define AIPS1_ARB_BASE_ADDR 0x30000000
  40. #define AIPS1_ARB_END_ADDR 0x303FFFFF
  41. #define AIPS2_ARB_BASE_ADDR 0x30400000
  42. #define AIPS2_ARB_END_ADDR 0x307FFFFF
  43. #define AIPS3_ARB_BASE_ADDR 0x30800000
  44. #define AIPS3_ARB_END_ADDR 0x30BFFFFF
  45. #define WEIM_ARB_BASE_ADDR 0x28000000
  46. #define WEIM_ARB_END_ADDR 0x2FFFFFFF
  47. #define QSPI0_ARB_BASE_ADDR 0x60000000
  48. #define QSPI0_ARB_END_ADDR 0x6FFFFFFF
  49. #define PCIE_ARB_BASE_ADDR 0x40000000
  50. #define PCIE_ARB_END_ADDR 0x4FFFFFFF
  51. #define PCIE_REG_BASE_ADDR 0x33800000
  52. #define PCIE_REG_END_ADDR 0x33803FFF
  53. #define MMDC0_ARB_BASE_ADDR 0x80000000
  54. #define MMDC0_ARB_END_ADDR 0xBFFFFFFF
  55. #define MMDC1_ARB_BASE_ADDR 0xC0000000
  56. #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
  57. /* Cortex-A9 MPCore private memory region */
  58. #define ARM_PERIPHBASE 0x31000000
  59. #define SCU_BASE_ADDR ARM_PERIPHBASE
  60. #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200)
  61. #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600)
  62. /* Defines for Blocks connected via AIPS (SkyBlue) */
  63. #define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
  64. #define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
  65. #define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
  66. /* DAP base-address */
  67. #define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR
  68. /* AIPS_TZ#1- On Platform */
  69. #define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000)
  70. /* AIPS_TZ#1- Off Platform */
  71. #define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000)
  72. #define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR
  73. #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000)
  74. #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000)
  75. #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000)
  76. #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000)
  77. #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000)
  78. #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000)
  79. #define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000)
  80. #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000)
  81. #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000)
  82. #define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000)
  83. #define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000)
  84. #define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000)
  85. #define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000)
  86. #define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR
  87. #define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000)
  88. #define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000)
  89. #define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000)
  90. #define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000)
  91. #define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000)
  92. #define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000)
  93. #define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR
  94. #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000)
  95. #define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000)
  96. #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000)
  97. #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000)
  98. #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000)
  99. #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000)
  100. #define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000)
  101. #define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000)
  102. #define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000)
  103. #define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000)
  104. #define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000)
  105. /* AIPS_TZ#2- On Platform */
  106. #define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000)
  107. /* AIPS_TZ#2- Off Platform */
  108. #define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000)
  109. #define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000)
  110. #define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000)
  111. #define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000)
  112. #define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000)
  113. #define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000)
  114. #define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000)
  115. #define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000)
  116. #define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000)
  117. #define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000)
  118. #define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000)
  119. #define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000)
  120. #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000)
  121. #define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000)
  122. #define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000)
  123. #define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR
  124. #define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000)
  125. #define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000)
  126. #define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000)
  127. #define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000)
  128. #define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000)
  129. #define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000)
  130. #define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000)
  131. #define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000)
  132. #define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000)
  133. #define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000)
  134. #define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000)
  135. #define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000)
  136. /* AIPS_TZ#3 - Global enable (0) */
  137. #define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000)
  138. #define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000)
  139. #define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000)
  140. #define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000)
  141. #define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000)
  142. #define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000)
  143. #define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000)
  144. #define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000)
  145. #define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000)
  146. #define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000)
  147. #define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000)
  148. /* AIPS_TZ#3- On Platform */
  149. #define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000)
  150. /* AIPS_TZ#3- Off Platform */
  151. #define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000)
  152. #define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR
  153. #define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000)
  154. #define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000)
  155. #define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000)
  156. #define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000)
  157. #define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000)
  158. #define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000)
  159. #define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000)
  160. #define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000)
  161. #define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000)
  162. #define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000)
  163. #define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000)
  164. #define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000)
  165. #define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000)
  166. #define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000)
  167. #define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000)
  168. #define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000)
  169. #define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000)
  170. #define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000)
  171. #define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000)
  172. #define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
  173. #define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
  174. #define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
  175. #define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
  176. #define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000)
  177. #define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000)
  178. #define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000)
  179. #define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000)
  180. #define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000)
  181. #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
  182. #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
  183. #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
  184. #define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR
  185. #define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR
  186. #define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR
  187. #define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR
  188. #define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR
  189. #define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR
  190. #define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR
  191. #define RDC_BASE_ADDR RDC_IPS_BASE_ADDR
  192. #define FEC_QUIRK_ENET_MAC
  193. #define SNVS_LPGPR 0x68
  194. #define CONFIG_SYS_FSL_SEC_OFFSET 0
  195. #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
  196. CONFIG_SYS_FSL_SEC_OFFSET)
  197. #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
  198. #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
  199. CONFIG_SYS_FSL_JR0_OFFSET)
  200. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  201. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  202. #include <asm/mach-imx/regs-lcdif.h>
  203. #include <asm/types.h>
  204. extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
  205. /* System Reset Controller (SRC) */
  206. struct src {
  207. u32 scr;
  208. u32 a7rcr0;
  209. u32 a7rcr1;
  210. u32 m4rcr;
  211. u32 reserved1;
  212. u32 ercr;
  213. u32 reserved2;
  214. u32 hsicphy_rcr;
  215. u32 usbophy1_rcr;
  216. u32 usbophy2_rcr;
  217. u32 mipiphy_rcr;
  218. u32 pciephy_rcr;
  219. u32 reserved3[10];
  220. u32 sbmr1;
  221. u32 srsr;
  222. u32 reserved4[2];
  223. u32 sisr;
  224. u32 simr;
  225. u32 sbmr2;
  226. u32 gpr1;
  227. u32 gpr2;
  228. u32 gpr3;
  229. u32 gpr4;
  230. u32 gpr5;
  231. u32 gpr6;
  232. u32 gpr7;
  233. u32 gpr8;
  234. u32 gpr9;
  235. u32 gpr10;
  236. u32 reserved5[985];
  237. u32 ddrc_rcr;
  238. };
  239. #define src_base ((struct src *)SRC_BASE_ADDR)
  240. #define SRC_M4_REG_OFFSET 0xC
  241. #define SRC_M4C_NON_SCLR_RST_OFFSET 0
  242. #define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
  243. #define SRC_M4_ENABLE_OFFSET 3
  244. #define SRC_M4_ENABLE_MASK BIT(3)
  245. #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1
  246. #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1)
  247. /* GPR0 Bit Fields */
  248. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u
  249. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0
  250. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u
  251. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1
  252. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u
  253. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2
  254. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u
  255. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3
  256. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u
  257. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4
  258. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u
  259. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5
  260. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
  261. #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6
  262. #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7)
  263. #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7
  264. /* GPR1 Bit Fields */
  265. #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
  266. #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0
  267. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u
  268. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1
  269. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK)
  270. #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u
  271. #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3
  272. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u
  273. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4
  274. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK)
  275. #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u
  276. #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6
  277. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u
  278. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7
  279. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK)
  280. #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u
  281. #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9
  282. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u
  283. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10
  284. #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK)
  285. #define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u
  286. #define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12
  287. #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
  288. #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
  289. #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u
  290. #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14
  291. #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u
  292. #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15
  293. #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u
  294. #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16
  295. #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u
  296. #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17
  297. #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u
  298. #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18
  299. #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u
  300. #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22
  301. #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u
  302. #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23
  303. #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u
  304. #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28
  305. #define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK)
  306. #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u
  307. #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30
  308. /* GPR2 Bit Fields */
  309. #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u
  310. #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0
  311. #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u
  312. #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1
  313. #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u
  314. #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2
  315. #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u
  316. #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3
  317. #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u
  318. #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4
  319. #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u
  320. #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5
  321. #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u
  322. #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6
  323. #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u
  324. #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7
  325. #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u
  326. #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8
  327. #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u
  328. #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9
  329. #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u
  330. #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10
  331. #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u
  332. #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11
  333. #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u
  334. #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12
  335. #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u
  336. #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13
  337. #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u
  338. #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14
  339. #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u
  340. #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15
  341. #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u
  342. #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16
  343. #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK)
  344. #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u
  345. #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24
  346. #define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u
  347. #define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25
  348. #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u
  349. #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26
  350. #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u
  351. #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27
  352. #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u
  353. #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28
  354. #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u
  355. #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29
  356. #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u
  357. #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30
  358. #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u
  359. #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31
  360. /* GPR3 Bit Fields */
  361. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u
  362. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0
  363. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u
  364. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1
  365. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u
  366. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2
  367. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u
  368. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3
  369. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u
  370. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4
  371. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u
  372. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5
  373. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u
  374. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6
  375. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u
  376. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7
  377. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u
  378. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8
  379. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u
  380. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9
  381. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u
  382. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10
  383. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u
  384. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11
  385. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u
  386. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12
  387. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u
  388. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13
  389. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u
  390. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14
  391. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u
  392. #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15
  393. #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u
  394. #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16
  395. #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u
  396. #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17
  397. #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u
  398. #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18
  399. #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u
  400. #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19
  401. #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u
  402. #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20
  403. #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u
  404. #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21
  405. #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u
  406. #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22
  407. #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u
  408. #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23
  409. #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u
  410. #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24
  411. #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u
  412. #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25
  413. #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u
  414. #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26
  415. #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u
  416. #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27
  417. #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u
  418. #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28
  419. #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u
  420. #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29
  421. #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u
  422. #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30
  423. #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u
  424. #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31
  425. /* GPR4 Bit Fields */
  426. #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u
  427. #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0
  428. #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u
  429. #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1
  430. #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u
  431. #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2
  432. #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u
  433. #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3
  434. #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u
  435. #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4
  436. #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u
  437. #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5
  438. #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u
  439. #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6
  440. #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u
  441. #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7
  442. #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u
  443. #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16
  444. #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u
  445. #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17
  446. #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u
  447. #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18
  448. #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u
  449. #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19
  450. #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u
  451. #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20
  452. #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u
  453. #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21
  454. #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u
  455. #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22
  456. #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u
  457. #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23
  458. #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u
  459. #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25
  460. #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK)
  461. #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u
  462. #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27
  463. #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK)
  464. /* GPR5 Bit Fields */
  465. #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u
  466. #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4
  467. #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u
  468. #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5
  469. #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u
  470. #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6
  471. #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u
  472. #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7
  473. #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u
  474. #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12
  475. #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u
  476. #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19
  477. #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u
  478. #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20
  479. #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u
  480. #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21
  481. #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u
  482. #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22
  483. #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u
  484. #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24
  485. #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u
  486. #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25
  487. #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u
  488. #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26
  489. #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u
  490. #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27
  491. #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u
  492. #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28
  493. #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u
  494. #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29
  495. #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u
  496. #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30
  497. #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u
  498. #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31
  499. /* GPR6 Bit Fields */
  500. #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u
  501. #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0
  502. #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u
  503. #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1
  504. #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u
  505. #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2
  506. #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u
  507. #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3
  508. /* GPR7 Bit Fields */
  509. #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u
  510. #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0
  511. #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u
  512. #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1
  513. #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u
  514. #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2
  515. #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u
  516. #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3
  517. #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u
  518. #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4
  519. #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK)
  520. #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u
  521. #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6
  522. #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u
  523. #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7
  524. #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u
  525. #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8
  526. #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u
  527. #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9
  528. #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u
  529. #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10
  530. #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK)
  531. #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u
  532. #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12
  533. #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u
  534. #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13
  535. /* GPR8 Bit Fields */
  536. #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u
  537. #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3
  538. #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK)
  539. #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u
  540. #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8
  541. /* GPR9 Bit Fields */
  542. #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u
  543. #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0
  544. #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu
  545. #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1
  546. #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK)
  547. /* GPR10 Bit Fields */
  548. #define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u
  549. #define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0
  550. #define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u
  551. #define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1
  552. #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u
  553. #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2
  554. #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u
  555. #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3
  556. #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u
  557. #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4
  558. #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK)
  559. /* GPR11 Bit Fields */
  560. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u
  561. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0
  562. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu
  563. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1
  564. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK)
  565. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u
  566. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6
  567. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u
  568. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7
  569. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK)
  570. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u
  571. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10
  572. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u
  573. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11
  574. #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK)
  575. /* GPR12 Bit Fields */
  576. #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u
  577. #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0
  578. #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u
  579. #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1
  580. #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u
  581. #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3
  582. #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u
  583. #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4
  584. #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u
  585. #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5
  586. #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u
  587. #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12
  588. #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK)
  589. #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
  590. #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17
  591. #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
  592. #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u
  593. #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21
  594. #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK)
  595. /* GPR13 Bit Fields */
  596. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u
  597. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0
  598. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u
  599. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1
  600. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u
  601. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2
  602. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u
  603. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3
  604. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u
  605. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4
  606. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u
  607. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5
  608. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u
  609. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6
  610. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u
  611. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7
  612. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u
  613. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8
  614. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u
  615. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9
  616. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u
  617. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10
  618. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u
  619. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11
  620. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u
  621. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12
  622. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u
  623. #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13
  624. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u
  625. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14
  626. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u
  627. #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15
  628. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u
  629. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16
  630. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK)
  631. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u
  632. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24
  633. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK)
  634. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u
  635. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28
  636. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u
  637. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29
  638. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u
  639. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30
  640. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u
  641. #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31
  642. /* GPR14 Bit Fields */
  643. #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u
  644. #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0
  645. #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u
  646. #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1
  647. /* GPR15 Bit Fields */
  648. #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u
  649. #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0
  650. #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u
  651. #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1
  652. #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu
  653. #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2
  654. #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK)
  655. #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u
  656. #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16
  657. #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK)
  658. /* GPR16 Bit Fields */
  659. #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u
  660. #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0
  661. #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK)
  662. #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u
  663. #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2
  664. #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u
  665. #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3
  666. #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u
  667. #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4
  668. #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u
  669. #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5
  670. #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u
  671. #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6
  672. #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK)
  673. #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u
  674. #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10
  675. #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u
  676. #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11
  677. #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u
  678. #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12
  679. #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u
  680. #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13
  681. #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK)
  682. #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u
  683. #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16
  684. #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u
  685. #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17
  686. #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u
  687. #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19
  688. #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK)
  689. #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u
  690. #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21
  691. #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u
  692. #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22
  693. #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u
  694. #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23
  695. /* GPR17 Bit Fields */
  696. #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu
  697. #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0
  698. #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK)
  699. #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u
  700. #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8
  701. #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK)
  702. /* GPR18 Bit Fields */
  703. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u
  704. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0
  705. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK)
  706. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u
  707. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3
  708. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK)
  709. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u
  710. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5
  711. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK)
  712. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u
  713. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8
  714. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK)
  715. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u
  716. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14
  717. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u
  718. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16
  719. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK)
  720. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u
  721. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24
  722. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK)
  723. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u
  724. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26
  725. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u
  726. #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27
  727. #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u
  728. #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28
  729. #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u
  730. #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29
  731. /* GPR19 Bit Fields */
  732. #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u
  733. #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0
  734. #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u
  735. #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8
  736. #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK)
  737. #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u
  738. #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16
  739. #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u
  740. #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17
  741. /* GPR20 Bit Fields */
  742. #define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu
  743. #define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0
  744. #define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK)
  745. #define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u
  746. #define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8
  747. #define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK)
  748. #define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u
  749. #define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16
  750. #define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK)
  751. #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u
  752. #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24
  753. #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u
  754. #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25
  755. #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u
  756. #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27
  757. #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK)
  758. /* GPR21 Bit Fields */
  759. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u
  760. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0
  761. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK)
  762. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u
  763. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3
  764. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK)
  765. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u
  766. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6
  767. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK)
  768. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u
  769. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9
  770. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK)
  771. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u
  772. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12
  773. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK)
  774. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u
  775. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15
  776. #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK)
  777. #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u
  778. #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18
  779. #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u
  780. #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19
  781. /* GPR22 Bit Fields */
  782. #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u
  783. #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16
  784. #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK)
  785. #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u
  786. #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24
  787. #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u
  788. #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25
  789. #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u
  790. #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26
  791. #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u
  792. #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27
  793. #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u
  794. #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28
  795. #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u
  796. #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29
  797. #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u
  798. #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31
  799. #define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4)
  800. #define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4)
  801. #define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4)
  802. struct iomuxc {
  803. u32 gpr[23];
  804. /* mux and pad registers */
  805. };
  806. struct iomuxc_gpr_base_regs {
  807. u32 gpr[23]; /* 0x000 */
  808. };
  809. /* ECSPI registers */
  810. struct cspi_regs {
  811. u32 rxdata;
  812. u32 txdata;
  813. u32 ctrl;
  814. u32 cfg;
  815. u32 intr;
  816. u32 dma;
  817. u32 stat;
  818. u32 period;
  819. };
  820. /*
  821. * CSPI register definitions
  822. */
  823. #define MXC_ECSPI
  824. #define MXC_CSPICTRL_EN (1 << 0)
  825. #define MXC_CSPICTRL_MODE (1 << 1)
  826. #define MXC_CSPICTRL_XCH (1 << 2)
  827. #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
  828. #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
  829. #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
  830. #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
  831. #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
  832. #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
  833. #define MXC_CSPICTRL_MAXBITS 0xfff
  834. #define MXC_CSPICTRL_TC (1 << 7)
  835. #define MXC_CSPICTRL_RXOVF (1 << 6)
  836. #define MXC_CSPIPERIOD_32KHZ (1 << 15)
  837. #define MAX_SPI_BYTES 32
  838. /* Bit position inside CTRL register to be associated with SS */
  839. #define MXC_CSPICTRL_CHAN 18
  840. /* Bit position inside CON register to be associated with SS */
  841. #define MXC_CSPICON_PHA 0 /* SCLK phase control */
  842. #define MXC_CSPICON_POL 4 /* SCLK polarity */
  843. #define MXC_CSPICON_SSPOL 12 /* SS polarity */
  844. #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
  845. #define MXC_SPI_BASE_ADDRESSES \
  846. ECSPI1_BASE_ADDR, \
  847. ECSPI2_BASE_ADDR, \
  848. ECSPI3_BASE_ADDR, \
  849. ECSPI4_BASE_ADDR
  850. #define CSU_INIT_SEC_LEVEL0 0x00FF00FF
  851. #define CSU_NUM_REGS 64
  852. struct ocotp_regs {
  853. u32 ctrl;
  854. u32 ctrl_set;
  855. u32 ctrl_clr;
  856. u32 ctrl_tog;
  857. u32 timing;
  858. u32 rsvd0[3];
  859. u32 data0;
  860. u32 rsvd1[3];
  861. u32 data1;
  862. u32 rsvd2[3];
  863. u32 data2;
  864. u32 rsvd3[3];
  865. u32 data3;
  866. u32 rsvd4[3];
  867. u32 read_ctrl;
  868. u32 rsvd5[3];
  869. u32 read_fuse_data0;
  870. u32 rsvd6[3];
  871. u32 read_fuse_data1;
  872. u32 rsvd7[3];
  873. u32 read_fuse_data2;
  874. u32 rsvd8[3];
  875. u32 read_fuse_data3;
  876. u32 rsvd9[3];
  877. u32 sw_sticky;
  878. u32 rsvd10[3];
  879. u32 scs;
  880. u32 scs_set;
  881. u32 scs_clr;
  882. u32 scs_tog;
  883. u32 crc_addr;
  884. u32 rsvd11[3];
  885. u32 crc_value;
  886. u32 rsvd12[3];
  887. u32 version;
  888. u32 rsvd13[0xc3];
  889. struct fuse_bank { /* offset 0x400 */
  890. u32 fuse_regs[0x10];
  891. } bank[16];
  892. };
  893. struct fuse_bank0_regs {
  894. u32 lock;
  895. u32 rsvd0[3];
  896. u32 tester0;
  897. u32 rsvd1[3];
  898. u32 tester1;
  899. u32 rsvd2[3];
  900. u32 tester2;
  901. u32 rsvd3[3];
  902. };
  903. struct fuse_bank1_regs {
  904. u32 tester3;
  905. u32 rsvd0[3];
  906. u32 tester4;
  907. u32 rsvd1[3];
  908. u32 tester5;
  909. u32 rsvd2[3];
  910. u32 cfg0;
  911. u32 rsvd3[3];
  912. };
  913. struct fuse_bank2_regs {
  914. u32 cfg1;
  915. u32 rsvd0[3];
  916. u32 cfg2;
  917. u32 rsvd1[3];
  918. u32 cfg3;
  919. u32 rsvd2[3];
  920. u32 cfg4;
  921. u32 rsvd3[3];
  922. };
  923. struct fuse_bank3_regs {
  924. u32 mem_trim0;
  925. u32 rsvd0[3];
  926. u32 mem_trim1;
  927. u32 rsvd1[3];
  928. u32 ana0;
  929. u32 rsvd2[3];
  930. u32 ana1;
  931. u32 rsvd3[3];
  932. };
  933. struct fuse_bank8_regs {
  934. u32 sjc_resp_low;
  935. u32 rsvd0[3];
  936. u32 sjc_resp_high;
  937. u32 rsvd1[3];
  938. u32 usb_id;
  939. u32 rsvd2[3];
  940. u32 field_return;
  941. u32 rsvd3[3];
  942. };
  943. struct fuse_bank9_regs {
  944. u32 mac_addr0;
  945. u32 rsvd0[3];
  946. u32 mac_addr1;
  947. u32 rsvd1[3];
  948. u32 mac_addr2;
  949. u32 rsvd2[7];
  950. };
  951. struct aipstz_regs {
  952. u32 mprot0;
  953. u32 mprot1;
  954. u32 rsvd[0xe];
  955. u32 opacr0;
  956. u32 opacr1;
  957. u32 opacr2;
  958. u32 opacr3;
  959. u32 opacr4;
  960. };
  961. struct wdog_regs {
  962. u16 wcr; /* Control */
  963. u16 wsr; /* Service */
  964. u16 wrsr; /* Reset Status */
  965. u16 wicr; /* Interrupt Control */
  966. u16 wmcr; /* Miscellaneous Control */
  967. };
  968. struct dbg_monitor_regs {
  969. u32 ctrl[4]; /* Control */
  970. u32 master_en[4]; /* Master enable */
  971. u32 irq[4]; /* IRQ */
  972. u32 trap_addr_low[4]; /* Trap address low */
  973. u32 trap_addr_high[4]; /* Trap address high */
  974. u32 trap_id[4]; /* Trap ID */
  975. u32 snvs_addr[4]; /* SNVS address */
  976. u32 snvs_data[4]; /* SNVS data */
  977. u32 snvs_info[4]; /* SNVS info */
  978. u32 version[4]; /* Version */
  979. };
  980. struct rdc_regs {
  981. u32 vir; /* Version information */
  982. u32 reserved1[8];
  983. u32 stat; /* Status */
  984. u32 intctrl; /* Interrupt and Control */
  985. u32 intstat; /* Interrupt Status */
  986. u32 reserved2[116];
  987. u32 mda[27]; /* Master Domain Assignment */
  988. u32 reserved3[101];
  989. u32 pdap[118]; /* Peripheral Domain Access Permissions */
  990. u32 reserved4[138];
  991. struct {
  992. u32 mrsa; /* Memory Region Start Address */
  993. u32 mrea; /* Memory Region End Address */
  994. u32 mrc; /* Memory Region Control */
  995. u32 mrvs; /* Memory Region Violation Status */
  996. } mem_region[52];
  997. };
  998. struct rdc_sema_regs {
  999. u8 gate[64]; /* Gate */
  1000. u16 rstgt; /* Reset Gate */
  1001. };
  1002. #define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR
  1003. #define LCDIF_CTRL_SFTRST (1 << 31)
  1004. #define LCDIF_CTRL_CLKGATE (1 << 30)
  1005. #define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
  1006. #define LCDIF_CTRL_READ_WRITEB (1 << 28)
  1007. #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
  1008. #define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
  1009. #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
  1010. #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
  1011. #define LCDIF_CTRL_DVI_MODE (1 << 20)
  1012. #define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
  1013. #define LCDIF_CTRL_VSYNC_MODE (1 << 18)
  1014. #define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
  1015. #define LCDIF_CTRL_DATA_SELECT (1 << 16)
  1016. #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
  1017. #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
  1018. #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
  1019. #define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
  1020. #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
  1021. #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
  1022. #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
  1023. #define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
  1024. #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
  1025. #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
  1026. #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
  1027. #define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
  1028. #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
  1029. #define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
  1030. #define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
  1031. #define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
  1032. #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
  1033. #define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
  1034. #define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
  1035. #define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
  1036. #define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
  1037. #define LCDIF_CTRL_RUN (1 << 0)
  1038. #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
  1039. #define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
  1040. #define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
  1041. #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
  1042. #define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
  1043. #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
  1044. #define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
  1045. #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
  1046. #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
  1047. #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
  1048. #define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
  1049. #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
  1050. #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
  1051. #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
  1052. #define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
  1053. #define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
  1054. #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
  1055. #define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
  1056. #define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
  1057. #define LCDIF_CTRL1_MODE86 (1 << 1)
  1058. #define LCDIF_CTRL1_RESET (1 << 0)
  1059. #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
  1060. #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
  1061. #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
  1062. #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
  1063. #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
  1064. #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
  1065. #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
  1066. #define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
  1067. #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
  1068. #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
  1069. #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
  1070. #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
  1071. #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
  1072. #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
  1073. #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
  1074. #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
  1075. #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
  1076. #define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
  1077. #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
  1078. #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
  1079. #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
  1080. #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
  1081. #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
  1082. #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
  1083. #define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
  1084. #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
  1085. #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
  1086. #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
  1087. #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
  1088. #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
  1089. #define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
  1090. #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
  1091. #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
  1092. #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
  1093. #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
  1094. #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
  1095. #define LCDIF_CUR_BUF_ADDR_OFFSET 0
  1096. #define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
  1097. #define LCDIF_NEXT_BUF_ADDR_OFFSET 0
  1098. #define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
  1099. #define LCDIF_TIMING_CMD_HOLD_OFFSET 24
  1100. #define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
  1101. #define LCDIF_TIMING_CMD_SETUP_OFFSET 16
  1102. #define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
  1103. #define LCDIF_TIMING_DATA_HOLD_OFFSET 8
  1104. #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
  1105. #define LCDIF_TIMING_DATA_SETUP_OFFSET 0
  1106. #define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
  1107. #define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
  1108. #define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
  1109. #define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
  1110. #define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
  1111. #define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
  1112. #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
  1113. #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
  1114. #define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
  1115. #define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
  1116. #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
  1117. #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
  1118. #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
  1119. #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
  1120. #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
  1121. #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
  1122. #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
  1123. #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
  1124. #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
  1125. #define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
  1126. #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
  1127. #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
  1128. #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
  1129. #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
  1130. #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
  1131. #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
  1132. #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
  1133. #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
  1134. #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
  1135. extern void check_cpu_temperature(void);
  1136. extern void pcie_power_up(void);
  1137. extern void pcie_power_off(void);
  1138. /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
  1139. * If boot from the other mode, USB0_PWD will keep reset value
  1140. */
  1141. #define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
  1142. readl(USBOTG2_IPS_BASE_ADDR + 0x158))
  1143. #define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
  1144. struct bootrom_sw_info {
  1145. u8 reserved_1;
  1146. u8 boot_dev_instance;
  1147. u8 boot_dev_type;
  1148. u8 reserved_2;
  1149. u32 arm_core_freq;
  1150. u32 axi_freq;
  1151. u32 ddr_freq;
  1152. u32 gpt1_freq;
  1153. u32 reserved_3[3];
  1154. };
  1155. #endif /* __ASSEMBLY__ */
  1156. #endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */