imx-regs.h 37 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
  4. */
  5. #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
  6. #define __ASM_ARCH_MX6_IMX_REGS_H__
  7. #define ARCH_MXC
  8. #define ROMCP_ARB_BASE_ADDR 0x00000000
  9. #define ROMCP_ARB_END_ADDR 0x000FFFFF
  10. #ifdef CONFIG_MX6SL
  11. #define GPU_2D_ARB_BASE_ADDR 0x02200000
  12. #define GPU_2D_ARB_END_ADDR 0x02203FFF
  13. #define OPENVG_ARB_BASE_ADDR 0x02204000
  14. #define OPENVG_ARB_END_ADDR 0x02207FFF
  15. #elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  16. #define CAAM_ARB_BASE_ADDR 0x00100000
  17. #define CAAM_ARB_END_ADDR 0x00107FFF
  18. #define GPU_ARB_BASE_ADDR 0x01800000
  19. #define GPU_ARB_END_ADDR 0x01803FFF
  20. #define APBH_DMA_ARB_BASE_ADDR 0x01804000
  21. #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
  22. #define M4_BOOTROM_BASE_ADDR 0x007F8000
  23. #elif !defined(CONFIG_MX6SLL)
  24. #define CAAM_ARB_BASE_ADDR 0x00100000
  25. #define CAAM_ARB_END_ADDR 0x00103FFF
  26. #define APBH_DMA_ARB_BASE_ADDR 0x00110000
  27. #define APBH_DMA_ARB_END_ADDR 0x00117FFF
  28. #define HDMI_ARB_BASE_ADDR 0x00120000
  29. #define HDMI_ARB_END_ADDR 0x00128FFF
  30. #define GPU_3D_ARB_BASE_ADDR 0x00130000
  31. #define GPU_3D_ARB_END_ADDR 0x00133FFF
  32. #define GPU_2D_ARB_BASE_ADDR 0x00134000
  33. #define GPU_2D_ARB_END_ADDR 0x00137FFF
  34. #define DTCP_ARB_BASE_ADDR 0x00138000
  35. #define DTCP_ARB_END_ADDR 0x0013BFFF
  36. #endif /* CONFIG_MX6SL */
  37. #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
  38. #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
  39. #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
  40. /* GPV - PL301 configuration ports */
  41. #if (defined(CONFIG_MX6SX) || \
  42. defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
  43. defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
  44. #define GPV2_BASE_ADDR 0x00D00000
  45. #define GPV3_BASE_ADDR 0x00E00000
  46. #define GPV4_BASE_ADDR 0x00F00000
  47. #define GPV5_BASE_ADDR 0x01000000
  48. #define GPV6_BASE_ADDR 0x01100000
  49. #define PCIE_ARB_BASE_ADDR 0x08000000
  50. #define PCIE_ARB_END_ADDR 0x08FFFFFF
  51. #else
  52. #define GPV2_BASE_ADDR 0x00200000
  53. #define GPV3_BASE_ADDR 0x00300000
  54. #define GPV4_BASE_ADDR 0x00800000
  55. #define PCIE_ARB_BASE_ADDR 0x01000000
  56. #define PCIE_ARB_END_ADDR 0x01FFFFFF
  57. #endif
  58. #define IRAM_BASE_ADDR 0x00900000
  59. #define SCU_BASE_ADDR 0x00A00000
  60. #define IC_INTERFACES_BASE_ADDR 0x00A00100
  61. #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
  62. #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
  63. #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
  64. #define L2_PL310_BASE 0x00A02000
  65. #define GPV0_BASE_ADDR 0x00B00000
  66. #define GPV1_BASE_ADDR 0x00C00000
  67. #define AIPS1_ARB_BASE_ADDR 0x02000000
  68. #define AIPS1_ARB_END_ADDR 0x020FFFFF
  69. #define AIPS2_ARB_BASE_ADDR 0x02100000
  70. #define AIPS2_ARB_END_ADDR 0x021FFFFF
  71. /* AIPS3 only on i.MX6SX */
  72. #define AIPS3_ARB_BASE_ADDR 0x02200000
  73. #define AIPS3_ARB_END_ADDR 0x022FFFFF
  74. #ifdef CONFIG_MX6SX
  75. #define WEIM_ARB_BASE_ADDR 0x50000000
  76. #define WEIM_ARB_END_ADDR 0x57FFFFFF
  77. #define QSPI0_AMBA_BASE 0x60000000
  78. #define QSPI0_AMBA_END 0x6FFFFFFF
  79. #define QSPI1_AMBA_BASE 0x70000000
  80. #define QSPI1_AMBA_END 0x7FFFFFFF
  81. #elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  82. #define WEIM_ARB_BASE_ADDR 0x50000000
  83. #define WEIM_ARB_END_ADDR 0x57FFFFFF
  84. #define QSPI0_AMBA_BASE 0x60000000
  85. #define QSPI0_AMBA_END 0x6FFFFFFF
  86. #elif !defined(CONFIG_MX6SLL)
  87. #define SATA_ARB_BASE_ADDR 0x02200000
  88. #define SATA_ARB_END_ADDR 0x02203FFF
  89. #define OPENVG_ARB_BASE_ADDR 0x02204000
  90. #define OPENVG_ARB_END_ADDR 0x02207FFF
  91. #define HSI_ARB_BASE_ADDR 0x02208000
  92. #define HSI_ARB_END_ADDR 0x0220BFFF
  93. #define IPU1_ARB_BASE_ADDR 0x02400000
  94. #define IPU1_ARB_END_ADDR 0x027FFFFF
  95. #define IPU2_ARB_BASE_ADDR 0x02800000
  96. #define IPU2_ARB_END_ADDR 0x02BFFFFF
  97. #define WEIM_ARB_BASE_ADDR 0x08000000
  98. #define WEIM_ARB_END_ADDR 0x0FFFFFFF
  99. #endif
  100. #if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
  101. defined(CONFIG_MX6SX) || \
  102. defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  103. #define MMDC0_ARB_BASE_ADDR 0x80000000
  104. #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
  105. #define MMDC1_ARB_BASE_ADDR 0xC0000000
  106. #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
  107. #else
  108. #define MMDC0_ARB_BASE_ADDR 0x10000000
  109. #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
  110. #define MMDC1_ARB_BASE_ADDR 0x80000000
  111. #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
  112. #endif
  113. #ifndef CONFIG_MX6SX
  114. #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
  115. #define IPU_SOC_OFFSET 0x00200000
  116. #endif
  117. /* Defines for Blocks connected via AIPS (SkyBlue) */
  118. #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
  119. #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
  120. #define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
  121. #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
  122. #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
  123. #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
  124. #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
  125. #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
  126. #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
  127. #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
  128. #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
  129. #define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
  130. #define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
  131. #define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
  132. #define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
  133. #define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
  134. #define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
  135. #define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
  136. #define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
  137. #define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
  138. #ifndef CONFIG_MX6SX
  139. #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
  140. #endif
  141. #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
  142. #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
  143. #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
  144. #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
  145. #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
  146. #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
  147. #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
  148. #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
  149. #ifndef CONFIG_MX6SX
  150. #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
  151. #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
  152. #endif
  153. #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
  154. #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
  155. #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
  156. #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
  157. #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
  158. #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
  159. #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
  160. #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
  161. /* QOSC on i.MX6SLL */
  162. #define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
  163. #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
  164. #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
  165. #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
  166. #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
  167. #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
  168. #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
  169. #define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
  170. #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
  171. #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
  172. #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
  173. #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
  174. #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
  175. #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
  176. #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
  177. #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
  178. #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
  179. #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
  180. #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
  181. #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
  182. #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
  183. #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
  184. #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
  185. #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
  186. #ifdef CONFIG_MX6SLL
  187. #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
  188. #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
  189. #define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
  190. #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
  191. #define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
  192. #elif defined(CONFIG_MX6SL)
  193. #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
  194. #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
  195. #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
  196. #elif defined(CONFIG_MX6SX)
  197. #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
  198. #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
  199. #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
  200. #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
  201. #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
  202. #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
  203. #else
  204. #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
  205. #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
  206. #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
  207. #endif
  208. #define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
  209. #define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
  210. #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
  211. #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
  212. #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
  213. #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
  214. #if defined(CONFIG_MX6UL)
  215. #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
  216. #else
  217. #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
  218. #endif
  219. #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
  220. #define CONFIG_SYS_FSL_SEC_OFFSET 0
  221. #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
  222. CONFIG_SYS_FSL_SEC_OFFSET)
  223. #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
  224. #define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
  225. CONFIG_SYS_FSL_JR0_OFFSET)
  226. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  227. #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
  228. #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
  229. #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
  230. #ifdef CONFIG_MX6SL
  231. #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
  232. #else
  233. #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
  234. #endif
  235. #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
  236. #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
  237. #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
  238. #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
  239. #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
  240. #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
  241. #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
  242. #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
  243. #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
  244. /* i.MX6SL/SLL */
  245. #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
  246. #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  247. #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
  248. #else
  249. /* i.MX6SX */
  250. #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
  251. #endif
  252. /* i.MX6DQ/SDL */
  253. #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
  254. #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
  255. #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
  256. #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
  257. #ifdef CONFIG_MX6SLL
  258. #define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
  259. #define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
  260. #endif
  261. #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
  262. #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
  263. #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
  264. #define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
  265. #ifdef CONFIG_MX6SX
  266. #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
  267. #else
  268. #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
  269. #endif
  270. #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
  271. #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  272. #define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
  273. #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
  274. #define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
  275. #elif defined(CONFIG_MX6SX)
  276. #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
  277. #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
  278. #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
  279. #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
  280. #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
  281. #else
  282. #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
  283. #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
  284. #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
  285. #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
  286. #endif
  287. #define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
  288. #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
  289. #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
  290. #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
  291. #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
  292. #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
  293. #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
  294. #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
  295. /* i.MX6SLL */
  296. #define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
  297. #ifdef CONFIG_MX6SX
  298. #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
  299. #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
  300. #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
  301. #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
  302. #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
  303. #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
  304. #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
  305. #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
  306. #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
  307. #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
  308. #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
  309. #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
  310. #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
  311. #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
  312. #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
  313. #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
  314. #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
  315. #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
  316. #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
  317. #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
  318. #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
  319. #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
  320. #elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  321. #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
  322. #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
  323. #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
  324. #define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
  325. #define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
  326. #define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
  327. #define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
  328. #endif
  329. #define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000)
  330. /* Only for i.MX6SX */
  331. #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
  332. #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
  333. #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
  334. #if !(defined(CONFIG_MX6SX) || \
  335. defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
  336. defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
  337. #define IRAM_SIZE 0x00040000
  338. #else
  339. #define IRAM_SIZE 0x00020000
  340. #endif
  341. #define FEC_QUIRK_ENET_MAC
  342. #include <asm/mach-imx/regs-lcdif.h>
  343. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  344. #include <asm/types.h>
  345. /* only for i.MX6SX/UL */
  346. #define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \
  347. MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
  348. #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
  349. MX6SLL_LCDIF_BASE_ADDR : \
  350. (is_cpu_type(MXC_CPU_MX6SL)) ? \
  351. MX6SL_LCDIF_BASE_ADDR : \
  352. ((is_cpu_type(MXC_CPU_MX6UL)) ? \
  353. MX6UL_LCDIF1_BASE_ADDR : \
  354. ((is_mx6ull()) ? \
  355. MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
  356. extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
  357. #define SRC_SCR_CORE_1_RESET_OFFSET 14
  358. #define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
  359. #define SRC_SCR_CORE_2_RESET_OFFSET 15
  360. #define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
  361. #define SRC_SCR_CORE_3_RESET_OFFSET 16
  362. #define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
  363. #define SRC_SCR_CORE_1_ENABLE_OFFSET 22
  364. #define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
  365. #define SRC_SCR_CORE_2_ENABLE_OFFSET 23
  366. #define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
  367. #define SRC_SCR_CORE_3_ENABLE_OFFSET 24
  368. #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
  369. struct rdc_regs {
  370. u32 vir; /* Version information */
  371. u32 reserved1[8];
  372. u32 stat; /* Status */
  373. u32 intctrl; /* Interrupt and Control */
  374. u32 intstat; /* Interrupt Status */
  375. u32 reserved2[116];
  376. u32 mda[32]; /* Master Domain Assignment */
  377. u32 reserved3[96];
  378. u32 pdap[104]; /* Peripheral Domain Access Permissions */
  379. u32 reserved4[88];
  380. struct {
  381. u32 mrsa; /* Memory Region Start Address */
  382. u32 mrea; /* Memory Region End Address */
  383. u32 mrc; /* Memory Region Control */
  384. u32 mrvs; /* Memory Region Violation Status */
  385. } mem_region[55];
  386. };
  387. struct rdc_sema_regs {
  388. u8 gate[64]; /* Gate */
  389. u16 rstgt; /* Reset Gate */
  390. };
  391. /* WEIM registers */
  392. struct weim {
  393. u32 cs0gcr1;
  394. u32 cs0gcr2;
  395. u32 cs0rcr1;
  396. u32 cs0rcr2;
  397. u32 cs0wcr1;
  398. u32 cs0wcr2;
  399. u32 cs1gcr1;
  400. u32 cs1gcr2;
  401. u32 cs1rcr1;
  402. u32 cs1rcr2;
  403. u32 cs1wcr1;
  404. u32 cs1wcr2;
  405. u32 cs2gcr1;
  406. u32 cs2gcr2;
  407. u32 cs2rcr1;
  408. u32 cs2rcr2;
  409. u32 cs2wcr1;
  410. u32 cs2wcr2;
  411. u32 cs3gcr1;
  412. u32 cs3gcr2;
  413. u32 cs3rcr1;
  414. u32 cs3rcr2;
  415. u32 cs3wcr1;
  416. u32 cs3wcr2;
  417. u32 unused[12];
  418. u32 wcr;
  419. u32 wiar;
  420. u32 ear;
  421. };
  422. /* System Reset Controller (SRC) */
  423. struct src {
  424. u32 scr;
  425. u32 sbmr1;
  426. u32 srsr;
  427. u32 reserved1[2];
  428. u32 sisr;
  429. u32 simr;
  430. u32 sbmr2;
  431. u32 gpr1;
  432. u32 gpr2;
  433. u32 gpr3;
  434. u32 gpr4;
  435. u32 gpr5;
  436. u32 gpr6;
  437. u32 gpr7;
  438. u32 gpr8;
  439. u32 gpr9;
  440. u32 gpr10;
  441. };
  442. #define src_base ((struct src *)SRC_BASE_ADDR)
  443. #define SRC_M4_REG_OFFSET 0
  444. #define SRC_M4_ENABLE_OFFSET 22
  445. #define SRC_M4_ENABLE_MASK BIT(22)
  446. #define SRC_M4C_NON_SCLR_RST_OFFSET 4
  447. #define SRC_M4C_NON_SCLR_RST_MASK BIT(4)
  448. /* GPR1 bitfields */
  449. #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
  450. #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
  451. #define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
  452. #define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
  453. #define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
  454. #define IOMUXC_GPR1_DPI_OFF BIT(24)
  455. #define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
  456. #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
  457. #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
  458. #define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
  459. #define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
  460. #define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
  461. #define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
  462. #define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
  463. #define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
  464. #define IOMUXC_GPR1_PCIE_INT BIT(14)
  465. #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
  466. #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
  467. #define IOMUXC_GPR1_GINT BIT(12)
  468. #define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
  469. #define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
  470. #define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
  471. #define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
  472. #define IOMUXC_GPR1_ACT_CS3 BIT(9)
  473. #define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
  474. #define IOMUXC_GPR1_ACT_CS2 BIT(6)
  475. #define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
  476. #define IOMUXC_GPR1_ACT_CS1 BIT(3)
  477. #define IOMUXC_GPR1_ADDRS0_OFFSET (1)
  478. #define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
  479. #define IOMUXC_GPR1_ACT_CS0 BIT(0)
  480. /* GPR3 bitfields */
  481. #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
  482. #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
  483. #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
  484. #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
  485. #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
  486. #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
  487. #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
  488. #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
  489. #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
  490. #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
  491. #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
  492. #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
  493. #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
  494. #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
  495. #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
  496. #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
  497. #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
  498. #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
  499. #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
  500. #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
  501. #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
  502. #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
  503. #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
  504. #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
  505. #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
  506. #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
  507. #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
  508. #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
  509. #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
  510. #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
  511. #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
  512. #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
  513. #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
  514. #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
  515. #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
  516. #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
  517. #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
  518. #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
  519. #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
  520. #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
  521. /* gpr12 bitfields */
  522. #define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
  523. #define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
  524. #define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
  525. #define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
  526. #define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
  527. #define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
  528. #define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
  529. struct iomuxc {
  530. #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  531. u8 reserved[0x4000];
  532. #endif
  533. u32 gpr[14];
  534. };
  535. struct gpc {
  536. u32 cntr;
  537. u32 pgr;
  538. u32 imr1;
  539. u32 imr2;
  540. u32 imr3;
  541. u32 imr4;
  542. u32 isr1;
  543. u32 isr2;
  544. u32 isr3;
  545. u32 isr4;
  546. };
  547. #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
  548. #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
  549. #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
  550. #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
  551. #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
  552. #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
  553. #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
  554. #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
  555. #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
  556. #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
  557. #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
  558. #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
  559. #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
  560. #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
  561. #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
  562. #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
  563. #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
  564. #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
  565. #define IOMUXC_GPR2_BITMAP_SPWG 0
  566. #define IOMUXC_GPR2_BITMAP_JEIDA 1
  567. #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
  568. #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
  569. #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
  570. #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
  571. #define IOMUXC_GPR2_DATA_WIDTH_18 0
  572. #define IOMUXC_GPR2_DATA_WIDTH_24 1
  573. #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
  574. #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
  575. #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
  576. #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
  577. #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
  578. #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  579. #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  580. #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  581. #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
  582. #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  583. #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  584. #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  585. #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
  586. #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
  587. #define IOMUXC_GPR2_MODE_DISABLED 0
  588. #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
  589. #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
  590. #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
  591. #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  592. #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  593. #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  594. #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  595. #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
  596. #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  597. #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  598. #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  599. #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  600. /* ECSPI registers */
  601. struct cspi_regs {
  602. u32 rxdata;
  603. u32 txdata;
  604. u32 ctrl;
  605. u32 cfg;
  606. u32 intr;
  607. u32 dma;
  608. u32 stat;
  609. u32 period;
  610. };
  611. /*
  612. * CSPI register definitions
  613. */
  614. #define MXC_ECSPI
  615. #define MXC_CSPICTRL_EN (1 << 0)
  616. #define MXC_CSPICTRL_MODE (1 << 1)
  617. #define MXC_CSPICTRL_XCH (1 << 2)
  618. #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
  619. #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
  620. #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
  621. #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
  622. #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
  623. #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
  624. #define MXC_CSPICTRL_MAXBITS 0xfff
  625. #define MXC_CSPICTRL_TC (1 << 7)
  626. #define MXC_CSPICTRL_RXOVF (1 << 6)
  627. #define MXC_CSPIPERIOD_32KHZ (1 << 15)
  628. #define MAX_SPI_BYTES 32
  629. #define SPI_MAX_NUM 4
  630. /* Bit position inside CTRL register to be associated with SS */
  631. #define MXC_CSPICTRL_CHAN 18
  632. /* Bit position inside CON register to be associated with SS */
  633. #define MXC_CSPICON_PHA 0 /* SCLK phase control */
  634. #define MXC_CSPICON_POL 4 /* SCLK polarity */
  635. #define MXC_CSPICON_SSPOL 12 /* SS polarity */
  636. #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
  637. #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
  638. defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  639. #define MXC_SPI_BASE_ADDRESSES \
  640. ECSPI1_BASE_ADDR, \
  641. ECSPI2_BASE_ADDR, \
  642. ECSPI3_BASE_ADDR, \
  643. ECSPI4_BASE_ADDR
  644. #else
  645. #define MXC_SPI_BASE_ADDRESSES \
  646. ECSPI1_BASE_ADDR, \
  647. ECSPI2_BASE_ADDR, \
  648. ECSPI3_BASE_ADDR, \
  649. ECSPI4_BASE_ADDR, \
  650. ECSPI5_BASE_ADDR
  651. #endif
  652. struct ocotp_regs {
  653. u32 ctrl;
  654. u32 ctrl_set;
  655. u32 ctrl_clr;
  656. u32 ctrl_tog;
  657. u32 timing;
  658. u32 rsvd0[3];
  659. u32 data;
  660. u32 rsvd1[3];
  661. u32 read_ctrl;
  662. u32 rsvd2[3];
  663. u32 read_fuse_data;
  664. u32 rsvd3[3];
  665. u32 sw_sticky;
  666. u32 rsvd4[3];
  667. u32 scs;
  668. u32 scs_set;
  669. u32 scs_clr;
  670. u32 scs_tog;
  671. u32 crc_addr;
  672. u32 rsvd5[3];
  673. u32 crc_value;
  674. u32 rsvd6[3];
  675. u32 version;
  676. u32 rsvd7[0xdb];
  677. /* fuse banks */
  678. struct fuse_bank {
  679. u32 fuse_regs[0x20];
  680. } bank[0];
  681. };
  682. struct fuse_bank0_regs {
  683. u32 lock;
  684. u32 rsvd0[3];
  685. u32 uid_low;
  686. u32 rsvd1[3];
  687. u32 uid_high;
  688. u32 rsvd2[3];
  689. u32 cfg2;
  690. u32 rsvd3[3];
  691. u32 cfg3;
  692. u32 rsvd4[3];
  693. u32 cfg4;
  694. u32 rsvd5[3];
  695. u32 cfg5;
  696. u32 rsvd6[3];
  697. u32 cfg6;
  698. u32 rsvd7[3];
  699. };
  700. struct fuse_bank1_regs {
  701. u32 mem0;
  702. u32 rsvd0[3];
  703. u32 mem1;
  704. u32 rsvd1[3];
  705. u32 mem2;
  706. u32 rsvd2[3];
  707. u32 mem3;
  708. u32 rsvd3[3];
  709. u32 mem4;
  710. u32 rsvd4[3];
  711. u32 ana0;
  712. u32 rsvd5[3];
  713. u32 ana1;
  714. u32 rsvd6[3];
  715. u32 ana2;
  716. u32 rsvd7[3];
  717. };
  718. struct fuse_bank4_regs {
  719. u32 sjc_resp_low;
  720. u32 rsvd0[3];
  721. u32 sjc_resp_high;
  722. u32 rsvd1[3];
  723. u32 mac_addr0;
  724. u32 rsvd2[3];
  725. u32 mac_addr1;
  726. u32 rsvd3[3];
  727. u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
  728. u32 rsvd4[7];
  729. u32 gp1;
  730. u32 rsvd5[3];
  731. u32 gp2;
  732. u32 rsvd6[3];
  733. };
  734. struct aipstz_regs {
  735. u32 mprot0;
  736. u32 mprot1;
  737. u32 rsvd[0xe];
  738. u32 opacr0;
  739. u32 opacr1;
  740. u32 opacr2;
  741. u32 opacr3;
  742. u32 opacr4;
  743. };
  744. struct anatop_regs {
  745. u32 pll_sys; /* 0x000 */
  746. u32 pll_sys_set; /* 0x004 */
  747. u32 pll_sys_clr; /* 0x008 */
  748. u32 pll_sys_tog; /* 0x00c */
  749. u32 usb1_pll_480_ctrl; /* 0x010 */
  750. u32 usb1_pll_480_ctrl_set; /* 0x014 */
  751. u32 usb1_pll_480_ctrl_clr; /* 0x018 */
  752. u32 usb1_pll_480_ctrl_tog; /* 0x01c */
  753. u32 usb2_pll_480_ctrl; /* 0x020 */
  754. u32 usb2_pll_480_ctrl_set; /* 0x024 */
  755. u32 usb2_pll_480_ctrl_clr; /* 0x028 */
  756. u32 usb2_pll_480_ctrl_tog; /* 0x02c */
  757. u32 pll_528; /* 0x030 */
  758. u32 pll_528_set; /* 0x034 */
  759. u32 pll_528_clr; /* 0x038 */
  760. u32 pll_528_tog; /* 0x03c */
  761. u32 pll_528_ss; /* 0x040 */
  762. u32 rsvd0[3];
  763. u32 pll_528_num; /* 0x050 */
  764. u32 rsvd1[3];
  765. u32 pll_528_denom; /* 0x060 */
  766. u32 rsvd2[3];
  767. u32 pll_audio; /* 0x070 */
  768. u32 pll_audio_set; /* 0x074 */
  769. u32 pll_audio_clr; /* 0x078 */
  770. u32 pll_audio_tog; /* 0x07c */
  771. u32 pll_audio_num; /* 0x080 */
  772. u32 rsvd3[3];
  773. u32 pll_audio_denom; /* 0x090 */
  774. u32 rsvd4[3];
  775. u32 pll_video; /* 0x0a0 */
  776. u32 pll_video_set; /* 0x0a4 */
  777. u32 pll_video_clr; /* 0x0a8 */
  778. u32 pll_video_tog; /* 0x0ac */
  779. u32 pll_video_num; /* 0x0b0 */
  780. u32 rsvd5[3];
  781. u32 pll_video_denom; /* 0x0c0 */
  782. u32 rsvd6[3];
  783. u32 pll_mlb; /* 0x0d0 */
  784. u32 pll_mlb_set; /* 0x0d4 */
  785. u32 pll_mlb_clr; /* 0x0d8 */
  786. u32 pll_mlb_tog; /* 0x0dc */
  787. u32 pll_enet; /* 0x0e0 */
  788. u32 pll_enet_set; /* 0x0e4 */
  789. u32 pll_enet_clr; /* 0x0e8 */
  790. u32 pll_enet_tog; /* 0x0ec */
  791. u32 pfd_480; /* 0x0f0 */
  792. u32 pfd_480_set; /* 0x0f4 */
  793. u32 pfd_480_clr; /* 0x0f8 */
  794. u32 pfd_480_tog; /* 0x0fc */
  795. u32 pfd_528; /* 0x100 */
  796. u32 pfd_528_set; /* 0x104 */
  797. u32 pfd_528_clr; /* 0x108 */
  798. u32 pfd_528_tog; /* 0x10c */
  799. u32 reg_1p1; /* 0x110 */
  800. u32 reg_1p1_set; /* 0x114 */
  801. u32 reg_1p1_clr; /* 0x118 */
  802. u32 reg_1p1_tog; /* 0x11c */
  803. u32 reg_3p0; /* 0x120 */
  804. u32 reg_3p0_set; /* 0x124 */
  805. u32 reg_3p0_clr; /* 0x128 */
  806. u32 reg_3p0_tog; /* 0x12c */
  807. u32 reg_2p5; /* 0x130 */
  808. u32 reg_2p5_set; /* 0x134 */
  809. u32 reg_2p5_clr; /* 0x138 */
  810. u32 reg_2p5_tog; /* 0x13c */
  811. u32 reg_core; /* 0x140 */
  812. u32 reg_core_set; /* 0x144 */
  813. u32 reg_core_clr; /* 0x148 */
  814. u32 reg_core_tog; /* 0x14c */
  815. u32 ana_misc0; /* 0x150 */
  816. u32 ana_misc0_set; /* 0x154 */
  817. u32 ana_misc0_clr; /* 0x158 */
  818. u32 ana_misc0_tog; /* 0x15c */
  819. u32 ana_misc1; /* 0x160 */
  820. u32 ana_misc1_set; /* 0x164 */
  821. u32 ana_misc1_clr; /* 0x168 */
  822. u32 ana_misc1_tog; /* 0x16c */
  823. u32 ana_misc2; /* 0x170 */
  824. u32 ana_misc2_set; /* 0x174 */
  825. u32 ana_misc2_clr; /* 0x178 */
  826. u32 ana_misc2_tog; /* 0x17c */
  827. u32 tempsense0; /* 0x180 */
  828. u32 tempsense0_set; /* 0x184 */
  829. u32 tempsense0_clr; /* 0x188 */
  830. u32 tempsense0_tog; /* 0x18c */
  831. u32 tempsense1; /* 0x190 */
  832. u32 tempsense1_set; /* 0x194 */
  833. u32 tempsense1_clr; /* 0x198 */
  834. u32 tempsense1_tog; /* 0x19c */
  835. u32 usb1_vbus_detect; /* 0x1a0 */
  836. u32 usb1_vbus_detect_set; /* 0x1a4 */
  837. u32 usb1_vbus_detect_clr; /* 0x1a8 */
  838. u32 usb1_vbus_detect_tog; /* 0x1ac */
  839. u32 usb1_chrg_detect; /* 0x1b0 */
  840. u32 usb1_chrg_detect_set; /* 0x1b4 */
  841. u32 usb1_chrg_detect_clr; /* 0x1b8 */
  842. u32 usb1_chrg_detect_tog; /* 0x1bc */
  843. u32 usb1_vbus_det_stat; /* 0x1c0 */
  844. u32 usb1_vbus_det_stat_set; /* 0x1c4 */
  845. u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
  846. u32 usb1_vbus_det_stat_tog; /* 0x1cc */
  847. u32 usb1_chrg_det_stat; /* 0x1d0 */
  848. u32 usb1_chrg_det_stat_set; /* 0x1d4 */
  849. u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
  850. u32 usb1_chrg_det_stat_tog; /* 0x1dc */
  851. u32 usb1_loopback; /* 0x1e0 */
  852. u32 usb1_loopback_set; /* 0x1e4 */
  853. u32 usb1_loopback_clr; /* 0x1e8 */
  854. u32 usb1_loopback_tog; /* 0x1ec */
  855. u32 usb1_misc; /* 0x1f0 */
  856. u32 usb1_misc_set; /* 0x1f4 */
  857. u32 usb1_misc_clr; /* 0x1f8 */
  858. u32 usb1_misc_tog; /* 0x1fc */
  859. u32 usb2_vbus_detect; /* 0x200 */
  860. u32 usb2_vbus_detect_set; /* 0x204 */
  861. u32 usb2_vbus_detect_clr; /* 0x208 */
  862. u32 usb2_vbus_detect_tog; /* 0x20c */
  863. u32 usb2_chrg_detect; /* 0x210 */
  864. u32 usb2_chrg_detect_set; /* 0x214 */
  865. u32 usb2_chrg_detect_clr; /* 0x218 */
  866. u32 usb2_chrg_detect_tog; /* 0x21c */
  867. u32 usb2_vbus_det_stat; /* 0x220 */
  868. u32 usb2_vbus_det_stat_set; /* 0x224 */
  869. u32 usb2_vbus_det_stat_clr; /* 0x228 */
  870. u32 usb2_vbus_det_stat_tog; /* 0x22c */
  871. u32 usb2_chrg_det_stat; /* 0x230 */
  872. u32 usb2_chrg_det_stat_set; /* 0x234 */
  873. u32 usb2_chrg_det_stat_clr; /* 0x238 */
  874. u32 usb2_chrg_det_stat_tog; /* 0x23c */
  875. u32 usb2_loopback; /* 0x240 */
  876. u32 usb2_loopback_set; /* 0x244 */
  877. u32 usb2_loopback_clr; /* 0x248 */
  878. u32 usb2_loopback_tog; /* 0x24c */
  879. u32 usb2_misc; /* 0x250 */
  880. u32 usb2_misc_set; /* 0x254 */
  881. u32 usb2_misc_clr; /* 0x258 */
  882. u32 usb2_misc_tog; /* 0x25c */
  883. u32 digprog; /* 0x260 */
  884. u32 reserved1[7];
  885. u32 digprog_sololite; /* 0x280 */
  886. };
  887. #define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
  888. #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
  889. #define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
  890. #define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
  891. #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
  892. #define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
  893. struct wdog_regs {
  894. u16 wcr; /* Control */
  895. u16 wsr; /* Service */
  896. u16 wrsr; /* Reset Status */
  897. u16 wicr; /* Interrupt Control */
  898. u16 wmcr; /* Miscellaneous Control */
  899. };
  900. #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
  901. #define PWMCR_DOZEEN (1 << 24)
  902. #define PWMCR_WAITEN (1 << 23)
  903. #define PWMCR_DBGEN (1 << 22)
  904. #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
  905. #define PWMCR_CLKSRC_IPG (1 << 16)
  906. #define PWMCR_EN (1 << 0)
  907. struct pwm_regs {
  908. u32 cr;
  909. u32 sr;
  910. u32 ir;
  911. u32 sar;
  912. u32 pr;
  913. u32 cnr;
  914. };
  915. /*
  916. * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
  917. * If boot from the other mode, USB0_PWD will keep reset value
  918. */
  919. #define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
  920. #endif /* __ASSEMBLY__ */
  921. #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */