imx-regs.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __ASM_ARCH_MX5_IMX_REGS_H__
  6. #define __ASM_ARCH_MX5_IMX_REGS_H__
  7. #define ARCH_MXC
  8. #if defined(CONFIG_MX51)
  9. #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
  10. #define IPU_SOC_BASE_ADDR 0x40000000
  11. #define IPU_SOC_OFFSET 0x1E000000
  12. #define SPBA0_BASE_ADDR 0x70000000
  13. #define AIPS1_BASE_ADDR 0x73F00000
  14. #define AIPS2_BASE_ADDR 0x83F00000
  15. #define CSD0_BASE_ADDR 0x90000000
  16. #define CSD1_BASE_ADDR 0xA0000000
  17. #define NFC_BASE_ADDR_AXI 0xCFFF0000
  18. #define CS1_BASE_ADDR 0xB8000000
  19. #elif defined(CONFIG_MX53)
  20. #define IPU_SOC_BASE_ADDR 0x18000000
  21. #define IPU_SOC_OFFSET 0x06000000
  22. #define SPBA0_BASE_ADDR 0x50000000
  23. #define AIPS1_BASE_ADDR 0x53F00000
  24. #define AIPS2_BASE_ADDR 0x63F00000
  25. #define CSD0_BASE_ADDR 0x70000000
  26. #define CSD1_BASE_ADDR 0xB0000000
  27. #define NFC_BASE_ADDR_AXI 0xF7FF0000
  28. #define IRAM_BASE_ADDR 0xF8000000
  29. #define CS1_BASE_ADDR 0xF4000000
  30. #define SATA_BASE_ADDR 0x10000000
  31. #else
  32. #error "CPU_TYPE not defined"
  33. #endif
  34. #define IRAM_SIZE 0x00020000 /* 128 KB */
  35. /*
  36. * SPBA global module enabled #0
  37. */
  38. #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
  39. #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
  40. #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
  41. #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
  42. #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
  43. #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
  44. #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
  45. #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
  46. #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
  47. #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
  48. #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
  49. #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
  50. /*
  51. * AIPS 1
  52. */
  53. #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
  54. #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
  55. #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
  56. #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
  57. #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
  58. #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
  59. #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
  60. #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
  61. #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
  62. #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
  63. #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
  64. #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
  65. #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
  66. #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
  67. #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
  68. #define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000)
  69. #define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000)
  70. #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
  71. #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
  72. #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
  73. #if defined(CONFIG_MX53)
  74. #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
  75. #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
  76. #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
  77. #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
  78. #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
  79. #endif
  80. /*
  81. * AIPS 2
  82. */
  83. #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
  84. #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
  85. #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
  86. #ifdef CONFIG_MX53
  87. #define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000)
  88. #endif
  89. #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
  90. #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
  91. #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
  92. #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
  93. #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
  94. #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
  95. #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
  96. #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
  97. #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
  98. #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
  99. #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
  100. #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
  101. #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
  102. #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
  103. #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
  104. #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
  105. #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
  106. #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
  107. #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
  108. #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
  109. #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
  110. #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
  111. #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
  112. #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
  113. #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
  114. #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
  115. #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
  116. #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
  117. #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
  118. #if defined(CONFIG_MX53)
  119. #define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
  120. #endif
  121. /*
  122. * WEIM CSnGCR1
  123. */
  124. #define CSEN 1
  125. #define SWR (1 << 1)
  126. #define SRD (1 << 2)
  127. #define MUM (1 << 3)
  128. #define WFL (1 << 4)
  129. #define RFL (1 << 5)
  130. #define CRE (1 << 6)
  131. #define CREP (1 << 7)
  132. #define BL(x) (((x) & 0x7) << 8)
  133. #define WC (1 << 11)
  134. #define BCD(x) (((x) & 0x3) << 12)
  135. #define BCS(x) (((x) & 0x3) << 14)
  136. #define DSZ(x) (((x) & 0x7) << 16)
  137. #define SP (1 << 19)
  138. #define CSREC(x) (((x) & 0x7) << 20)
  139. #define AUS (1 << 23)
  140. #define GBC(x) (((x) & 0x7) << 24)
  141. #define WP (1 << 27)
  142. #define PSZ(x) (((x) & 0x0f << 28)
  143. /*
  144. * WEIM CSnGCR2
  145. */
  146. #define ADH(x) (((x) & 0x3))
  147. #define DAPS(x) (((x) & 0x0f << 4)
  148. #define DAE (1 << 8)
  149. #define DAP (1 << 9)
  150. #define MUX16_BYP (1 << 12)
  151. /*
  152. * WEIM CSnRCR1
  153. */
  154. #define RCSN(x) (((x) & 0x7))
  155. #define RCSA(x) (((x) & 0x7) << 4)
  156. #define OEN(x) (((x) & 0x7) << 8)
  157. #define OEA(x) (((x) & 0x7) << 12)
  158. #define RADVN(x) (((x) & 0x7) << 16)
  159. #define RAL (1 << 19)
  160. #define RADVA(x) (((x) & 0x7) << 20)
  161. #define RWSC(x) (((x) & 0x3f) << 24)
  162. /*
  163. * WEIM CSnRCR2
  164. */
  165. #define RBEN(x) (((x) & 0x7))
  166. #define RBE (1 << 3)
  167. #define RBEA(x) (((x) & 0x7) << 4)
  168. #define RL(x) (((x) & 0x3) << 8)
  169. #define PAT(x) (((x) & 0x7) << 12)
  170. #define APR (1 << 15)
  171. /*
  172. * WEIM CSnWCR1
  173. */
  174. #define WCSN(x) (((x) & 0x7))
  175. #define WCSA(x) (((x) & 0x7) << 3)
  176. #define WEN(x) (((x) & 0x7) << 6)
  177. #define WEA(x) (((x) & 0x7) << 9)
  178. #define WBEN(x) (((x) & 0x7) << 12)
  179. #define WBEA(x) (((x) & 0x7) << 15)
  180. #define WADVN(x) (((x) & 0x7) << 18)
  181. #define WADVA(x) (((x) & 0x7) << 21)
  182. #define WWSC(x) (((x) & 0x3f) << 24)
  183. #define WBED1 (1 << 30)
  184. #define WAL (1 << 31)
  185. /*
  186. * WEIM CSnWCR2
  187. */
  188. #define WBED 1
  189. /*
  190. * CSPI register definitions
  191. */
  192. #define MXC_ECSPI
  193. #define MXC_CSPICTRL_EN (1 << 0)
  194. #define MXC_CSPICTRL_MODE (1 << 1)
  195. #define MXC_CSPICTRL_XCH (1 << 2)
  196. #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
  197. #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
  198. #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
  199. #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
  200. #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
  201. #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
  202. #define MXC_CSPICTRL_MAXBITS 0xfff
  203. #define MXC_CSPICTRL_TC (1 << 7)
  204. #define MXC_CSPICTRL_RXOVF (1 << 6)
  205. #define MXC_CSPIPERIOD_32KHZ (1 << 15)
  206. #define MAX_SPI_BYTES 32
  207. /* Bit position inside CTRL register to be associated with SS */
  208. #define MXC_CSPICTRL_CHAN 18
  209. /* Bit position inside CON register to be associated with SS */
  210. #define MXC_CSPICON_PHA 0 /* SCLK phase control */
  211. #define MXC_CSPICON_POL 4 /* SCLK polarity */
  212. #define MXC_CSPICON_SSPOL 12 /* SS polarity */
  213. #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
  214. #define MXC_SPI_BASE_ADDRESSES \
  215. CSPI1_BASE_ADDR, \
  216. CSPI2_BASE_ADDR, \
  217. CSPI3_BASE_ADDR,
  218. /*
  219. * Number of GPIO pins per port
  220. */
  221. #define GPIO_NUM_PIN 32
  222. #define IIM_SREV 0x24
  223. #define ROM_SI_REV 0x48
  224. #define NFC_BUF_SIZE 0x1000
  225. /* M4IF */
  226. #define M4IF_FBPM0 0x40
  227. #define M4IF_FIDBP 0x48
  228. #define M4IF_GENP_WEIM_MM_MASK 0x00000001
  229. #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
  230. /* Assuming 24MHz input clock with doubler ON */
  231. /* MFI PDF */
  232. #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
  233. #define DP_MFD_864 (180 - 1) /* PL Dither mode */
  234. #define DP_MFN_864 180
  235. #define DP_MFN_800_DIT 60 /* PL Dither mode */
  236. #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
  237. #define DP_MFD_850 (48 - 1)
  238. #define DP_MFN_850 41
  239. #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
  240. #define DP_MFD_800 (3 - 1)
  241. #define DP_MFN_800 1
  242. #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
  243. #define DP_MFD_700 (24 - 1)
  244. #define DP_MFN_700 7
  245. #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
  246. #define DP_MFD_665 (96 - 1)
  247. #define DP_MFN_665 89
  248. #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
  249. #define DP_MFD_532 (24 - 1)
  250. #define DP_MFN_532 13
  251. #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
  252. #define DP_MFD_400 (3 - 1)
  253. #define DP_MFN_400 1
  254. #define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
  255. #define DP_MFD_455 (48 - 1)
  256. #define DP_MFN_455 23
  257. #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
  258. #define DP_MFD_216 (4 - 1)
  259. #define DP_MFN_216 3
  260. #define IMX_IIM_BASE (IIM_BASE_ADDR)
  261. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  262. #include <asm/types.h>
  263. #define __REG(x) (*((volatile u32 *)(x)))
  264. #define __REG16(x) (*((volatile u16 *)(x)))
  265. #define __REG8(x) (*((volatile u8 *)(x)))
  266. struct clkctl {
  267. u32 ccr;
  268. u32 ccdr;
  269. u32 csr;
  270. u32 ccsr;
  271. u32 cacrr;
  272. u32 cbcdr;
  273. u32 cbcmr;
  274. u32 cscmr1;
  275. u32 cscmr2;
  276. u32 cscdr1;
  277. u32 cs1cdr;
  278. u32 cs2cdr;
  279. u32 cdcdr;
  280. u32 chsccdr;
  281. u32 cscdr2;
  282. u32 cscdr3;
  283. u32 cscdr4;
  284. u32 cwdr;
  285. u32 cdhipr;
  286. u32 cdcr;
  287. u32 ctor;
  288. u32 clpcr;
  289. u32 cisr;
  290. u32 cimr;
  291. u32 ccosr;
  292. u32 cgpr;
  293. u32 ccgr0;
  294. u32 ccgr1;
  295. u32 ccgr2;
  296. u32 ccgr3;
  297. u32 ccgr4;
  298. u32 ccgr5;
  299. u32 ccgr6;
  300. #if defined(CONFIG_MX53)
  301. u32 ccgr7;
  302. #endif
  303. u32 cmeor;
  304. };
  305. /* DPLL registers */
  306. struct dpll {
  307. u32 dp_ctl;
  308. u32 dp_config;
  309. u32 dp_op;
  310. u32 dp_mfd;
  311. u32 dp_mfn;
  312. u32 dp_mfn_minus;
  313. u32 dp_mfn_plus;
  314. u32 dp_hfs_op;
  315. u32 dp_hfs_mfd;
  316. u32 dp_hfs_mfn;
  317. u32 dp_mfn_togc;
  318. u32 dp_destat;
  319. };
  320. /* WEIM registers */
  321. struct weim {
  322. u32 cs0gcr1;
  323. u32 cs0gcr2;
  324. u32 cs0rcr1;
  325. u32 cs0rcr2;
  326. u32 cs0wcr1;
  327. u32 cs0wcr2;
  328. u32 cs1gcr1;
  329. u32 cs1gcr2;
  330. u32 cs1rcr1;
  331. u32 cs1rcr2;
  332. u32 cs1wcr1;
  333. u32 cs1wcr2;
  334. u32 cs2gcr1;
  335. u32 cs2gcr2;
  336. u32 cs2rcr1;
  337. u32 cs2rcr2;
  338. u32 cs2wcr1;
  339. u32 cs2wcr2;
  340. u32 cs3gcr1;
  341. u32 cs3gcr2;
  342. u32 cs3rcr1;
  343. u32 cs3rcr2;
  344. u32 cs3wcr1;
  345. u32 cs3wcr2;
  346. u32 cs4gcr1;
  347. u32 cs4gcr2;
  348. u32 cs4rcr1;
  349. u32 cs4rcr2;
  350. u32 cs4wcr1;
  351. u32 cs4wcr2;
  352. u32 cs5gcr1;
  353. u32 cs5gcr2;
  354. u32 cs5rcr1;
  355. u32 cs5rcr2;
  356. u32 cs5wcr1;
  357. u32 cs5wcr2;
  358. u32 wcr;
  359. u32 wiar;
  360. u32 ear;
  361. };
  362. #if defined(CONFIG_MX51)
  363. struct iomuxc {
  364. u32 gpr[2];
  365. u32 omux0;
  366. u32 omux1;
  367. u32 omux2;
  368. u32 omux3;
  369. u32 omux4;
  370. };
  371. #elif defined(CONFIG_MX53)
  372. struct iomuxc {
  373. u32 gpr[3];
  374. u32 omux0;
  375. u32 omux1;
  376. u32 omux2;
  377. u32 omux3;
  378. u32 omux4;
  379. };
  380. #endif
  381. #define IOMUXC_GPR2_BITMAP_SPWG 0
  382. #define IOMUXC_GPR2_BITMAP_JEIDA 1
  383. #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
  384. #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  385. #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \
  386. IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  387. #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \
  388. IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  389. #define IOMUXC_GPR2_DATA_WIDTH_18 0
  390. #define IOMUXC_GPR2_DATA_WIDTH_24 1
  391. #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
  392. #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  393. #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \
  394. IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  395. #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \
  396. IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  397. #define IOMUXC_GPR2_MODE_DISABLED 0
  398. #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
  399. #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
  400. #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
  401. #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  402. #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \
  403. IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  404. #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \
  405. IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  406. #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \
  407. IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  408. /* System Reset Controller (SRC) */
  409. struct src {
  410. u32 scr;
  411. u32 sbmr;
  412. u32 srsr;
  413. u32 reserved1[2];
  414. u32 sisr;
  415. u32 simr;
  416. };
  417. struct srtc_regs {
  418. u32 lpscmr; /* 0x00 */
  419. u32 lpsclr; /* 0x04 */
  420. u32 lpsar; /* 0x08 */
  421. u32 lpsmcr; /* 0x0c */
  422. u32 lpcr; /* 0x10 */
  423. u32 lpsr; /* 0x14 */
  424. u32 lppdr; /* 0x18 */
  425. u32 lpgr; /* 0x1c */
  426. u32 hpcmr; /* 0x20 */
  427. u32 hpclr; /* 0x24 */
  428. u32 hpamr; /* 0x28 */
  429. u32 hpalr; /* 0x2c */
  430. u32 hpcr; /* 0x30 */
  431. u32 hpisr; /* 0x34 */
  432. u32 hpienr; /* 0x38 */
  433. };
  434. /* CSPI registers */
  435. struct cspi_regs {
  436. u32 rxdata;
  437. u32 txdata;
  438. u32 ctrl;
  439. u32 cfg;
  440. u32 intr;
  441. u32 dma;
  442. u32 stat;
  443. u32 period;
  444. };
  445. struct iim_regs {
  446. u32 stat;
  447. u32 statm;
  448. u32 err;
  449. u32 emask;
  450. u32 fctl;
  451. u32 ua;
  452. u32 la;
  453. u32 sdat;
  454. u32 prev;
  455. u32 srev;
  456. u32 prg_p;
  457. u32 scs0;
  458. u32 scs1;
  459. u32 scs2;
  460. u32 scs3;
  461. u32 res0[0x1f1];
  462. struct fuse_bank {
  463. u32 fuse_regs[0x20];
  464. u32 fuse_rsvd[0xe0];
  465. #if defined(CONFIG_MX51)
  466. } bank[4];
  467. #elif defined(CONFIG_MX53)
  468. } bank[5];
  469. #endif
  470. };
  471. struct fuse_bank0_regs {
  472. u32 fuse0_7[8];
  473. u32 uid[8];
  474. u32 fuse16_23[8];
  475. #if defined(CONFIG_MX51)
  476. u32 imei[8];
  477. #elif defined(CONFIG_MX53)
  478. u32 gp[8];
  479. #endif
  480. };
  481. struct fuse_bank1_regs {
  482. u32 fuse0_8[9];
  483. u32 mac_addr[6];
  484. u32 fuse15_31[0x11];
  485. };
  486. #if defined(CONFIG_MX53)
  487. struct fuse_bank4_regs {
  488. u32 fuse0_4[5];
  489. u32 gp[3];
  490. u32 fuse8_31[0x18];
  491. };
  492. #endif
  493. #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
  494. #define PWMCR_DOZEEN (1 << 24)
  495. #define PWMCR_WAITEN (1 << 23)
  496. #define PWMCR_DBGEN (1 << 22)
  497. #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
  498. #define PWMCR_CLKSRC_IPG (1 << 16)
  499. #define PWMCR_EN (1 << 0)
  500. struct pwm_regs {
  501. u32 cr;
  502. u32 sr;
  503. u32 ir;
  504. u32 sar;
  505. u32 pr;
  506. u32 cnr;
  507. };
  508. #endif /* __ASSEMBLY__ */
  509. #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */