immap_lsch3.h 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * LayerScape Internal Memory Map
  4. *
  5. * Copyright 2017-2019 NXP
  6. * Copyright 2014 Freescale Semiconductor, Inc.
  7. */
  8. #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
  9. #define __ARCH_FSL_LSCH3_IMMAP_H_
  10. #define CONFIG_SYS_IMMR 0x01000000
  11. #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
  12. #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
  13. #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
  14. #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
  15. #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
  16. #ifdef CONFIG_ARCH_LX2160A
  17. #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
  18. #else
  19. #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
  20. #endif
  21. #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
  22. #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
  23. #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
  24. #ifndef CONFIG_NXP_LSCH3_2
  25. #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
  26. #else
  27. #define SYS_NXP_FSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
  28. #define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18
  29. #define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200
  30. #endif
  31. #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
  32. #define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR
  33. #define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
  34. #ifndef CONFIG_NXP_LSCH3_2
  35. #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
  36. #endif
  37. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
  38. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
  39. #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
  40. #define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
  41. #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
  42. 0x18A0)
  43. #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
  44. #define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
  45. #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
  46. #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
  47. #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
  48. #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
  49. #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
  50. #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
  51. #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
  52. #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
  53. #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
  54. #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
  55. #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
  56. #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
  57. #ifdef CONFIG_NXP_LSCH3_2
  58. #define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000)
  59. #define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000)
  60. #define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000)
  61. #define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000)
  62. #endif
  63. #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
  64. #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
  65. #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
  66. #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
  67. #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
  68. /* TZ Address Space Controller Definitions */
  69. #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
  70. #define TZASC2_BASE 0x01110000 /* as per CCSR map. */
  71. #define TZASC3_BASE 0x01120000 /* as per CCSR map. */
  72. #define TZASC4_BASE 0x01130000 /* as per CCSR map. */
  73. #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
  74. #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
  75. #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
  76. #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
  77. #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
  78. #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
  79. #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
  80. #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
  81. #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
  82. /* EDMA */
  83. #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c0000)
  84. /* SATA */
  85. #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
  86. #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
  87. #define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000)
  88. #define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000)
  89. /* QDMA */
  90. #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
  91. #define QMAN_CQSIDR_REG 0x20a80
  92. /* DISPLAY */
  93. #define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e080000)
  94. /* GPU */
  95. #define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000)
  96. /* SFP */
  97. #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
  98. /* SEC */
  99. #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
  100. #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
  101. #define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
  102. #define FSL_SEC_JR1_OFFSET 0x07020000ull
  103. #define FSL_SEC_JR2_OFFSET 0x07030000ull
  104. #define FSL_SEC_JR3_OFFSET 0x07040000ull
  105. #define CONFIG_SYS_FSL_SEC_ADDR \
  106. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
  107. #define CONFIG_SYS_FSL_JR0_ADDR \
  108. (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
  109. #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
  110. #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
  111. #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
  112. #define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
  113. #ifdef CONFIG_TFABOOT
  114. #ifdef CONFIG_NXP_LSCH3_2
  115. /* RCW_SRC field in Power-On Reset Control Register 1 */
  116. #define RCW_SRC_MASK 0x07800000
  117. #define RCW_SRC_BIT 23
  118. /* CFG_RCW_SRC[3:0] */
  119. #define RCW_SRC_TYPE_MASK 0x8
  120. #define RCW_SRC_ADDR_OFFSET_8MB 0x800000
  121. /* RCW SRC HARDCODED */
  122. #define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */
  123. #define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */
  124. #define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */
  125. #define RCW_SRC_I2C1_VAL 0xa /* 0xa */
  126. #define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */
  127. #define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */
  128. #define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */
  129. #define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */
  130. #define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */
  131. #else
  132. #define RCW_SRC_MASK (0xFF800000)
  133. #define RCW_SRC_BIT 23
  134. /* CFG_RCW_SRC[6:0] */
  135. #define RCW_SRC_TYPE_MASK (0x70)
  136. /* RCW SRC HARDCODED */
  137. #define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */
  138. /* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */
  139. /* RCW SRC NOR */
  140. #define RCW_SRC_NOR_VAL (0x20)
  141. #define NOR_TYPE_MASK (0x10)
  142. #define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */
  143. #define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */
  144. /* RCW SRC Serial Flash
  145. * 1. SERIAL NOR (QSPI)
  146. * 2. OTHERS (SD/MMC, SPI, I2C1
  147. */
  148. #define RCW_SRC_SERIAL_MASK (0x7F)
  149. #define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */
  150. #define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */
  151. #define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */
  152. #define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */
  153. #endif
  154. #endif
  155. /* Security Monitor */
  156. #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
  157. /* MMU 500 */
  158. #define SMMU_SCR0 (SMMU_BASE + 0x0)
  159. #define SMMU_SCR1 (SMMU_BASE + 0x4)
  160. #define SMMU_SCR2 (SMMU_BASE + 0x8)
  161. #define SMMU_SACR (SMMU_BASE + 0x10)
  162. #define SMMU_IDR0 (SMMU_BASE + 0x20)
  163. #define SMMU_IDR1 (SMMU_BASE + 0x24)
  164. #define SMMU_NSCR0 (SMMU_BASE + 0x400)
  165. #define SMMU_NSCR2 (SMMU_BASE + 0x408)
  166. #define SMMU_NSACR (SMMU_BASE + 0x410)
  167. #define SCR0_CLIENTPD_MASK 0x00000001
  168. #define SCR0_USFCFG_MASK 0x00000400
  169. /* PCIe */
  170. #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
  171. #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
  172. #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
  173. #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
  174. #ifdef CONFIG_ARCH_LX2160A
  175. #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
  176. #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
  177. #endif
  178. #ifdef CONFIG_ARCH_LX2160A
  179. #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
  180. #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
  181. #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
  182. #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL
  183. #define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL
  184. #define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL
  185. #elif CONFIG_ARCH_LS1088A
  186. #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
  187. #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
  188. #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
  189. #elif CONFIG_ARCH_LS1028A
  190. #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
  191. #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
  192. #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL
  193. /* this is used by integrated PCI on LS1028, includes ECAM and register space */
  194. #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL
  195. #else
  196. #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
  197. #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
  198. #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
  199. #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
  200. #endif
  201. /* Device Configuration */
  202. #define DCFG_BASE 0x01e00000
  203. #define DCFG_PORSR1 0x000
  204. #define DCFG_PORSR1_RCW_SRC 0xff800000
  205. #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
  206. #define DCFG_RCWSR12 0x12c
  207. #define DCFG_RCWSR12_SDHC_SHIFT 24
  208. #define DCFG_RCWSR12_SDHC_MASK 0x7
  209. #define DCFG_RCWSR13 0x130
  210. #define DCFG_RCWSR13_SDHC_SHIFT 3
  211. #define DCFG_RCWSR13_SDHC_MASK 0x7
  212. #define DCFG_RCWSR13_DSPI (0 << 8)
  213. #define DCFG_RCWSR15 0x138
  214. #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
  215. #define DCFG_DCSR_BASE 0X700100000ULL
  216. #define DCFG_DCSR_PORCR1 0x000
  217. /* Interrupt Sampling Control */
  218. #define ISC_BASE 0x01F70000
  219. #define IRQCR_OFFSET 0x14
  220. /* Supplemental Configuration */
  221. #define SCFG_BASE 0x01fc0000
  222. #define SCFG_USB3PRM1CR 0x000
  223. #define SCFG_USB3PRM1CR_INIT 0x27672b2a
  224. #define SCFG_USB_TXVREFTUNE 0x9
  225. #define SCFG_USB_SQRXTUNE_MASK 0x7
  226. #define SCFG_QSPICLKCTLR 0x10
  227. #define DCSR_BASE 0x700000000ULL
  228. #define DCSR_USB_PHY1 0x4600000
  229. #define DCSR_USB_PHY2 0x4610000
  230. #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
  231. #define USB_PHY_RX_EQ_VAL_1 0x0000
  232. #define USB_PHY_RX_EQ_VAL_2 0x0080
  233. #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  234. defined(CONFIG_ARCH_LS1028A)
  235. #define USB_PHY_RX_EQ_VAL_3 0x0380
  236. #define USB_PHY_RX_EQ_VAL_4 0x0b80
  237. #elif defined(CONFIG_ARCH_LX2160A)
  238. #define USB_PHY_RX_EQ_VAL_3 0x0080
  239. #define USB_PHY_RX_EQ_VAL_4 0x0880
  240. #endif
  241. #define DCSR_USB_IOCR1 0x108004
  242. #define DCSR_USB_PCSTXSWINGFULL 0x71
  243. #define TP_ITYP_AV 0x00000001 /* Initiator available */
  244. #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
  245. #define TP_ITYP_TYPE_ARM 0x0
  246. #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
  247. #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
  248. #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
  249. #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
  250. #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
  251. #define TY_ITYP_VER_A7 0x1
  252. #define TY_ITYP_VER_A53 0x2
  253. #define TY_ITYP_VER_A57 0x3
  254. #define TY_ITYP_VER_A72 0x4
  255. #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
  256. #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
  257. #define TP_INIT_PER_CLUSTER 4
  258. /* This is chassis generation 3 */
  259. #ifndef __ASSEMBLY__
  260. struct sys_info {
  261. unsigned long freq_processor[CONFIG_MAX_CPUS];
  262. /* frequency of platform PLL */
  263. unsigned long freq_systembus;
  264. unsigned long freq_ddrbus;
  265. unsigned long freq_cga_m2;
  266. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  267. unsigned long freq_ddrbus2;
  268. #endif
  269. unsigned long freq_localbus;
  270. unsigned long freq_qe;
  271. #ifdef CONFIG_SYS_DPAA_FMAN
  272. unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
  273. #endif
  274. #ifdef CONFIG_SYS_DPAA_QBMAN
  275. unsigned long freq_qman;
  276. #endif
  277. #ifdef CONFIG_SYS_DPAA_PME
  278. unsigned long freq_pme;
  279. #endif
  280. };
  281. /* Global Utilities Block */
  282. struct ccsr_gur {
  283. u32 porsr1; /* POR status 1 */
  284. u32 porsr2; /* POR status 2 */
  285. u8 res_008[0x20-0x8];
  286. u32 gpporcr1; /* General-purpose POR configuration */
  287. u32 gpporcr2; /* General-purpose POR configuration 2 */
  288. u32 gpporcr3;
  289. u32 gpporcr4;
  290. u8 res_030[0x60-0x30];
  291. #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
  292. #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
  293. #if defined(CONFIG_ARCH_LS1088A)
  294. #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
  295. #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
  296. #else
  297. #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
  298. #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
  299. #endif
  300. u32 dcfg_fusesr; /* Fuse status register */
  301. u8 res_064[0x70-0x64];
  302. u32 devdisr; /* Device disable control 1 */
  303. u32 devdisr2; /* Device disable control 2 */
  304. u32 devdisr3; /* Device disable control 3 */
  305. u32 devdisr4; /* Device disable control 4 */
  306. u32 devdisr5; /* Device disable control 5 */
  307. u32 devdisr6; /* Device disable control 6 */
  308. u8 res_088[0x94-0x88];
  309. u32 coredisr; /* Device disable control 7 */
  310. #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
  311. #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
  312. #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
  313. #define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
  314. #define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
  315. #define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
  316. #define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
  317. #define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
  318. #define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
  319. #define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
  320. #define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
  321. #define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
  322. #define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
  323. #define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
  324. #define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
  325. #define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
  326. #define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
  327. #define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
  328. #define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
  329. #define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
  330. #define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
  331. #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
  332. #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
  333. #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
  334. u8 res_098[0xa0-0x98];
  335. u32 pvr; /* Processor version */
  336. u32 svr; /* System version */
  337. u8 res_0a8[0x100-0xa8];
  338. u32 rcwsr[30]; /* Reset control word status */
  339. #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
  340. #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
  341. #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
  342. #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
  343. #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
  344. #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
  345. #if defined(CONFIG_ARCH_LS2080A)
  346. #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
  347. #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
  348. #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
  349. #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
  350. #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
  351. #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
  352. #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
  353. #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
  354. #define FSL_CHASSIS3_SRDS1_REGSR 29
  355. #define FSL_CHASSIS3_SRDS2_REGSR 29
  356. #elif defined(CONFIG_ARCH_LX2160A)
  357. #define FSL_CHASSIS3_EC1_REGSR 27
  358. #define FSL_CHASSIS3_EC2_REGSR 27
  359. #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003
  360. #define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0
  361. #define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007
  362. #define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2
  363. #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000
  364. #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
  365. #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000
  366. #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21
  367. #define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000
  368. #define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26
  369. #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
  370. #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
  371. #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
  372. #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
  373. #define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK
  374. #define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT
  375. #define FSL_CHASSIS3_SRDS1_REGSR 29
  376. #define FSL_CHASSIS3_SRDS2_REGSR 29
  377. #define FSL_CHASSIS3_SRDS3_REGSR 29
  378. #define FSL_CHASSIS3_RCWSR12_REGSR 12
  379. #define FSL_CHASSIS3_RCWSR13_REGSR 13
  380. #define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000
  381. #define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
  382. #define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038
  383. #define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
  384. #define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00
  385. #define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9
  386. #elif defined(CONFIG_ARCH_LS1088A)
  387. #define FSL_CHASSIS3_EC1_REGSR 26
  388. #define FSL_CHASSIS3_EC2_REGSR 26
  389. #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007
  390. #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0
  391. #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038
  392. #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3
  393. #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
  394. #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
  395. #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
  396. #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0
  397. #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
  398. #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
  399. #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
  400. #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
  401. #define FSL_CHASSIS3_SRDS1_REGSR 29
  402. #define FSL_CHASSIS3_SRDS2_REGSR 30
  403. #elif defined(CONFIG_ARCH_LS1028A)
  404. #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
  405. #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
  406. #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
  407. #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
  408. #define FSL_CHASSIS3_SRDS1_REGSR 29
  409. #endif
  410. #define RCW_SB_EN_REG_INDEX 9
  411. #define RCW_SB_EN_MASK 0x00000400
  412. u8 res_178[0x200-0x178];
  413. u32 scratchrw[16]; /* Scratch Read/Write */
  414. u8 res_240[0x300-0x240];
  415. u32 scratchw1r[4]; /* Scratch Read (Write once) */
  416. u8 res_310[0x400-0x310];
  417. u32 bootlocptrl; /* Boot location pointer low-order addr */
  418. u32 bootlocptrh; /* Boot location pointer high-order addr */
  419. u8 res_408[0x520-0x408];
  420. u32 usb1_amqr;
  421. u32 usb2_amqr;
  422. u8 res_528[0x530-0x528]; /* add more registers when needed */
  423. u32 sdmm1_amqr;
  424. u32 sdmm2_amqr;
  425. u8 res_538[0x550 - 0x538]; /* add more registers when needed */
  426. u32 sata1_amqr;
  427. u32 sata2_amqr;
  428. u32 sata3_amqr;
  429. u32 sata4_amqr;
  430. u8 res_560[0x570 - 0x560]; /* add more registers when needed */
  431. u32 misc1_amqr;
  432. u8 res_574[0x590-0x574]; /* add more registers when needed */
  433. u32 spare1_amqr;
  434. u32 spare2_amqr;
  435. u32 spare3_amqr;
  436. u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */
  437. u32 gencr[7]; /* General Control Registers */
  438. u8 res_63c[0x640-0x63c]; /* add more registers when needed */
  439. u32 cgensr1; /* Core General Status Register */
  440. u8 res_644[0x660-0x644]; /* add more registers when needed */
  441. u32 cgencr1; /* Core General Control Register */
  442. u8 res_664[0x740-0x664]; /* add more registers when needed */
  443. u32 tp_ityp[64]; /* Topology Initiator Type Register */
  444. struct {
  445. u32 upper;
  446. u32 lower;
  447. } tp_cluster[4]; /* Core cluster n Topology Register */
  448. u8 res_864[0x920-0x864]; /* add more registers when needed */
  449. u32 ioqoscr[8]; /*I/O Quality of Services Register */
  450. u32 uccr;
  451. u8 res_944[0x960-0x944]; /* add more registers when needed */
  452. u32 ftmcr;
  453. u8 res_964[0x990-0x964]; /* add more registers when needed */
  454. u32 coredisablesr;
  455. u8 res_994[0xa00-0x994]; /* add more registers when needed */
  456. u32 sdbgcr; /*Secure Debug Confifuration Register */
  457. u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
  458. u32 ipbrr1;
  459. u32 ipbrr2;
  460. u8 res_858[0x1000-0xc00];
  461. };
  462. struct ccsr_clk_cluster_group {
  463. struct {
  464. u8 res_00[0x10];
  465. u32 csr;
  466. u8 res_14[0x20-0x14];
  467. } hwncsr[3];
  468. u8 res_60[0x80-0x60];
  469. struct {
  470. u32 gsr;
  471. u8 res_84[0xa0-0x84];
  472. } pllngsr[3];
  473. u8 res_e0[0x100-0xe0];
  474. };
  475. struct ccsr_clk_ctrl {
  476. struct {
  477. u32 csr; /* core cluster n clock control status */
  478. u8 res_04[0x20-0x04];
  479. } clkcncsr[8];
  480. };
  481. struct ccsr_reset {
  482. u32 rstcr; /* 0x000 */
  483. u32 rstcrsp; /* 0x004 */
  484. u8 res_008[0x10-0x08]; /* 0x008 */
  485. u32 rstrqmr1; /* 0x010 */
  486. u32 rstrqmr2; /* 0x014 */
  487. u32 rstrqsr1; /* 0x018 */
  488. u32 rstrqsr2; /* 0x01c */
  489. u32 rstrqwdtmrl; /* 0x020 */
  490. u32 rstrqwdtmru; /* 0x024 */
  491. u8 res_028[0x30-0x28]; /* 0x028 */
  492. u32 rstrqwdtsrl; /* 0x030 */
  493. u32 rstrqwdtsru; /* 0x034 */
  494. u8 res_038[0x60-0x38]; /* 0x038 */
  495. u32 brrl; /* 0x060 */
  496. u32 brru; /* 0x064 */
  497. u8 res_068[0x80-0x68]; /* 0x068 */
  498. u32 pirset; /* 0x080 */
  499. u32 pirclr; /* 0x084 */
  500. u8 res_088[0x90-0x88]; /* 0x088 */
  501. u32 brcorenbr; /* 0x090 */
  502. u8 res_094[0x100-0x94]; /* 0x094 */
  503. u32 rcw_reqr; /* 0x100 */
  504. u32 rcw_completion; /* 0x104 */
  505. u8 res_108[0x110-0x108]; /* 0x108 */
  506. u32 pbi_reqr; /* 0x110 */
  507. u32 pbi_completion; /* 0x114 */
  508. u8 res_118[0xa00-0x118]; /* 0x118 */
  509. u32 qmbm_warmrst; /* 0xa00 */
  510. u32 soc_warmrst; /* 0xa04 */
  511. u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
  512. u32 ip_rev1; /* 0xbf8 */
  513. u32 ip_rev2; /* 0xbfc */
  514. };
  515. struct ccsr_serdes {
  516. struct {
  517. u32 rstctl; /* Reset Control Register */
  518. u32 pllcr0; /* PLL Control Register 0 */
  519. u32 pllcr1; /* PLL Control Register 1 */
  520. u32 pllcr2; /* PLL Control Register 2 */
  521. u32 pllcr3; /* PLL Control Register 3 */
  522. u32 pllcr4; /* PLL Control Register 4 */
  523. u32 pllcr5; /* PLL Control Register 5 */
  524. u8 res[0x20 - 0x1c];
  525. } bank[2];
  526. u8 res1[0x90 - 0x40];
  527. u32 srdstcalcr; /* TX Calibration Control */
  528. u32 srdstcalcr1; /* TX Calibration Control1 */
  529. u8 res2[0xa0 - 0x98];
  530. u32 srdsrcalcr; /* RX Calibration Control */
  531. u32 srdsrcalcr1; /* RX Calibration Control1 */
  532. u8 res3[0xb0 - 0xa8];
  533. u32 srdsgr0; /* General Register 0 */
  534. u8 res4[0x800 - 0xb4];
  535. struct serdes_lane {
  536. u32 gcr0; /* General Control Register 0 */
  537. u32 gcr1; /* General Control Register 1 */
  538. u32 gcr2; /* General Control Register 2 */
  539. u32 ssc0; /* Speed Switch Control 0 */
  540. u32 rec0; /* Receive Equalization Control 0 */
  541. u32 rec1; /* Receive Equalization Control 1 */
  542. u32 tec0; /* Transmit Equalization Control 0 */
  543. u32 ssc1; /* Speed Switch Control 1 */
  544. u8 res1[0x840 - 0x820];
  545. } lane[8];
  546. u8 res5[0x19fc - 0xa00];
  547. };
  548. #endif /*__ASSEMBLY__ */
  549. #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */