board.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for B&R BRPPT1
  6. *
  7. * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
  8. * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  9. *
  10. */
  11. #include <common.h>
  12. #include <bootcount.h>
  13. #include <env.h>
  14. #include <errno.h>
  15. #include <spl.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/omap.h>
  19. #include <asm/arch/ddr_defs.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/mem.h>
  24. #include <asm/io.h>
  25. #include <asm/emif.h>
  26. #include <asm/gpio.h>
  27. #include <i2c.h>
  28. #include <power/tps65217.h>
  29. #include "../common/bur_common.h"
  30. #include <watchdog.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. /* --------------------------------------------------------------------------*/
  33. /* -- defines for GPIO -- */
  34. #define REPSWITCH (0+20) /* GPIO0_20 */
  35. #if defined(CONFIG_SPL_BUILD)
  36. /* TODO: check ram-timing ! */
  37. static const struct ddr_data ddr3_data = {
  38. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  39. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  40. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  41. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  42. };
  43. static const struct cmd_control ddr3_cmd_ctrl_data = {
  44. .cmd0csratio = MT41K256M16HA125E_RATIO,
  45. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  46. .cmd1csratio = MT41K256M16HA125E_RATIO,
  47. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  48. .cmd2csratio = MT41K256M16HA125E_RATIO,
  49. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  50. };
  51. static struct emif_regs ddr3_emif_reg_data = {
  52. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  53. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  54. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  55. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  56. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  57. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  58. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  59. };
  60. static const struct ctrl_ioregs ddr3_ioregs = {
  61. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  62. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  63. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  64. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  65. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  66. };
  67. #define OSC (V_OSCK/1000000)
  68. static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
  69. void am33xx_spl_board_init(void)
  70. {
  71. int rc;
  72. struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  73. /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
  74. struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
  75. /*
  76. * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
  77. * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
  78. * the source of timer6 clk to CLK_M_OSC
  79. */
  80. writel(0x01, &cmdpll->clktimer6clk);
  81. /* enable additional clocks of modules which are accessed later */
  82. u32 *const clk_domains[] = {
  83. &cmper->lcdcclkstctrl,
  84. 0
  85. };
  86. u32 *const clk_modules_tsspecific[] = {
  87. &cmper->lcdclkctrl,
  88. &cmper->timer5clkctrl,
  89. &cmper->timer6clkctrl,
  90. 0
  91. };
  92. do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
  93. /* setup I2C */
  94. enable_i2c_pin_mux();
  95. pmicsetup(0, 0);
  96. /* peripheral reset */
  97. rc = gpio_request(64 + 29, "GPMC_WAIT1");
  98. if (rc != 0)
  99. printf("cannot request GPMC_WAIT1 GPIO!\n");
  100. rc = gpio_direction_output(64 + 29, 1);
  101. if (rc != 0)
  102. printf("cannot set GPMC_WAIT1 GPIO!\n");
  103. rc = gpio_request(64 + 28, "GPMC_WAIT0");
  104. if (rc != 0)
  105. printf("cannot request GPMC_WAIT0 GPIO!\n");
  106. rc = gpio_direction_output(64 + 28, 1);
  107. if (rc != 0)
  108. printf("cannot set GPMC_WAIT0 GPIO!\n");
  109. }
  110. const struct dpll_params *get_dpll_ddr_params(void)
  111. {
  112. return &dpll_ddr3;
  113. }
  114. void sdram_init(void)
  115. {
  116. config_ddr(400, &ddr3_ioregs,
  117. &ddr3_data,
  118. &ddr3_cmd_ctrl_data,
  119. &ddr3_emif_reg_data, 0);
  120. }
  121. #endif /* CONFIG_SPL_BUILD */
  122. /* Basic board specific setup. Pinmux has been handled already. */
  123. int board_init(void)
  124. {
  125. #if defined(CONFIG_HW_WATCHDOG)
  126. hw_watchdog_init();
  127. #endif
  128. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  129. #ifdef CONFIG_NAND
  130. gpmc_init();
  131. #endif
  132. return 0;
  133. }
  134. #ifdef CONFIG_BOARD_LATE_INIT
  135. static char *bootmodeascii[16] = {
  136. "BOOT", "reserved", "reserved", "reserved",
  137. "RUN", "reserved", "reserved", "reserved",
  138. "reserved", "reserved", "reserved", "reserved",
  139. "PME", "reserved", "reserved", "DIAG",
  140. };
  141. int board_late_init(void)
  142. {
  143. unsigned char bmode = 0;
  144. ulong bootcount = 0;
  145. int rc;
  146. bootcount = bootcount_load() & 0xF;
  147. rc = gpio_request(REPSWITCH, "REPSWITCH");
  148. if (rc != 0 || gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
  149. bmode = 12;
  150. else if (bootcount > 0)
  151. bmode = 0;
  152. else
  153. bmode = 4;
  154. printf("Mode: %s\n", bootmodeascii[bmode & 0x0F]);
  155. env_set_ulong("b_mode", bmode);
  156. /* get sure that bootcmd isn't affected by any bootcount value */
  157. env_set_ulong("bootlimit", 0);
  158. return 0;
  159. }
  160. #endif /* CONFIG_BOARD_LATE_INIT */