o2dnt.h 8.2 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __CONFIG_H
  24. #define __CONFIG_H
  25. /*
  26. * High Level Configuration Options
  27. * (easy to change)
  28. */
  29. #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
  30. #define CONFIG_MPC5200
  31. #define CONFIG_O2DNT 1 /* ... on O2DNT board */
  32. #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
  33. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  34. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  35. #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
  36. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  37. # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  38. #endif
  39. /*
  40. * Serial console configuration
  41. */
  42. #define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
  43. #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
  44. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  45. /*
  46. * PCI Mapping:
  47. * 0x40000000 - 0x4fffffff - PCI Memory
  48. * 0x50000000 - 0x50ffffff - PCI IO Space
  49. */
  50. #define CONFIG_PCI 1
  51. #define CONFIG_PCI_PNP 1
  52. /* #define CONFIG_PCI_SCAN_SHOW 1 */
  53. #define CONFIG_PCI_MEM_BUS 0x40000000
  54. #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  55. #define CONFIG_PCI_MEM_SIZE 0x10000000
  56. #define CONFIG_PCI_IO_BUS 0x50000000
  57. #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  58. #define CONFIG_PCI_IO_SIZE 0x01000000
  59. #define CFG_XLB_PIPELINING 1
  60. #define CONFIG_NET_MULTI 1
  61. #define CONFIG_EEPRO100
  62. #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
  63. #define CONFIG_NS8382X 1
  64. #define ADD_PCI_CMD CFG_CMD_PCI
  65. /* Partitions */
  66. #define CONFIG_MAC_PARTITION
  67. #define CONFIG_DOS_PARTITION
  68. #define CONFIG_ISO_PARTITION
  69. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  70. /*
  71. * Supported commands
  72. */
  73. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
  74. CFG_CMD_EEPROM | \
  75. CFG_CMD_FAT | \
  76. CFG_CMD_I2C | \
  77. CFG_CMD_NFS | \
  78. CFG_CMD_MII | \
  79. CFG_CMD_PING | \
  80. ADD_PCI_CMD )
  81. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  82. #include <cmd_confdefs.h>
  83. #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
  84. # define CFG_LOWBOOT 1
  85. #else
  86. # error "TEXT_BASE must be 0xFF000000"
  87. #endif
  88. /*
  89. * Autobooting
  90. */
  91. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  92. #define CONFIG_PREBOOT "echo;" \
  93. "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  94. "echo"
  95. #undef CONFIG_BOOTARGS
  96. #define CONFIG_EXTRA_ENV_SETTINGS \
  97. "netdev=eth0\0" \
  98. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  99. "nfsroot=${serverip}:${rootpath}\0" \
  100. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  101. "addip=setenv bootargs ${bootargs} " \
  102. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  103. ":${hostname}:${netdev}:off panic=1\0" \
  104. "flash_nfs=run nfsargs addip;" \
  105. "bootm ${kernel_addr}\0" \
  106. "flash_self=run ramargs addip;" \
  107. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  108. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
  109. "rootpath=/opt/eldk/ppc_82xx\0" \
  110. "bootfile=/tftpboot/MPC5200/uImage\0" \
  111. ""
  112. #define CONFIG_BOOTCOMMAND "run flash_self"
  113. #if defined(CONFIG_MPC5200)
  114. /*
  115. * IPB Bus clocking configuration.
  116. */
  117. #define CFG_IPBSPEED_133 /* define for 133MHz speed */
  118. #if defined(CFG_IPBSPEED_133)
  119. /*
  120. * PCI Bus clocking configuration
  121. *
  122. * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
  123. * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
  124. * been tested with a IPB Bus Clock of 66 MHz.
  125. */
  126. #define CFG_PCISPEED_66 /* define for 66MHz speed */
  127. #endif
  128. #endif
  129. /*
  130. * I2C configuration
  131. */
  132. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  133. #define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
  134. #define CFG_I2C_SPEED 100000 /* 100 kHz */
  135. #define CFG_I2C_SLAVE 0x7F
  136. /*
  137. * EEPROM configuration:
  138. *
  139. * O2DNT board is equiped with Ramtron FRAM device FM24CL16
  140. * 16 Kib Ferroelectric Nonvolatile serial RAM memory
  141. * organized as 2048 x 8 bits and addressable as eight I2C devices
  142. * 0x50 ... 0x57 each 256 bytes in size
  143. *
  144. */
  145. #define CFG_I2C_FRAM
  146. #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
  147. #define CFG_I2C_EEPROM_ADDR_LEN 1
  148. #define CFG_EEPROM_PAGE_WRITE_BITS 3
  149. /*
  150. * There is no write delay with FRAM, write operations are performed at bus
  151. * speed. Thus, no status polling or write delay is needed.
  152. */
  153. /*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70*/
  154. /*
  155. * Flash configuration
  156. */
  157. #define CFG_FLASH_BASE 0xFF000000
  158. #define CFG_FLASH_SIZE 0x01000000
  159. #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
  160. #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
  161. #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
  162. #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
  163. #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
  164. #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
  165. #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  166. /*
  167. * Environment settings
  168. */
  169. #define CFG_ENV_IS_IN_FLASH 1
  170. #define CFG_ENV_SIZE 0x20000
  171. #define CFG_ENV_SECT_SIZE 0x20000
  172. #define CONFIG_ENV_OVERWRITE 1
  173. /*
  174. * Memory map
  175. */
  176. #define CFG_MBAR 0xF0000000
  177. #define CFG_SDRAM_BASE 0x00000000
  178. #define CFG_DEFAULT_MBAR 0x80000000
  179. /* Use SRAM until RAM will be available */
  180. #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
  181. #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
  182. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  183. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  184. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  185. #define CFG_MONITOR_BASE TEXT_BASE
  186. #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
  187. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  188. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  189. /*
  190. * Ethernet configuration
  191. */
  192. #define CONFIG_MPC5xxx_FEC 1
  193. /*
  194. * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
  195. */
  196. /* #define CONFIG_FEC_10MBIT 1 */
  197. #define CONFIG_PHY_ADDR 0x00
  198. /*
  199. * GPIO configuration
  200. */
  201. /*#define CFG_GPS_PORT_CONFIG 0x10002004 */
  202. #define CFG_GPS_PORT_CONFIG 0x00002004 /* no CAN */
  203. /*
  204. * Miscellaneous configurable options
  205. */
  206. #define CFG_LONGHELP /* undef to save memory */
  207. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  208. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  209. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  210. #else
  211. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  212. #endif
  213. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  214. #define CFG_MAXARGS 16 /* max number of command args */
  215. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  216. #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
  217. #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
  218. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  219. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  220. /*
  221. * Various low-level settings
  222. */
  223. #if defined(CONFIG_MPC5200)
  224. #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
  225. #define CFG_HID0_FINAL HID0_ICE
  226. #else
  227. #define CFG_HID0_INIT 0
  228. #define CFG_HID0_FINAL 0
  229. #endif
  230. #define CFG_BOOTCS_START CFG_FLASH_BASE
  231. #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
  232. #ifdef CFG_PCISPEED_66
  233. /*
  234. * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
  235. */
  236. #define CFG_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */
  237. #else
  238. #define CFG_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */
  239. #endif
  240. #define CFG_CS0_START CFG_FLASH_BASE
  241. #define CFG_CS0_SIZE CFG_FLASH_SIZE
  242. #define CFG_CS_BURST 0x00000000
  243. #define CFG_CS_DEADCYCLE 0x33333333
  244. #define CFG_RESET_ADDRESS 0xff000000
  245. #endif /* __CONFIG_H */