fec.c 14 KB

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  1. /*
  2. * (C) Copyright 2000-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <malloc.h>
  25. #include <asm/fec.h>
  26. #ifdef CONFIG_M5272
  27. #include <asm/m5272.h>
  28. #include <asm/immap_5272.h>
  29. #endif
  30. #ifdef CONFIG_M5282
  31. #include <asm/m5282.h>
  32. #include <asm/immap_5282.h>
  33. #endif
  34. #include <net.h>
  35. #include <command.h>
  36. #ifdef CONFIG_M5272
  37. #define FEC_ADDR (CFG_MBAR + 0x840)
  38. #endif
  39. #ifdef CONFIG_M5282
  40. #define FEC_ADDR (CFG_MBAR + 0x1000)
  41. #endif
  42. #undef ET_DEBUG
  43. #undef MII_DEBUG
  44. #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
  45. #ifdef CFG_DISCOVER_PHY
  46. #include <miiphy.h>
  47. static void mii_discover_phy (void);
  48. #endif
  49. /* Ethernet Transmit and Receive Buffers */
  50. #define DBUF_LENGTH 1520
  51. #define TX_BUF_CNT 2
  52. #define TOUT_LOOP 100
  53. #define PKT_MAXBUF_SIZE 1518
  54. #define PKT_MINBUF_SIZE 64
  55. #define PKT_MAXBLR_SIZE 1520
  56. static char txbuf[DBUF_LENGTH];
  57. static uint rxIdx; /* index of the current RX buffer */
  58. static uint txIdx; /* index of the current TX buffer */
  59. /*
  60. * FEC Ethernet Tx and Rx buffer descriptors allocated at the
  61. * immr->udata_bd address on Dual-Port RAM
  62. * Provide for Double Buffering
  63. */
  64. typedef volatile struct CommonBufferDescriptor {
  65. cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
  66. cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
  67. } RTXBD;
  68. static RTXBD *rtx = NULL;
  69. int eth_send (volatile void *packet, int length)
  70. {
  71. int j, rc;
  72. volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
  73. /* section 16.9.23.3
  74. * Wait for ready
  75. */
  76. j = 0;
  77. while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
  78. && (j < TOUT_LOOP)) {
  79. udelay (1);
  80. j++;
  81. }
  82. if (j >= TOUT_LOOP) {
  83. printf ("TX not ready\n");
  84. }
  85. rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
  86. rtx->txbd[txIdx].cbd_datlen = length;
  87. rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
  88. /* Activate transmit Buffer Descriptor polling */
  89. fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
  90. j = 0;
  91. while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
  92. && (j < TOUT_LOOP)) {
  93. udelay (1);
  94. j++;
  95. }
  96. if (j >= TOUT_LOOP) {
  97. printf ("TX timeout\n");
  98. }
  99. #ifdef ET_DEBUG
  100. printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
  101. __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
  102. (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
  103. #endif
  104. /* return only status bits */ ;
  105. rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
  106. txIdx = (txIdx + 1) % TX_BUF_CNT;
  107. return rc;
  108. }
  109. int eth_rx (void)
  110. {
  111. int length;
  112. volatile fec_t *fecp = (fec_t *) FEC_ADDR;
  113. for (;;) {
  114. /* section 16.9.23.2 */
  115. if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
  116. length = -1;
  117. break; /* nothing received - leave for() loop */
  118. }
  119. length = rtx->rxbd[rxIdx].cbd_datlen;
  120. if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
  121. #ifdef ET_DEBUG
  122. printf ("%s[%d] err: %x\n",
  123. __FUNCTION__, __LINE__,
  124. rtx->rxbd[rxIdx].cbd_sc);
  125. #endif
  126. } else {
  127. /* Pass the packet up to the protocol layers. */
  128. NetReceive (NetRxPackets[rxIdx], length - 4);
  129. }
  130. /* Give the buffer back to the FEC. */
  131. rtx->rxbd[rxIdx].cbd_datlen = 0;
  132. /* wrap around buffer index when necessary */
  133. if ((rxIdx + 1) >= PKTBUFSRX) {
  134. rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
  135. (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  136. rxIdx = 0;
  137. } else {
  138. rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
  139. rxIdx++;
  140. }
  141. /* Try to fill Buffer Descriptors */
  142. fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
  143. }
  144. return length;
  145. }
  146. /**************************************************************
  147. *
  148. * FEC Ethernet Initialization Routine
  149. *
  150. *************************************************************/
  151. #define FEC_ECNTRL_ETHER_EN 0x00000002
  152. #define FEC_ECNTRL_RESET 0x00000001
  153. #define FEC_RCNTRL_BC_REJ 0x00000010
  154. #define FEC_RCNTRL_PROM 0x00000008
  155. #define FEC_RCNTRL_MII_MODE 0x00000004
  156. #define FEC_RCNTRL_DRT 0x00000002
  157. #define FEC_RCNTRL_LOOP 0x00000001
  158. #define FEC_TCNTRL_FDEN 0x00000004
  159. #define FEC_TCNTRL_HBC 0x00000002
  160. #define FEC_TCNTRL_GTS 0x00000001
  161. #define FEC_RESET_DELAY 50000
  162. int eth_init (bd_t * bd)
  163. {
  164. int i;
  165. volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
  166. /* Whack a reset.
  167. * A delay is required between a reset of the FEC block and
  168. * initialization of other FEC registers because the reset takes
  169. * some time to complete. If you don't delay, subsequent writes
  170. * to FEC registers might get killed by the reset routine which is
  171. * still in progress.
  172. */
  173. fecp->fec_ecntrl = FEC_ECNTRL_RESET;
  174. for (i = 0;
  175. (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
  176. ++i) {
  177. udelay (1);
  178. }
  179. if (i == FEC_RESET_DELAY) {
  180. printf ("FEC_RESET_DELAY timeout\n");
  181. return 0;
  182. }
  183. /* We use strictly polling mode only
  184. */
  185. fecp->fec_imask = 0;
  186. /* Clear any pending interrupt */
  187. fecp->fec_ievent = 0xffffffff;
  188. /* Set station address */
  189. #define ea bd->bi_enetaddr
  190. fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
  191. (ea[2] << 8) | (ea[3]);
  192. fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
  193. #ifdef ET_DEBUG
  194. printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
  195. ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
  196. #endif
  197. #undef ea
  198. /* Clear multicast address hash table
  199. */
  200. fecp->fec_hash_table_high = 0;
  201. fecp->fec_hash_table_low = 0;
  202. /* Set maximum receive buffer size.
  203. */
  204. fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
  205. /*
  206. * Setup Buffers and Buffer Desriptors
  207. */
  208. rxIdx = 0;
  209. txIdx = 0;
  210. if (!rtx) {
  211. rtx = (RTXBD *) CFG_ENET_BD_BASE;
  212. }
  213. /*
  214. * Setup Receiver Buffer Descriptors (13.14.24.18)
  215. * Settings:
  216. * Empty, Wrap
  217. */
  218. for (i = 0; i < PKTBUFSRX; i++) {
  219. rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  220. rtx->rxbd[i].cbd_datlen = 0; /* Reset */
  221. rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
  222. }
  223. rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  224. /*
  225. * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  226. * Settings:
  227. * Last, Tx CRC
  228. */
  229. for (i = 0; i < TX_BUF_CNT; i++) {
  230. rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
  231. rtx->txbd[i].cbd_datlen = 0; /* Reset */
  232. rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
  233. }
  234. rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
  235. /* Set receive and transmit descriptor base
  236. */
  237. fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
  238. fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
  239. /* Enable MII mode
  240. */
  241. #if 0 /* Full duplex mode */
  242. fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
  243. fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
  244. #else /* Half duplex mode */
  245. fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
  246. fecp->fec_x_cntrl = 0;
  247. #endif
  248. /* Set MII speed */
  249. fecp->fec_mii_speed = 0x0e;
  250. /* Configure port B for MII.
  251. */
  252. /* port initialization was already made in cpu_init_f() */
  253. /* Now enable the transmit and receive processing
  254. */
  255. fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
  256. #ifdef CFG_DISCOVER_PHY
  257. /* wait for the PHY to wake up after reset */
  258. mii_discover_phy ();
  259. #endif
  260. /* And last, try to fill Rx Buffer Descriptors */
  261. fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
  262. return 1;
  263. }
  264. void eth_halt (void)
  265. {
  266. volatile fec_t *fecp = (fec_t *) FEC_ADDR;
  267. fecp->fec_ecntrl = 0;
  268. }
  269. #if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
  270. static int phyaddr = -1; /* didn't find a PHY yet */
  271. static uint phytype;
  272. /* Make MII read/write commands for the FEC.
  273. */
  274. #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
  275. (REG & 0x1f) << 18))
  276. #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
  277. (REG & 0x1f) << 18) | \
  278. (VAL & 0xffff))
  279. /* Interrupt events/masks.
  280. */
  281. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  282. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  283. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  284. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  285. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  286. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  287. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  288. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  289. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  290. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  291. /* PHY identification
  292. */
  293. #define PHY_ID_LXT970 0x78100000 /* LXT970 */
  294. #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
  295. #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
  296. #define PHY_ID_QS6612 0x01814400 /* QS6612 */
  297. #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
  298. #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
  299. #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
  300. /* send command to phy using mii, wait for result */
  301. static uint mii_send (uint mii_cmd)
  302. {
  303. uint mii_reply;
  304. volatile fec_t *ep = (fec_t *) (FEC_ADDR);
  305. ep->fec_mii_data = mii_cmd; /* command to phy */
  306. /* wait for mii complete */
  307. while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */
  308. mii_reply = ep->fec_mii_data; /* result from phy */
  309. ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
  310. #ifdef ET_DEBUG
  311. printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
  312. __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
  313. #endif
  314. return (mii_reply & 0xffff); /* data read from phy */
  315. }
  316. #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
  317. #if defined(CFG_DISCOVER_PHY)
  318. static void mii_discover_phy (void)
  319. {
  320. #define MAX_PHY_PASSES 11
  321. uint phyno;
  322. int pass;
  323. phyaddr = -1; /* didn't find a PHY yet */
  324. for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
  325. if (pass > 1) {
  326. /* PHY may need more time to recover from reset.
  327. * The LXT970 needs 50ms typical, no maximum is
  328. * specified, so wait 10ms before try again.
  329. * With 11 passes this gives it 100ms to wake up.
  330. */
  331. udelay (10000); /* wait 10ms */
  332. }
  333. for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
  334. phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
  335. #ifdef ET_DEBUG
  336. printf ("PHY type 0x%x pass %d type ", phytype, pass);
  337. #endif
  338. if (phytype != 0xffff) {
  339. phyaddr = phyno;
  340. phytype <<= 16;
  341. phytype |= mii_send (mk_mii_read (phyno,
  342. PHY_PHYIDR2));
  343. #ifdef ET_DEBUG
  344. printf ("PHY @ 0x%x pass %d type ", phyno,
  345. pass);
  346. switch (phytype & 0xfffffff0) {
  347. case PHY_ID_LXT970:
  348. printf ("LXT970\n");
  349. break;
  350. case PHY_ID_LXT971:
  351. printf ("LXT971\n");
  352. break;
  353. case PHY_ID_82555:
  354. printf ("82555\n");
  355. break;
  356. case PHY_ID_QS6612:
  357. printf ("QS6612\n");
  358. break;
  359. case PHY_ID_AMD79C784:
  360. printf ("AMD79C784\n");
  361. break;
  362. case PHY_ID_LSI80225B:
  363. printf ("LSI L80225/B\n");
  364. break;
  365. default:
  366. printf ("0x%08x\n", phytype);
  367. break;
  368. }
  369. #endif
  370. }
  371. }
  372. }
  373. if (phyaddr < 0) {
  374. printf ("No PHY device found.\n");
  375. }
  376. }
  377. #endif /* CFG_DISCOVER_PHY */
  378. #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
  379. static int mii_init_done = 0;
  380. /****************************************************************************
  381. * mii_init -- Initialize the MII for MII command without ethernet
  382. * This function is a subset of eth_init
  383. ****************************************************************************
  384. */
  385. void mii_init (void)
  386. {
  387. volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
  388. int i;
  389. if (mii_init_done != 0) {
  390. return;
  391. }
  392. /* Whack a reset.
  393. * A delay is required between a reset of the FEC block and
  394. * initialization of other FEC registers because the reset takes
  395. * some time to complete. If you don't delay, subsequent writes
  396. * to FEC registers might get killed by the reset routine which is
  397. * still in progress.
  398. */
  399. fecp->fec_ecntrl = FEC_ECNTRL_RESET;
  400. for (i = 0;
  401. (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
  402. ++i) {
  403. udelay (1);
  404. }
  405. if (i == FEC_RESET_DELAY) {
  406. printf ("FEC_RESET_DELAY timeout\n");
  407. return;
  408. }
  409. /* We use strictly polling mode only
  410. */
  411. fecp->fec_imask = 0;
  412. /* Clear any pending interrupt
  413. */
  414. fecp->fec_ievent = 0xffffffff;
  415. /* Set MII speed */
  416. fecp->fec_mii_speed = 0x0e;
  417. /* Configure port B for MII.
  418. */
  419. /* port initialization was already made in cpu_init_f() */
  420. /* Now enable the transmit and receive processing */
  421. fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
  422. mii_init_done = 1;
  423. }
  424. /*****************************************************************************
  425. * Read and write a MII PHY register, routines used by MII Utilities
  426. *
  427. * FIXME: These routines are expected to return 0 on success, but mii_send
  428. * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
  429. * no PHY connected...
  430. * For now always return 0.
  431. * FIXME: These routines only work after calling eth_init() at least once!
  432. * Otherwise they hang in mii_send() !!! Sorry!
  433. *****************************************************************************/
  434. int mcf52x2_miiphy_read (char *devname, unsigned char addr,
  435. unsigned char reg, unsigned short *value)
  436. {
  437. short rdreg; /* register working value */
  438. #ifdef MII_DEBUG
  439. printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
  440. #endif
  441. rdreg = mii_send (mk_mii_read (addr, reg));
  442. *value = rdreg;
  443. #ifdef MII_DEBUG
  444. printf ("0x%04x\n", *value);
  445. #endif
  446. return 0;
  447. }
  448. int mcf52x2_miiphy_write (char *devname, unsigned char addr,
  449. unsigned char reg, unsigned short value)
  450. {
  451. short rdreg; /* register working value */
  452. #ifdef MII_DEBUG
  453. printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
  454. #endif
  455. rdreg = mii_send (mk_mii_write (addr, reg, value));
  456. #ifdef MII_DEBUG
  457. printf ("0x%04x\n", value);
  458. #endif
  459. return 0;
  460. }
  461. #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
  462. #endif /* CFG_CMD_NET, FEC_ENET */
  463. int mcf52x2_miiphy_initialize(bd_t *bis)
  464. {
  465. #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
  466. #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
  467. miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
  468. #endif
  469. #endif
  470. return 0;
  471. }