pci.c 6.0 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. */
  24. #include <asm/mmu.h>
  25. #include <common.h>
  26. #include <pci.h>
  27. #ifdef CONFIG_PCI
  28. /* System RAM mapped to PCI space */
  29. #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
  30. #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
  31. #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  32. #ifndef CONFIG_PCI_PNP
  33. static struct pci_config_table pci_tqm834x_config_table[] = {
  34. {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  35. PCI_IDSEL_NUMBER, PCI_ANY_ID,
  36. pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
  37. PCI_ENET0_MEMADDR,
  38. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
  39. }
  40. },
  41. {}
  42. };
  43. #endif
  44. static struct pci_controller pci1_hose = {
  45. #ifndef CONFIG_PCI_PNP
  46. config_table:pci_tqm834x_config_table,
  47. #endif
  48. };
  49. /**************************************************************************
  50. * pci_init_board()
  51. *
  52. * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
  53. * per TQM834x design physical connections to external devices (PCI sockets)
  54. * are routed only to the PCI1 we do not account for the second one - this code
  55. * supports PCI1 module only. Should support for the PCI2 be required in the
  56. * future it needs a separate pci_controller structure (above) and handling -
  57. * please refer to other boards' implementation for dual PCI host controllers,
  58. * for example board/Marvell/db64360/pci.c, pci_init_board()
  59. *
  60. */
  61. void
  62. pci_init_board(void)
  63. {
  64. volatile immap_t * immr;
  65. volatile clk8349_t * clk;
  66. volatile law8349_t * pci_law;
  67. volatile pot8349_t * pci_pot;
  68. volatile pcictrl8349_t * pci_ctrl;
  69. volatile pciconf8349_t * pci_conf;
  70. u16 reg16;
  71. u32 reg32;
  72. struct pci_controller * hose;
  73. immr = (immap_t *)CFG_IMMRBAR;
  74. clk = (clk8349_t *)&immr->clk;
  75. pci_law = immr->sysconf.pcilaw;
  76. pci_pot = immr->ios.pot;
  77. pci_ctrl = immr->pci_ctrl;
  78. pci_conf = immr->pci_conf;
  79. hose = &pci1_hose;
  80. /*
  81. * Configure PCI controller and PCI_CLK_OUTPUT
  82. */
  83. /*
  84. * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
  85. * line actually used for clocking all external PCI devices in TQM83xx.
  86. * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
  87. * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
  88. * are known to hang the board; this issue is under investigation
  89. * (13 oct 05)
  90. */
  91. reg32 = OCCR_PCICOE1;
  92. #if 0
  93. /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
  94. reg32 = 0xff000000;
  95. #endif
  96. if (clk->spmr & SPMR_CKID) {
  97. /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
  98. * fields accordingly */
  99. reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
  100. reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
  101. | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
  102. | OCCR_PCICD6 | OCCR_PCICD7);
  103. }
  104. clk->occr = reg32;
  105. udelay(2000);
  106. /*
  107. * Release PCI RST Output signal
  108. */
  109. pci_ctrl[0].gcr = 0;
  110. udelay(2000);
  111. pci_ctrl[0].gcr = 1;
  112. udelay(2000);
  113. /*
  114. * Configure PCI Local Access Windows
  115. */
  116. pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
  117. pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
  118. pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
  119. pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
  120. /*
  121. * Configure PCI Outbound Translation Windows
  122. */
  123. /* PCI1 mem space */
  124. pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
  125. pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
  126. pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
  127. /* PCI1 IO space */
  128. pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
  129. pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
  130. pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
  131. /*
  132. * Configure PCI Inbound Translation Windows
  133. */
  134. /* we need RAM mapped to PCI space for the devices to
  135. * access main memory */
  136. pci_ctrl[0].pitar1 = 0x0;
  137. pci_ctrl[0].pibar1 = 0x0;
  138. pci_ctrl[0].piebar1 = 0x0;
  139. pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M;
  140. hose->first_busno = 0;
  141. hose->last_busno = 0xff;
  142. /* PCI memory space */
  143. pci_set_region(hose->regions + 0,
  144. CFG_PCI1_MEM_BASE,
  145. CFG_PCI1_MEM_PHYS,
  146. CFG_PCI1_MEM_SIZE,
  147. PCI_REGION_MEM);
  148. /* PCI IO space */
  149. pci_set_region(hose->regions + 1,
  150. CFG_PCI1_IO_BASE,
  151. CFG_PCI1_IO_PHYS,
  152. CFG_PCI1_IO_SIZE,
  153. PCI_REGION_IO);
  154. /* System memory space */
  155. pci_set_region(hose->regions + 2,
  156. CONFIG_PCI_SYS_MEM_BUS,
  157. CONFIG_PCI_SYS_MEM_PHYS,
  158. CONFIG_PCI_SYS_MEM_SIZE,
  159. PCI_REGION_MEM | PCI_REGION_MEMORY);
  160. hose->region_count = 3;
  161. pci_setup_indirect(hose,
  162. (CFG_IMMRBAR+0x8300),
  163. (CFG_IMMRBAR+0x8304));
  164. pci_register_hose(hose);
  165. /*
  166. * Write to Command register
  167. */
  168. reg16 = 0xff;
  169. pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
  170. &reg16);
  171. reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  172. pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
  173. reg16);
  174. /*
  175. * Clear non-reserved bits in status register.
  176. */
  177. pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
  178. 0xffff);
  179. pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
  180. 0x80);
  181. #ifdef CONFIG_PCI_SCAN_SHOW
  182. printf("PCI: Bus Dev VenId DevId Class Int\n");
  183. #endif
  184. /*
  185. * Hose scan.
  186. */
  187. hose->last_busno = pci_hose_scan(hose);
  188. }
  189. #endif /* CONFIG_PCI */