p3p440.c 7.9 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include <asm/processor.h>
  27. #include <command.h>
  28. #include "p3p440.h"
  29. void set_led(int color)
  30. {
  31. switch (color) {
  32. case LED_OFF:
  33. out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED);
  34. break;
  35. case LED_GREEN:
  36. out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED);
  37. break;
  38. case LED_RED:
  39. out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN);
  40. break;
  41. case LED_ORANGE:
  42. out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED);
  43. break;
  44. }
  45. }
  46. static int is_monarch(void)
  47. {
  48. out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_GPIO_RDY);
  49. udelay(1000);
  50. if (in32(GPIO0_IR) & CFG_MONARCH_IO)
  51. return 0;
  52. else
  53. return 1;
  54. }
  55. static void wait_for_pci_ready(void)
  56. {
  57. /*
  58. * Configure EREADY_IO as input
  59. */
  60. out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO);
  61. udelay(1000);
  62. for (;;) {
  63. if (in32(GPIO0_IR) & CFG_EREADY_IO)
  64. return;
  65. }
  66. }
  67. int board_early_init_f(void)
  68. {
  69. uint reg;
  70. /*--------------------------------------------------------------------
  71. * Setup the external bus controller/chip selects
  72. *-------------------------------------------------------------------*/
  73. mtdcr(ebccfga, xbcfg);
  74. reg = mfdcr(ebccfgd);
  75. mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
  76. /*--------------------------------------------------------------------
  77. * Setup pin multiplexing (GPIO/IRQ...)
  78. *-------------------------------------------------------------------*/
  79. mtdcr(cpc0_gpio, 0x03F01F80);
  80. out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
  81. out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN);
  82. out32(GPIO0_OR, CFG_GPIO_RDY);
  83. /*--------------------------------------------------------------------
  84. * Setup the interrupt controller polarities, triggers, etc.
  85. *-------------------------------------------------------------------*/
  86. mtdcr(uic0sr, 0xffffffff); /* clear all */
  87. mtdcr(uic0er, 0x00000000); /* disable all */
  88. mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
  89. mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
  90. mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
  91. mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
  92. mtdcr(uic0sr, 0xffffffff); /* clear all */
  93. mtdcr(uic1sr, 0xffffffff); /* clear all */
  94. mtdcr(uic1er, 0x00000000); /* disable all */
  95. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  96. mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
  97. mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
  98. mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
  99. mtdcr(uic1sr, 0xffffffff); /* clear all */
  100. return 0;
  101. }
  102. int checkboard(void)
  103. {
  104. char *s = getenv("serial#");
  105. printf("Board: P3P440");
  106. if (s != NULL) {
  107. puts(", serial# ");
  108. puts(s);
  109. }
  110. if (is_monarch()) {
  111. puts(", Monarch");
  112. } else {
  113. puts(", None-Monarch");
  114. }
  115. putc('\n');
  116. return (0);
  117. }
  118. int misc_init_r (void)
  119. {
  120. DECLARE_GLOBAL_DATA_PTR;
  121. /*
  122. * Adjust flash start and offset to detected values
  123. */
  124. gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  125. gd->bd->bi_flashoffset = 0;
  126. /*
  127. * Check if only one FLASH bank is available
  128. */
  129. if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
  130. mtebc(pb1cr, 0); /* disable cs */
  131. mtebc(pb1ap, 0);
  132. mtebc(pb2cr, 0); /* disable cs */
  133. mtebc(pb2ap, 0);
  134. mtebc(pb3cr, 0); /* disable cs */
  135. mtebc(pb3ap, 0);
  136. }
  137. return 0;
  138. }
  139. /*************************************************************************
  140. * pci_pre_init
  141. *
  142. * This routine is called just prior to registering the hose and gives
  143. * the board the opportunity to check things. Returning a value of zero
  144. * indicates that things are bad & PCI initialization should be aborted.
  145. *
  146. * Different boards may wish to customize the pci controller structure
  147. * (add regions, override default access routines, etc) or perform
  148. * certain pre-initialization actions.
  149. *
  150. ************************************************************************/
  151. #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
  152. int pci_pre_init(struct pci_controller *hose)
  153. {
  154. unsigned long strap;
  155. /*--------------------------------------------------------------------------+
  156. * The P3P440 board is always configured as the host & requires the
  157. * PCI arbiter to be disabled because it's an PMC module.
  158. *--------------------------------------------------------------------------*/
  159. strap = mfdcr(cpc0_strp1);
  160. if (strap & 0x00100000) {
  161. printf("PCI: CPC0_STRP1[PAE] set.\n");
  162. return 0;
  163. }
  164. return 1;
  165. }
  166. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
  167. /*************************************************************************
  168. * pci_target_init
  169. *
  170. * The bootstrap configuration provides default settings for the pci
  171. * inbound map (PIM). But the bootstrap config choices are limited and
  172. * may not be sufficient for a given board.
  173. *
  174. ************************************************************************/
  175. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  176. void pci_target_init(struct pci_controller *hose)
  177. {
  178. DECLARE_GLOBAL_DATA_PTR;
  179. /*--------------------------------------------------------------------------+
  180. * Disable everything
  181. *--------------------------------------------------------------------------*/
  182. out32r(PCIX0_PIM0SA, 0); /* disable */
  183. out32r(PCIX0_PIM1SA, 0); /* disable */
  184. out32r(PCIX0_PIM2SA, 0); /* disable */
  185. out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
  186. /*--------------------------------------------------------------------------+
  187. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
  188. * options to not support sizes such as 128/256 MB.
  189. *--------------------------------------------------------------------------*/
  190. out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
  191. out32r(PCIX0_PIM0LAH, 0);
  192. out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
  193. out32r(PCIX0_BAR0, 0);
  194. /*--------------------------------------------------------------------------+
  195. * Program the board's subsystem id/vendor id
  196. *--------------------------------------------------------------------------*/
  197. out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
  198. out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
  199. out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
  200. }
  201. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  202. /*************************************************************************
  203. * is_pci_host
  204. *
  205. * This routine is called to determine if a pci scan should be
  206. * performed. With various hardware environments (especially cPCI and
  207. * PPMC) it's insufficient to depend on the state of the arbiter enable
  208. * bit in the strap register, or generic host/adapter assumptions.
  209. *
  210. * Rather than hard-code a bad assumption in the general 440 code, the
  211. * 440 pci code requires the board to decide at runtime.
  212. *
  213. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  214. *
  215. *
  216. ************************************************************************/
  217. #if defined(CONFIG_PCI)
  218. int is_pci_host(struct pci_controller *hose)
  219. {
  220. if (is_monarch()) {
  221. wait_for_pci_ready();
  222. return 1; /* return 1 for host controller */
  223. } else {
  224. return 0; /* return 0 for adapter controller */
  225. }
  226. }
  227. #endif /* defined(CONFIG_PCI) */