mpc8260ads.c 20 KB

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  1. /*
  2. * (C) Copyright 2001-2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Modified during 2001 by
  6. * Advanced Communications Technologies (Australia) Pty. Ltd.
  7. * Howard Walker, Tuong Vu-Dinh
  8. *
  9. * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
  10. * Added support for the 16M dram simm on the 8260ads boards
  11. *
  12. * (C) Copyright 2003-2004 Arabella Software Ltd.
  13. * Yuli Barcohen <yuli@arabellasw.com>
  14. * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
  15. *
  16. * Copyright (c) 2005 MontaVista Software, Inc.
  17. * Vitaly Bordug <vbordug@ru.mvista.com>
  18. * Added support for PCI.
  19. *
  20. * See file CREDITS for list of people who contributed to this
  21. * project.
  22. *
  23. * This program is free software; you can redistribute it and/or
  24. * modify it under the terms of the GNU General Public License as
  25. * published by the Free Software Foundation; either version 2 of
  26. * the License, or (at your option) any later version.
  27. *
  28. * This program is distributed in the hope that it will be useful,
  29. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  31. * GNU General Public License for more details.
  32. *
  33. * You should have received a copy of the GNU General Public License
  34. * along with this program; if not, write to the Free Software
  35. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  36. * MA 02111-1307 USA
  37. */
  38. #include <common.h>
  39. #include <ioports.h>
  40. #include <mpc8260.h>
  41. #include <asm/m8260_pci.h>
  42. #include <i2c.h>
  43. #include <spd.h>
  44. #include <miiphy.h>
  45. #ifdef CONFIG_PCI
  46. #include <pci.h>
  47. #endif
  48. /*
  49. * I/O Port configuration table
  50. *
  51. * if conf is 1, then that port pin will be configured at boot time
  52. * according to the five values podr/pdir/ppar/psor/pdat for that entry
  53. */
  54. #define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
  55. #define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
  56. #define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
  57. const iop_conf_t iop_conf_tab[4][32] = {
  58. /* Port A configuration */
  59. { /* conf ppar psor pdir podr pdat */
  60. /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
  61. /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
  62. /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
  63. /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
  64. /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
  65. /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
  66. /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
  67. /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
  68. /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
  69. /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
  70. /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
  71. /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
  72. /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
  73. /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
  74. /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
  75. /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
  76. /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
  77. /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
  78. /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
  79. /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
  80. /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
  81. /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
  82. /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
  83. /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
  84. /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
  85. /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
  86. /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
  87. /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
  88. /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
  89. /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
  90. /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
  91. /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
  92. },
  93. /* Port B configuration */
  94. { /* conf ppar psor pdir podr pdat */
  95. /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
  96. /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
  97. /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
  98. /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
  99. /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
  100. /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
  101. /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
  102. /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
  103. /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
  104. /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
  105. /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
  106. /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
  107. /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
  108. /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
  109. /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
  110. /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
  111. /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
  112. /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
  113. /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
  114. /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
  115. /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  116. /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  117. /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  118. /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  119. /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  120. /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  121. /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  122. /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  123. /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  124. /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  125. /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  126. /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  127. },
  128. /* Port C */
  129. { /* conf ppar psor pdir podr pdat */
  130. /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
  131. /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
  132. /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
  133. /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
  134. /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
  135. /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
  136. /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
  137. /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
  138. /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
  139. /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
  140. /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
  141. /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
  142. #if CONFIG_ADSTYPE == CFG_8272ADS
  143. /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
  144. /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
  145. /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
  146. /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
  147. #else
  148. /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
  149. /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
  150. /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
  151. /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
  152. #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
  153. /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
  154. /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
  155. /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
  156. /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
  157. /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
  158. #if CONFIG_ADSTYPE == CFG_8272ADS
  159. /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
  160. /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
  161. #else
  162. /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
  163. /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
  164. #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
  165. /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
  166. /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
  167. /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
  168. /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
  169. /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
  170. /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
  171. /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
  172. /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
  173. /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
  174. },
  175. /* Port D */
  176. { /* conf ppar psor pdir podr pdat */
  177. /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
  178. /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
  179. /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
  180. /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
  181. /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
  182. /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
  183. /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
  184. /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
  185. /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
  186. /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
  187. /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
  188. /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
  189. /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
  190. /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
  191. /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
  192. /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
  193. /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
  194. /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
  195. /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  196. /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  197. /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  198. /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  199. /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
  200. /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
  201. /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
  202. /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
  203. /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
  204. /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
  205. /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  206. /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  207. /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  208. /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  209. }
  210. };
  211. void reset_phy (void)
  212. {
  213. vu_long *bcsr = (vu_long *)CFG_BCSR;
  214. /* Reset the PHY */
  215. #if CFG_PHY_ADDR == 0
  216. bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
  217. udelay(2);
  218. bcsr[1] |= FETH1_RST;
  219. #else
  220. bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
  221. udelay(2);
  222. bcsr[3] |= FETH2_RST;
  223. #endif /* CFG_PHY_ADDR == 0 */
  224. udelay(1000);
  225. #ifdef CONFIG_MII
  226. #if CONFIG_ADSTYPE >= CFG_PQ2FADS
  227. /*
  228. * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
  229. * Enable autonegotiation.
  230. */
  231. bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
  232. bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
  233. PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  234. #else
  235. /*
  236. * Ethernet PHY is configured (by means of configuration pins)
  237. * to work at 10Mb/s only. We reconfigure it using MII
  238. * to advertise all capabilities, including 100Mb/s, and
  239. * restart autonegotiation.
  240. */
  241. /* Advertise all capabilities */
  242. bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
  243. /* Do not bypass Rx/Tx (de)scrambler */
  244. bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000);
  245. bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
  246. PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  247. #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
  248. #endif /* CONFIG_MII */
  249. }
  250. #ifdef CONFIG_PCI
  251. typedef struct pci_ic_s {
  252. unsigned long pci_int_stat;
  253. unsigned long pci_int_mask;
  254. }pci_ic_t;
  255. #endif
  256. int board_early_init_f (void)
  257. {
  258. vu_long *bcsr = (vu_long *)CFG_BCSR;
  259. #ifdef CONFIG_PCI
  260. volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
  261. /* mask alll the PCI interrupts */
  262. pci_ic->pci_int_mask |= 0xfff00000;
  263. #endif
  264. #if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
  265. bcsr[1] &= ~RS232EN_1;
  266. #endif
  267. #if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
  268. bcsr[1] &= ~RS232EN_2;
  269. #endif
  270. #if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
  271. #if CONFIG_ADSTYPE == CFG_PQ2FADS
  272. if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
  273. #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
  274. {
  275. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  276. immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
  277. immap->im_siu_conf.sc_siumcr =
  278. (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
  279. | SIUMCR_LBPC01;
  280. }
  281. #endif /* CONFIG_ADSTYPE != CFG_8260ADS */
  282. return 0;
  283. }
  284. #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
  285. long int initdram (int board_type)
  286. {
  287. #if CONFIG_ADSTYPE == CFG_PQ2FADS
  288. long int msize = 32;
  289. #elif CONFIG_ADSTYPE == CFG_8272ADS
  290. long int msize = 64;
  291. #else
  292. long int msize = 16;
  293. #endif
  294. #ifndef CFG_RAMBOOT
  295. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  296. volatile memctl8260_t *memctl = &immap->im_memctl;
  297. volatile uchar *ramaddr, c = 0xff;
  298. uint or;
  299. uint psdmr;
  300. uint psrt;
  301. int i;
  302. immap->im_siu_conf.sc_ppc_acr = 0x00000002;
  303. immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
  304. immap->im_siu_conf.sc_tescr1 = 0x00004000;
  305. memctl->memc_mptpr = CFG_MPTPR;
  306. #ifdef CFG_LSDRAM_BASE
  307. /*
  308. Initialise local bus SDRAM only if the pins
  309. are configured as local bus pins and not as PCI.
  310. The configuration is determined by the HRCW.
  311. */
  312. if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
  313. memctl->memc_lsrt = CFG_LSRT;
  314. #if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
  315. memctl->memc_or3 = 0xFF803280;
  316. memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
  317. #else /* CS4 */
  318. memctl->memc_or4 = 0xFFC01480;
  319. memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
  320. #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
  321. memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
  322. ramaddr = (uchar *) CFG_LSDRAM_BASE;
  323. *ramaddr = c;
  324. memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
  325. for (i = 0; i < 8; i++)
  326. *ramaddr = c;
  327. memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
  328. *ramaddr = c;
  329. memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
  330. }
  331. #endif /* CFG_LSDRAM_BASE */
  332. /* Init 60x bus SDRAM */
  333. #ifdef CONFIG_SPD_EEPROM
  334. {
  335. spd_eeprom_t spd;
  336. uint pbi, bsel, rowst, lsb, tmp;
  337. i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
  338. /* Bank-based interleaving is not supported for physical bank
  339. sizes greater than 128MB which is encoded as 0x20 in SPD
  340. */
  341. pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
  342. msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
  343. or = ~(msize - 1) << 20; /* SDAM */
  344. switch (spd.nbanks) { /* BPD */
  345. case 2:
  346. bsel = 1;
  347. break;
  348. case 4:
  349. bsel = 2;
  350. or |= 0x00002000;
  351. break;
  352. case 8:
  353. bsel = 3;
  354. or |= 0x00004000;
  355. break;
  356. }
  357. lsb = 3; /* For 64-bit port, lsb is 3 bits */
  358. if (pbi) { /* Bus partition depends on interleaving */
  359. rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
  360. or |= (rowst << 9); /* ROWST */
  361. } else {
  362. rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
  363. or |= ((rowst * 2 - 12) << 9); /* ROWST */
  364. }
  365. or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
  366. psdmr = (pbi << 31); /* PBI */
  367. /* Bus multiplexing parameters */
  368. tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
  369. psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
  370. psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
  371. tmp = (31 - lsb - 10) - tmp;
  372. /* Pin connected to SDA10 is (31 - lsb - 10).
  373. rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
  374. so (rowst + tmp) alternates with AP.
  375. */
  376. if (pbi) /* Table 10-7 */
  377. psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
  378. else
  379. psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
  380. /* SDRAM device-specific parameters */
  381. tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
  382. switch (tmp) { /* RFRC */
  383. case 1:
  384. case 2:
  385. psdmr |= (1 << 15);
  386. break;
  387. case 3:
  388. case 4:
  389. case 5:
  390. case 6:
  391. case 7:
  392. case 8:
  393. psdmr |= ((tmp - 2) << 15);
  394. break;
  395. default:
  396. psdmr |= (7 << 15);
  397. }
  398. psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
  399. psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
  400. /* BL=0 because for 64-bit SDRAM burst length must be 4 */
  401. /* LDOTOPRE ??? */
  402. for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
  403. tmp >>= 1;
  404. switch (i) { /* WRC */
  405. case 0:
  406. case 1:
  407. psdmr |= (1 << 4);
  408. break;
  409. case 2:
  410. case 3:
  411. psdmr |= (i << 4);
  412. break;
  413. }
  414. /* EAMUX=0 - no external address multiplexing */
  415. /* BUFCMD=0 - no external buffers */
  416. for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
  417. tmp >>= 1;
  418. psdmr |= i; /* CL */
  419. switch (spd.refresh & 0x7F) {
  420. case 1:
  421. tmp = 3900;
  422. break;
  423. case 2:
  424. tmp = 7800;
  425. break;
  426. case 3:
  427. tmp = 31300;
  428. break;
  429. case 4:
  430. tmp = 62500;
  431. break;
  432. case 5:
  433. tmp = 125000;
  434. break;
  435. default:
  436. tmp = 15625;
  437. }
  438. psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
  439. ((memctl->memc_mptpr >> 8) + 1)) - 1;
  440. #ifdef SPD_DEBUG
  441. printf ("\nDIMM type: %-18.18s\n", spd.mpart);
  442. printf ("SPD size: %d\n", spd.info_size);
  443. printf ("EEPROM size: %d\n", 1 << spd.chip_size);
  444. printf ("Memory type: %d\n", spd.mem_type);
  445. printf ("Row addr: %d\n", spd.nrow_addr);
  446. printf ("Column addr: %d\n", spd.ncol_addr);
  447. printf ("# of rows: %d\n", spd.nrows);
  448. printf ("Row density: %d\n", spd.row_dens);
  449. printf ("# of banks: %d\n", spd.nbanks);
  450. printf ("Data width: %d\n",
  451. 256 * spd.dataw_msb + spd.dataw_lsb);
  452. printf ("Chip width: %d\n", spd.primw);
  453. printf ("Refresh rate: %02X\n", spd.refresh);
  454. printf ("CAS latencies: %02X\n", spd.cas_lat);
  455. printf ("Write latencies: %02X\n", spd.write_lat);
  456. printf ("tRP: %d\n", spd.trp);
  457. printf ("tRCD: %d\n", spd.trcd);
  458. printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
  459. #endif /* SPD_DEBUG */
  460. }
  461. #else /* !CONFIG_SPD_EEPROM */
  462. or = CFG_OR2;
  463. psdmr = CFG_PSDMR;
  464. psrt = CFG_PSRT;
  465. #endif /* CONFIG_SPD_EEPROM */
  466. memctl->memc_psrt = psrt;
  467. memctl->memc_or2 = or;
  468. memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
  469. ramaddr = (uchar *) CFG_SDRAM_BASE;
  470. memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
  471. *ramaddr = c;
  472. memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
  473. for (i = 0; i < 8; i++)
  474. *ramaddr = c;
  475. memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
  476. *ramaddr = c;
  477. memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
  478. *ramaddr = c;
  479. #endif /* CFG_RAMBOOT */
  480. /* return total 60x bus SDRAM size */
  481. return (msize * 1024 * 1024);
  482. }
  483. int checkboard (void)
  484. {
  485. #if CONFIG_ADSTYPE == CFG_8260ADS
  486. puts ("Board: Motorola MPC8260ADS\n");
  487. #elif CONFIG_ADSTYPE == CFG_8266ADS
  488. puts ("Board: Motorola MPC8266ADS\n");
  489. #elif CONFIG_ADSTYPE == CFG_PQ2FADS
  490. puts ("Board: Motorola PQ2FADS-ZU\n");
  491. #elif CONFIG_ADSTYPE == CFG_8272ADS
  492. puts ("Board: Motorola MPC8272ADS\n");
  493. #else
  494. puts ("Board: unknown\n");
  495. #endif
  496. return 0;
  497. }
  498. #ifdef CONFIG_PCI
  499. struct pci_controller hose;
  500. extern void pci_mpc8250_init(struct pci_controller *);
  501. void pci_init_board(void)
  502. {
  503. pci_mpc8250_init(&hose);
  504. }
  505. #endif