lowlevel_init.S 5.4 KB

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  1. /*
  2. * Memory sub-system initialization code for INCA-IP development board.
  3. *
  4. * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <config.h>
  25. #include <version.h>
  26. #include <asm/regdef.h>
  27. #define EBU_MODUL_BASE 0xB8000200
  28. #define EBU_CLC(value) 0x0000(value)
  29. #define EBU_CON(value) 0x0010(value)
  30. #define EBU_ADDSEL0(value) 0x0020(value)
  31. #define EBU_ADDSEL1(value) 0x0024(value)
  32. #define EBU_ADDSEL2(value) 0x0028(value)
  33. #define EBU_BUSCON0(value) 0x0060(value)
  34. #define EBU_BUSCON1(value) 0x0064(value)
  35. #define EBU_BUSCON2(value) 0x0068(value)
  36. #define MC_MODUL_BASE 0xBF800000
  37. #define MC_ERRCAUSE(value) 0x0100(value)
  38. #define MC_ERRADDR(value) 0x0108(value)
  39. #define MC_IOGP(value) 0x0800(value)
  40. #define MC_SELFRFSH(value) 0x0A00(value)
  41. #define MC_CTRLENA(value) 0x1000(value)
  42. #define MC_MRSCODE(value) 0x1008(value)
  43. #define MC_CFGDW(value) 0x1010(value)
  44. #define MC_CFGPB0(value) 0x1018(value)
  45. #define MC_LATENCY(value) 0x1038(value)
  46. #define MC_TREFRESH(value) 0x1040(value)
  47. #define CGU_MODUL_BASE 0xBF107000
  48. #define CGU_PLL1CR(value) 0x0008(value)
  49. #define CGU_DIVCR(value) 0x0010(value)
  50. #define CGU_MUXCR(value) 0x0014(value)
  51. #define CGU_PLL1SR(value) 0x000C(value)
  52. .set noreorder
  53. /*
  54. * void ebu_init(long)
  55. *
  56. * a0 has the clock value we are going to run at
  57. */
  58. .globl ebu_init
  59. .ent ebu_init
  60. ebu_init:
  61. __ebu_init:
  62. li t1, EBU_MODUL_BASE
  63. li t2, 0xA0000041
  64. sw t2, EBU_ADDSEL0(t1)
  65. li t2, 0xA0800041
  66. sw t2, EBU_ADDSEL2(t1)
  67. li t2, 0xBE0000F1
  68. sw t2, EBU_ADDSEL1(t1)
  69. li t3, 100000000
  70. beq a0, t3, 1f
  71. nop
  72. li t3, 133000000
  73. beq a0, t3, 2f
  74. nop
  75. li t3, 150000000
  76. beq a0, t3, 2f
  77. nop
  78. b 3f
  79. nop
  80. /* 100 MHz */
  81. 1:
  82. li t2, 0x8841417D
  83. sw t2, EBU_BUSCON0(t1)
  84. sw t2, EBU_BUSCON2(t1)
  85. li t2, 0x684142BD
  86. b 3f
  87. sw t2, EBU_BUSCON1(t1) /* delay slot */
  88. /* 133 or 150 MHz */
  89. 2:
  90. li t2, 0x8841417E
  91. sw t2, EBU_BUSCON0(t1)
  92. sw t2, EBU_BUSCON2(t1)
  93. li t2, 0x684143FD
  94. sw t2, EBU_BUSCON1(t1)
  95. 3:
  96. j ra
  97. nop
  98. .end ebu_init
  99. /*
  100. * void cgu_init(long)
  101. *
  102. * a0 has the clock value
  103. */
  104. .globl cgu_init
  105. .ent cgu_init
  106. cgu_init:
  107. __cgu_init:
  108. li t1, CGU_MODUL_BASE
  109. li t3, 100000000
  110. beq a0, t3, 1f
  111. nop
  112. li t3, 133000000
  113. beq a0, t3, 2f
  114. nop
  115. li t3, 150000000
  116. beq a0, t3, 3f
  117. nop
  118. b 5f
  119. nop
  120. /* 100 MHz clock */
  121. 1:
  122. li t2, 0x80000014
  123. sw t2, CGU_DIVCR(t1)
  124. li t2, 0x80000000
  125. sw t2, CGU_MUXCR(t1)
  126. li t2, 0x800B0001
  127. b 5f
  128. sw t2, CGU_PLL1CR(t1) /* delay slot */
  129. /* 133 MHz clock */
  130. 2:
  131. li t2, 0x80000054
  132. sw t2, CGU_DIVCR(t1)
  133. li t2, 0x80000000
  134. sw t2, CGU_MUXCR(t1)
  135. li t2, 0x800B0001
  136. b 5f
  137. sw t2, CGU_PLL1CR(t1) /* delay slot */
  138. /* 150 MHz clock */
  139. 3:
  140. li t2, 0x80000017
  141. sw t2, CGU_DIVCR(t1)
  142. li t2, 0xC00B0001
  143. sw t2, CGU_PLL1CR(t1)
  144. li t3, 0x80000000
  145. 4:
  146. lw t2, CGU_PLL1SR(t1)
  147. and t2, t2, t3
  148. beq t2, zero, 4b
  149. nop
  150. li t2, 0x80000001
  151. sw t2, CGU_MUXCR(t1)
  152. 5:
  153. j ra
  154. nop
  155. .end cgu_init
  156. /*
  157. * void sdram_init(long)
  158. *
  159. * a0 has the clock value
  160. */
  161. .globl sdram_init
  162. .ent sdram_init
  163. sdram_init:
  164. __sdram_init:
  165. li t1, MC_MODUL_BASE
  166. #if 0
  167. /* Disable memory controller before changing any of its registers */
  168. sw zero, MC_CTRLENA(t1)
  169. #endif
  170. li t2, 100000000
  171. beq a0, t2, 1f
  172. nop
  173. li t2, 133000000
  174. beq a0, t2, 2f
  175. nop
  176. li t2, 150000000
  177. beq a0, t2, 3f
  178. nop
  179. b 5f
  180. nop
  181. /* 100 MHz clock */
  182. 1:
  183. /* Set clock ratio (clkrat=1:1, rddel=3) */
  184. li t2, 0x00000003
  185. sw t2, MC_IOGP(t1)
  186. /* Set sdram refresh rate (4K/64ms @ 100MHz) */
  187. li t2, 0x0000061A
  188. b 4f
  189. sw t2, MC_TREFRESH(t1)
  190. /* 133 MHz clock */
  191. 2:
  192. /* Set clock ratio (clkrat=1:1, rddel=3) */
  193. li t2, 0x00000003
  194. sw t2, MC_IOGP(t1)
  195. /* Set sdram refresh rate (4K/64ms @ 133MHz) */
  196. li t2, 0x00000822
  197. b 4f
  198. sw t2, MC_TREFRESH(t1)
  199. /* 150 MHz clock */
  200. 3:
  201. /* Set clock ratio (clkrat=3:2, rddel=4) */
  202. li t2, 0x00000014
  203. sw t2, MC_IOGP(t1)
  204. /* Set sdram refresh rate (4K/64ms @ 150MHz) */
  205. li t2, 0x00000927
  206. sw t2, MC_TREFRESH(t1)
  207. 4:
  208. /* Clear Error log registers */
  209. sw zero, MC_ERRCAUSE(t1)
  210. sw zero, MC_ERRADDR(t1)
  211. /* Clear Power-down registers */
  212. sw zero, MC_SELFRFSH(t1)
  213. /* Set CAS Latency */
  214. li t2, 0x00000020 /* CL = 2 */
  215. sw t2, MC_MRSCODE(t1)
  216. /* Set word width to 16 bit */
  217. li t2, 0x2
  218. sw t2, MC_CFGDW(t1)
  219. /* Set CS0 to SDRAM parameters */
  220. li t2, 0x000014C9
  221. sw t2, MC_CFGPB0(t1)
  222. /* Set SDRAM latency parameters */
  223. li t2, 0x00026325 /* BC PC100 */
  224. sw t2, MC_LATENCY(t1)
  225. 5:
  226. /* Finally enable the controller */
  227. li t2, 0x00000001
  228. sw t2, MC_CTRLENA(t1)
  229. j ra
  230. nop
  231. .end sdram_init
  232. .globl lowlevel_init
  233. .ent lowlevel_init
  234. lowlevel_init:
  235. /* EBU, CGU and SDRAM Initialization.
  236. */
  237. li a0, CPU_CLOCK_RATE
  238. move t0, ra
  239. /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
  240. * modify t0 and a0.
  241. */
  242. bal __cgu_init
  243. nop
  244. bal __ebu_init
  245. nop
  246. bal __sdram_init
  247. nop
  248. move ra, t0
  249. j ra
  250. nop
  251. .end lowlevel_init