flash.c 17 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/inca-ip.h>
  25. flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  26. /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
  27. * has nothing to do with the flash chip being 8-bit or 16-bit.
  28. */
  29. #ifdef CONFIG_FLASH_16BIT
  30. typedef unsigned short FLASH_PORT_WIDTH;
  31. typedef volatile unsigned short FLASH_PORT_WIDTHV;
  32. #define FLASH_ID_MASK 0xFFFF
  33. #else
  34. typedef unsigned long FLASH_PORT_WIDTH;
  35. typedef volatile unsigned long FLASH_PORT_WIDTHV;
  36. #define FLASH_ID_MASK 0xFFFFFFFF
  37. #endif
  38. #define FPW FLASH_PORT_WIDTH
  39. #define FPWV FLASH_PORT_WIDTHV
  40. #define ORMASK(size) ((-size) & OR_AM_MSK)
  41. #if 0
  42. #define FLASH_CYCLE1 0x0555
  43. #define FLASH_CYCLE2 0x02aa
  44. #else
  45. #define FLASH_CYCLE1 0x0554
  46. #define FLASH_CYCLE2 0x02ab
  47. #endif
  48. /*-----------------------------------------------------------------------
  49. * Functions
  50. */
  51. static ulong flash_get_size(FPWV *addr, flash_info_t *info);
  52. static void flash_reset(flash_info_t *info);
  53. static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
  54. static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
  55. static void flash_get_offsets(ulong base, flash_info_t *info);
  56. static flash_info_t *flash_get_info(ulong base);
  57. /*-----------------------------------------------------------------------
  58. * flash_init()
  59. *
  60. * sets up flash_info and returns size of FLASH (bytes)
  61. */
  62. unsigned long flash_init (void)
  63. {
  64. unsigned long size = 0;
  65. int i;
  66. /* Init: no FLASHes known */
  67. for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
  68. ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
  69. ulong * buscon = (ulong *)
  70. ((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2);
  71. /* Disable write protection */
  72. *buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
  73. #if 1
  74. memset(&flash_info[i], 0, sizeof(flash_info_t));
  75. #endif
  76. flash_info[i].size =
  77. flash_get_size((FPW *)flashbase, &flash_info[i]);
  78. if (flash_info[i].flash_id == FLASH_UNKNOWN) {
  79. printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
  80. i, flash_info[i].size);
  81. }
  82. size += flash_info[i].size;
  83. }
  84. #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
  85. /* monitor protection ON by default */
  86. flash_protect(FLAG_PROTECT_SET,
  87. CFG_MONITOR_BASE,
  88. CFG_MONITOR_BASE+monitor_flash_len-1,
  89. flash_get_info(CFG_MONITOR_BASE));
  90. #endif
  91. #ifdef CFG_ENV_IS_IN_FLASH
  92. /* ENV protection ON by default */
  93. flash_protect(FLAG_PROTECT_SET,
  94. CFG_ENV_ADDR,
  95. CFG_ENV_ADDR+CFG_ENV_SIZE-1,
  96. flash_get_info(CFG_ENV_ADDR));
  97. #endif
  98. return size;
  99. }
  100. /*-----------------------------------------------------------------------
  101. */
  102. static void flash_reset(flash_info_t *info)
  103. {
  104. FPWV *base = (FPWV *)(info->start[0]);
  105. /* Put FLASH back in read mode */
  106. if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
  107. *base = (FPW)0x00FF00FF; /* Intel Read Mode */
  108. else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
  109. *base = (FPW)0x00F000F0; /* AMD Read Mode */
  110. }
  111. /*-----------------------------------------------------------------------
  112. */
  113. static void flash_get_offsets (ulong base, flash_info_t *info)
  114. {
  115. int i;
  116. /* set up sector start address table */
  117. if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
  118. && (info->flash_id & FLASH_BTYPE)) {
  119. int bootsect_size; /* number of bytes/boot sector */
  120. int sect_size; /* number of bytes/regular sector */
  121. bootsect_size = 0x00002000 * (sizeof(FPW)/2);
  122. sect_size = 0x00010000 * (sizeof(FPW)/2);
  123. /* set sector offsets for bottom boot block type */
  124. for (i = 0; i < 8; ++i) {
  125. info->start[i] = base + (i * bootsect_size);
  126. }
  127. for (i = 8; i < info->sector_count; i++) {
  128. info->start[i] = base + ((i - 7) * sect_size);
  129. }
  130. }
  131. else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
  132. && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
  133. int sect_size; /* number of bytes/sector */
  134. sect_size = 0x00010000 * (sizeof(FPW)/2);
  135. /* set up sector start address table (uniform sector type) */
  136. for( i = 0; i < info->sector_count; i++ )
  137. info->start[i] = base + (i * sect_size);
  138. }
  139. }
  140. /*-----------------------------------------------------------------------
  141. */
  142. static flash_info_t *flash_get_info(ulong base)
  143. {
  144. int i;
  145. flash_info_t * info;
  146. for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
  147. info = & flash_info[i];
  148. if (info->start[0] <= base && base < info->start[0] + info->size)
  149. break;
  150. }
  151. return i == CFG_MAX_FLASH_BANKS ? 0 : info;
  152. }
  153. /*-----------------------------------------------------------------------
  154. */
  155. void flash_print_info (flash_info_t *info)
  156. {
  157. int i;
  158. uchar *boottype;
  159. uchar *bootletter;
  160. char *fmt;
  161. uchar botbootletter[] = "B";
  162. uchar topbootletter[] = "T";
  163. uchar botboottype[] = "bottom boot sector";
  164. uchar topboottype[] = "top boot sector";
  165. if (info->flash_id == FLASH_UNKNOWN) {
  166. printf ("missing or unknown FLASH type\n");
  167. return;
  168. }
  169. switch (info->flash_id & FLASH_VENDMASK) {
  170. case FLASH_MAN_AMD: printf ("AMD "); break;
  171. case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
  172. case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
  173. case FLASH_MAN_SST: printf ("SST "); break;
  174. case FLASH_MAN_STM: printf ("STM "); break;
  175. case FLASH_MAN_INTEL: printf ("INTEL "); break;
  176. default: printf ("Unknown Vendor "); break;
  177. }
  178. /* check for top or bottom boot, if it applies */
  179. if (info->flash_id & FLASH_BTYPE) {
  180. boottype = botboottype;
  181. bootletter = botbootletter;
  182. }
  183. else {
  184. boottype = topboottype;
  185. bootletter = topbootletter;
  186. }
  187. switch (info->flash_id & FLASH_TYPEMASK) {
  188. case FLASH_AM640U:
  189. fmt = "29LV641D (64 Mbit, uniform sectors)\n";
  190. break;
  191. case FLASH_28F800C3B:
  192. case FLASH_28F800C3T:
  193. fmt = "28F800C3%s (8 Mbit, %s)\n";
  194. break;
  195. case FLASH_INTEL800B:
  196. case FLASH_INTEL800T:
  197. fmt = "28F800B3%s (8 Mbit, %s)\n";
  198. break;
  199. case FLASH_28F160C3B:
  200. case FLASH_28F160C3T:
  201. fmt = "28F160C3%s (16 Mbit, %s)\n";
  202. break;
  203. case FLASH_INTEL160B:
  204. case FLASH_INTEL160T:
  205. fmt = "28F160B3%s (16 Mbit, %s)\n";
  206. break;
  207. case FLASH_28F320C3B:
  208. case FLASH_28F320C3T:
  209. fmt = "28F320C3%s (32 Mbit, %s)\n";
  210. break;
  211. case FLASH_INTEL320B:
  212. case FLASH_INTEL320T:
  213. fmt = "28F320B3%s (32 Mbit, %s)\n";
  214. break;
  215. case FLASH_28F640C3B:
  216. case FLASH_28F640C3T:
  217. fmt = "28F640C3%s (64 Mbit, %s)\n";
  218. break;
  219. case FLASH_INTEL640B:
  220. case FLASH_INTEL640T:
  221. fmt = "28F640B3%s (64 Mbit, %s)\n";
  222. break;
  223. default:
  224. fmt = "Unknown Chip Type\n";
  225. break;
  226. }
  227. printf (fmt, bootletter, boottype);
  228. printf (" Size: %ld MB in %d Sectors\n",
  229. info->size >> 20,
  230. info->sector_count);
  231. printf (" Sector Start Addresses:");
  232. for (i=0; i<info->sector_count; ++i) {
  233. if ((i % 5) == 0) {
  234. printf ("\n ");
  235. }
  236. printf (" %08lX%s", info->start[i],
  237. info->protect[i] ? " (RO)" : " ");
  238. }
  239. printf ("\n");
  240. }
  241. /*-----------------------------------------------------------------------
  242. */
  243. /*
  244. * The following code cannot be run from FLASH!
  245. */
  246. ulong flash_get_size (FPWV *addr, flash_info_t *info)
  247. {
  248. /* Write auto select command: read Manufacturer ID */
  249. /* Write auto select command sequence and test FLASH answer */
  250. addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
  251. addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
  252. addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
  253. /* The manufacturer codes are only 1 byte, so just use 1 byte.
  254. * This works for any bus width and any FLASH device width.
  255. */
  256. switch (addr[1] & 0xff) {
  257. case (uchar)AMD_MANUFACT:
  258. info->flash_id = FLASH_MAN_AMD;
  259. break;
  260. case (uchar)INTEL_MANUFACT:
  261. info->flash_id = FLASH_MAN_INTEL;
  262. break;
  263. default:
  264. info->flash_id = FLASH_UNKNOWN;
  265. info->sector_count = 0;
  266. info->size = 0;
  267. break;
  268. }
  269. /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
  270. if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) {
  271. case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
  272. info->flash_id += FLASH_AM640U;
  273. info->sector_count = 128;
  274. info->size = 0x00800000 * (sizeof(FPW)/2);
  275. break; /* => 8 or 16 MB */
  276. case (FPW)INTEL_ID_28F800C3B:
  277. info->flash_id += FLASH_28F800C3B;
  278. info->sector_count = 23;
  279. info->size = 0x00100000 * (sizeof(FPW)/2);
  280. break; /* => 1 or 2 MB */
  281. case (FPW)INTEL_ID_28F800B3B:
  282. info->flash_id += FLASH_INTEL800B;
  283. info->sector_count = 23;
  284. info->size = 0x00100000 * (sizeof(FPW)/2);
  285. break; /* => 1 or 2 MB */
  286. case (FPW)INTEL_ID_28F160C3B:
  287. info->flash_id += FLASH_28F160C3B;
  288. info->sector_count = 39;
  289. info->size = 0x00200000 * (sizeof(FPW)/2);
  290. break; /* => 2 or 4 MB */
  291. case (FPW)INTEL_ID_28F160B3B:
  292. info->flash_id += FLASH_INTEL160B;
  293. info->sector_count = 39;
  294. info->size = 0x00200000 * (sizeof(FPW)/2);
  295. break; /* => 2 or 4 MB */
  296. case (FPW)INTEL_ID_28F320C3B:
  297. info->flash_id += FLASH_28F320C3B;
  298. info->sector_count = 71;
  299. info->size = 0x00400000 * (sizeof(FPW)/2);
  300. break; /* => 4 or 8 MB */
  301. case (FPW)INTEL_ID_28F320B3B:
  302. info->flash_id += FLASH_INTEL320B;
  303. info->sector_count = 71;
  304. info->size = 0x00400000 * (sizeof(FPW)/2);
  305. break; /* => 4 or 8 MB */
  306. case (FPW)INTEL_ID_28F640C3B:
  307. info->flash_id += FLASH_28F640C3B;
  308. info->sector_count = 135;
  309. info->size = 0x00800000 * (sizeof(FPW)/2);
  310. break; /* => 8 or 16 MB */
  311. case (FPW)INTEL_ID_28F640B3B:
  312. info->flash_id += FLASH_INTEL640B;
  313. info->sector_count = 135;
  314. info->size = 0x00800000 * (sizeof(FPW)/2);
  315. break; /* => 8 or 16 MB */
  316. default:
  317. info->flash_id = FLASH_UNKNOWN;
  318. info->sector_count = 0;
  319. info->size = 0;
  320. return (0); /* => no or unknown flash */
  321. }
  322. flash_get_offsets((ulong)addr, info);
  323. /* Put FLASH back in read mode */
  324. flash_reset(info);
  325. return (info->size);
  326. }
  327. /*-----------------------------------------------------------------------
  328. */
  329. int flash_erase (flash_info_t *info, int s_first, int s_last)
  330. {
  331. FPWV *addr;
  332. int flag, prot, sect;
  333. int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
  334. ulong start, now, last;
  335. int rcode = 0;
  336. if ((s_first < 0) || (s_first > s_last)) {
  337. if (info->flash_id == FLASH_UNKNOWN) {
  338. printf ("- missing\n");
  339. } else {
  340. printf ("- no sectors to erase\n");
  341. }
  342. return 1;
  343. }
  344. switch (info->flash_id & FLASH_TYPEMASK) {
  345. case FLASH_INTEL800B:
  346. case FLASH_INTEL160B:
  347. case FLASH_INTEL320B:
  348. case FLASH_INTEL640B:
  349. case FLASH_28F800C3B:
  350. case FLASH_28F160C3B:
  351. case FLASH_28F320C3B:
  352. case FLASH_28F640C3B:
  353. case FLASH_AM640U:
  354. break;
  355. case FLASH_UNKNOWN:
  356. default:
  357. printf ("Can't erase unknown flash type %08lx - aborted\n",
  358. info->flash_id);
  359. return 1;
  360. }
  361. prot = 0;
  362. for (sect=s_first; sect<=s_last; ++sect) {
  363. if (info->protect[sect]) {
  364. prot++;
  365. }
  366. }
  367. if (prot) {
  368. printf ("- Warning: %d protected sectors will not be erased!\n",
  369. prot);
  370. } else {
  371. printf ("\n");
  372. }
  373. last = get_timer(0);
  374. /* Start erase on unprotected sectors */
  375. for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
  376. if (info->protect[sect] != 0) /* protected, skip it */
  377. continue;
  378. /* Disable interrupts which might cause a timeout here */
  379. flag = disable_interrupts();
  380. addr = (FPWV *)(info->start[sect]);
  381. if (intel) {
  382. *addr = (FPW)0x00500050; /* clear status register */
  383. *addr = (FPW)0x00200020; /* erase setup */
  384. *addr = (FPW)0x00D000D0; /* erase confirm */
  385. }
  386. else {
  387. /* must be AMD style if not Intel */
  388. FPWV *base; /* first address in bank */
  389. base = (FPWV *)(info->start[0]);
  390. base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
  391. base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
  392. base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
  393. base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
  394. base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
  395. *addr = (FPW)0x00300030; /* erase sector */
  396. }
  397. /* re-enable interrupts if necessary */
  398. if (flag)
  399. enable_interrupts();
  400. start = get_timer(0);
  401. /* wait at least 50us for AMD, 80us for Intel.
  402. * Let's wait 1 ms.
  403. */
  404. udelay (1000);
  405. while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
  406. if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
  407. printf ("Timeout\n");
  408. if (intel) {
  409. /* suspend erase */
  410. *addr = (FPW)0x00B000B0;
  411. }
  412. flash_reset(info); /* reset to read mode */
  413. rcode = 1; /* failed */
  414. break;
  415. }
  416. /* show that we're waiting */
  417. if ((get_timer(last)) > CFG_HZ) {/* every second */
  418. putc ('.');
  419. last = get_timer(0);
  420. }
  421. }
  422. /* show that we're waiting */
  423. if ((get_timer(last)) > CFG_HZ) { /* every second */
  424. putc ('.');
  425. last = get_timer(0);
  426. }
  427. flash_reset(info); /* reset to read mode */
  428. }
  429. printf (" done\n");
  430. return rcode;
  431. }
  432. /*-----------------------------------------------------------------------
  433. * Copy memory to flash, returns:
  434. * 0 - OK
  435. * 1 - write timeout
  436. * 2 - Flash not erased
  437. */
  438. int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  439. {
  440. FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
  441. int bytes; /* number of bytes to program in current word */
  442. int left; /* number of bytes left to program */
  443. int i, res;
  444. for (left = cnt, res = 0;
  445. left > 0 && res == 0;
  446. addr += sizeof(data), left -= sizeof(data) - bytes) {
  447. bytes = addr & (sizeof(data) - 1);
  448. addr &= ~(sizeof(data) - 1);
  449. /* combine source and destination data so can program
  450. * an entire word of 16 or 32 bits
  451. */
  452. for (i = 0; i < sizeof(data); i++) {
  453. data <<= 8;
  454. if (i < bytes || i - bytes >= left )
  455. data += *((uchar *)addr + i);
  456. else
  457. data += *src++;
  458. }
  459. /* write one word to the flash */
  460. switch (info->flash_id & FLASH_VENDMASK) {
  461. case FLASH_MAN_AMD:
  462. res = write_word_amd(info, (FPWV *)addr, data);
  463. break;
  464. case FLASH_MAN_INTEL:
  465. res = write_word_intel(info, (FPWV *)addr, data);
  466. break;
  467. default:
  468. /* unknown flash type, error! */
  469. printf ("missing or unknown FLASH type\n");
  470. res = 1; /* not really a timeout, but gives error */
  471. break;
  472. }
  473. }
  474. return (res);
  475. }
  476. /*-----------------------------------------------------------------------
  477. * Write a word to Flash for AMD FLASH
  478. * A word is 16 or 32 bits, whichever the bus width of the flash bank
  479. * (not an individual chip) is.
  480. *
  481. * returns:
  482. * 0 - OK
  483. * 1 - write timeout
  484. * 2 - Flash not erased
  485. */
  486. static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
  487. {
  488. ulong start;
  489. int flag;
  490. int res = 0; /* result, assume success */
  491. FPWV *base; /* first address in flash bank */
  492. /* Check if Flash is (sufficiently) erased */
  493. if ((*dest & data) != data) {
  494. return (2);
  495. }
  496. base = (FPWV *)(info->start[0]);
  497. /* Disable interrupts which might cause a timeout here */
  498. flag = disable_interrupts();
  499. base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
  500. base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
  501. base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
  502. *dest = data; /* start programming the data */
  503. /* re-enable interrupts if necessary */
  504. if (flag)
  505. enable_interrupts();
  506. start = get_timer (0);
  507. /* data polling for D7 */
  508. while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
  509. if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
  510. *dest = (FPW)0x00F000F0; /* reset bank */
  511. res = 1;
  512. }
  513. }
  514. return (res);
  515. }
  516. /*-----------------------------------------------------------------------
  517. * Write a word to Flash for Intel FLASH
  518. * A word is 16 or 32 bits, whichever the bus width of the flash bank
  519. * (not an individual chip) is.
  520. *
  521. * returns:
  522. * 0 - OK
  523. * 1 - write timeout
  524. * 2 - Flash not erased
  525. */
  526. static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
  527. {
  528. ulong start;
  529. int flag;
  530. int res = 0; /* result, assume success */
  531. /* Check if Flash is (sufficiently) erased */
  532. if ((*dest & data) != data) {
  533. return (2);
  534. }
  535. /* Disable interrupts which might cause a timeout here */
  536. flag = disable_interrupts();
  537. *dest = (FPW)0x00500050; /* clear status register */
  538. *dest = (FPW)0x00FF00FF; /* make sure in read mode */
  539. *dest = (FPW)0x00400040; /* program setup */
  540. *dest = data; /* start programming the data */
  541. /* re-enable interrupts if necessary */
  542. if (flag)
  543. enable_interrupts();
  544. start = get_timer (0);
  545. while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
  546. if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
  547. *dest = (FPW)0x00B000B0; /* Suspend program */
  548. res = 1;
  549. }
  550. }
  551. if (res == 0 && (*dest & (FPW)0x00100010))
  552. res = 1; /* write failed, time out error is close enough */
  553. *dest = (FPW)0x00500050; /* clear status register */
  554. *dest = (FPW)0x00FF00FF; /* make sure in read mode */
  555. return (res);
  556. }