mv_eth.c 104 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184
  1. /*
  2. * (C) Copyright 2003
  3. * Ingo Assmus <ingo.assmus@keymile.com>
  4. *
  5. * based on - Driver for MV64360X ethernet ports
  6. * Copyright (C) 2002 rabeeh@galileo.co.il
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * mv_eth.c - header file for the polled mode GT ethernet driver
  28. */
  29. #include <common.h>
  30. #include <net.h>
  31. #include <malloc.h>
  32. #include "mv_eth.h"
  33. /* enable Debug outputs */
  34. #undef DEBUG_MV_ETH
  35. #ifdef DEBUG_MV_ETH
  36. #define DEBUG
  37. #define DP(x) x
  38. #else
  39. #define DP(x)
  40. #endif
  41. #undef MV64360_CHECKSUM_OFFLOAD
  42. /*************************************************************************
  43. **************************************************************************
  44. **************************************************************************
  45. * The first part is the high level driver of the gigE ethernet ports. *
  46. **************************************************************************
  47. **************************************************************************
  48. *************************************************************************/
  49. /* Definition for configuring driver */
  50. /* #define UPDATE_STATS_BY_SOFTWARE */
  51. #undef MV64360_RX_QUEUE_FILL_ON_TASK
  52. /* Constants */
  53. #define MAGIC_ETH_RUNNING 8031971
  54. #define MV64360_INTERNAL_SRAM_SIZE _256K
  55. #define EXTRA_BYTES 32
  56. #define WRAP ETH_HLEN + 2 + 4 + 16
  57. #define BUFFER_MTU dev->mtu + WRAP
  58. #define INT_CAUSE_UNMASK_ALL 0x0007ffff
  59. #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
  60. #ifdef MV64360_RX_FILL_ON_TASK
  61. #define INT_CAUSE_MASK_ALL 0x00000000
  62. #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
  63. #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
  64. #endif
  65. /* Read/Write to/from MV64360 internal registers */
  66. #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
  67. #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
  68. #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
  69. #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
  70. /* Static function declarations */
  71. static int mv64360_eth_real_open (struct eth_device *eth);
  72. static int mv64360_eth_real_stop (struct eth_device *eth);
  73. static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
  74. *dev);
  75. static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
  76. static void mv64360_eth_update_stat (struct eth_device *dev);
  77. bool db64360_eth_start (struct eth_device *eth);
  78. unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
  79. unsigned int mib_offset);
  80. int mv64360_eth_receive (struct eth_device *dev);
  81. int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
  82. #ifndef UPDATE_STATS_BY_SOFTWARE
  83. static void mv64360_eth_print_stat (struct eth_device *dev);
  84. #endif
  85. /* Processes a received packet */
  86. extern void NetReceive (volatile uchar *, int);
  87. extern unsigned int INTERNAL_REG_BASE_ADDR;
  88. /*************************************************
  89. *Helper functions - used inside the driver only *
  90. *************************************************/
  91. #ifdef DEBUG_MV_ETH
  92. void print_globals (struct eth_device *dev)
  93. {
  94. printf ("Ethernet PRINT_Globals-Debug function\n");
  95. printf ("Base Address for ETH_PORT_INFO: %08x\n",
  96. (unsigned int) dev->priv);
  97. printf ("Base Address for mv64360_eth_priv: %08x\n",
  98. (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
  99. port_private));
  100. printf ("GT Internal Base Address: %08x\n",
  101. INTERNAL_REG_BASE_ADDR);
  102. printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
  103. printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
  104. printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
  105. (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
  106. p_rx_buffer_base[0],
  107. (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
  108. printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
  109. (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
  110. p_tx_buffer_base[0],
  111. (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
  112. }
  113. #endif
  114. #define my_cpu_to_le32(x) my_le32_to_cpu((x))
  115. unsigned long my_le32_to_cpu (unsigned long x)
  116. {
  117. return (((x & 0x000000ffU) << 24) |
  118. ((x & 0x0000ff00U) << 8) |
  119. ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
  120. }
  121. /**********************************************************************
  122. * mv64360_eth_print_phy_status
  123. *
  124. * Prints gigabit ethenret phy status
  125. *
  126. * Input : pointer to ethernet interface network device structure
  127. * Output : N/A
  128. **********************************************************************/
  129. static void mv64360_eth_print_phy_status (struct eth_device *dev)
  130. {
  131. struct mv64360_eth_priv *port_private;
  132. unsigned int port_num;
  133. ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
  134. unsigned int port_status, phy_reg_data;
  135. port_private =
  136. (struct mv64360_eth_priv *) ethernet_private->port_private;
  137. port_num = port_private->port_num;
  138. /* Check Link status on phy */
  139. eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
  140. if (!(phy_reg_data & 0x20)) {
  141. printf ("Ethernet port changed link status to DOWN\n");
  142. } else {
  143. port_status =
  144. MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
  145. printf ("Ethernet status port %d: Link up", port_num);
  146. printf (", %s",
  147. (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
  148. if (port_status & BIT4)
  149. printf (", Speed 1 Gbps");
  150. else
  151. printf (", %s",
  152. (port_status & BIT5) ? "Speed 100 Mbps" :
  153. "Speed 10 Mbps");
  154. printf ("\n");
  155. }
  156. }
  157. /**********************************************************************
  158. * u-boot entry functions for mv64360_eth
  159. *
  160. **********************************************************************/
  161. int db64360_eth_probe (struct eth_device *dev)
  162. {
  163. return ((int) db64360_eth_start (dev));
  164. }
  165. int db64360_eth_poll (struct eth_device *dev)
  166. {
  167. return mv64360_eth_receive (dev);
  168. }
  169. int db64360_eth_transmit (struct eth_device *dev, volatile void *packet,
  170. int length)
  171. {
  172. mv64360_eth_xmit (dev, packet, length);
  173. return 0;
  174. }
  175. void db64360_eth_disable (struct eth_device *dev)
  176. {
  177. mv64360_eth_stop (dev);
  178. }
  179. void mv6436x_eth_initialize (bd_t * bis)
  180. {
  181. struct eth_device *dev;
  182. ETH_PORT_INFO *ethernet_private;
  183. struct mv64360_eth_priv *port_private;
  184. int devnum, x, temp;
  185. char *s, *e, buf[64];
  186. for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
  187. dev = calloc (sizeof (*dev), 1);
  188. if (!dev) {
  189. printf ("%s: mv_enet%d allocation failure, %s\n",
  190. __FUNCTION__, devnum, "eth_device structure");
  191. return;
  192. }
  193. /* must be less than NAMESIZE (16) */
  194. sprintf (dev->name, "mv_enet%d", devnum);
  195. #ifdef DEBUG
  196. printf ("Initializing %s\n", dev->name);
  197. #endif
  198. /* Extract the MAC address from the environment */
  199. switch (devnum) {
  200. case 0:
  201. s = "ethaddr";
  202. break;
  203. case 1:
  204. s = "eth1addr";
  205. break;
  206. case 2:
  207. s = "eth2addr";
  208. break;
  209. default: /* this should never happen */
  210. printf ("%s: Invalid device number %d\n",
  211. __FUNCTION__, devnum);
  212. return;
  213. }
  214. temp = getenv_r (s, buf, sizeof (buf));
  215. s = (temp > 0) ? buf : NULL;
  216. #ifdef DEBUG
  217. printf ("Setting MAC %d to %s\n", devnum, s);
  218. #endif
  219. for (x = 0; x < 6; ++x) {
  220. dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
  221. if (s)
  222. s = (*e) ? e + 1 : e;
  223. }
  224. /* ronen - set the MAC addr in the HW */
  225. eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
  226. dev->init = (void *) db64360_eth_probe;
  227. dev->halt = (void *) ethernet_phy_reset;
  228. dev->send = (void *) db64360_eth_transmit;
  229. dev->recv = (void *) db64360_eth_poll;
  230. ethernet_private =
  231. calloc (sizeof (*ethernet_private), 1);
  232. dev->priv = (void *) ethernet_private;
  233. if (!ethernet_private) {
  234. printf ("%s: %s allocation failure, %s\n",
  235. __FUNCTION__, dev->name,
  236. "Private Device Structure");
  237. free (dev);
  238. return;
  239. }
  240. /* start with an zeroed ETH_PORT_INFO */
  241. memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
  242. memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
  243. /* set pointer to memory for stats data structure etc... */
  244. port_private =
  245. calloc (sizeof (*ethernet_private), 1);
  246. ethernet_private->port_private = (void *)port_private;
  247. if (!port_private) {
  248. printf ("%s: %s allocation failure, %s\n",
  249. __FUNCTION__, dev->name,
  250. "Port Private Device Structure");
  251. free (ethernet_private);
  252. free (dev);
  253. return;
  254. }
  255. port_private->stats =
  256. calloc (sizeof (struct net_device_stats), 1);
  257. if (!port_private->stats) {
  258. printf ("%s: %s allocation failure, %s\n",
  259. __FUNCTION__, dev->name,
  260. "Net stat Structure");
  261. free (port_private);
  262. free (ethernet_private);
  263. free (dev);
  264. return;
  265. }
  266. memset (ethernet_private->port_private, 0,
  267. sizeof (struct mv64360_eth_priv));
  268. switch (devnum) {
  269. case 0:
  270. ethernet_private->port_num = ETH_0;
  271. break;
  272. case 1:
  273. ethernet_private->port_num = ETH_1;
  274. break;
  275. case 2:
  276. ethernet_private->port_num = ETH_2;
  277. break;
  278. default:
  279. printf ("Invalid device number %d\n", devnum);
  280. break;
  281. };
  282. port_private->port_num = devnum;
  283. /*
  284. * Read MIB counter on the GT in order to reset them,
  285. * then zero all the stats fields in memory
  286. */
  287. mv64360_eth_update_stat (dev);
  288. memset (port_private->stats, 0,
  289. sizeof (struct net_device_stats));
  290. /* Extract the MAC address from the environment */
  291. switch (devnum) {
  292. case 0:
  293. s = "ethaddr";
  294. break;
  295. case 1:
  296. s = "eth1addr";
  297. break;
  298. case 2:
  299. s = "eth2addr";
  300. break;
  301. default: /* this should never happen */
  302. printf ("%s: Invalid device number %d\n",
  303. __FUNCTION__, devnum);
  304. return;
  305. }
  306. temp = getenv_r (s, buf, sizeof (buf));
  307. s = (temp > 0) ? buf : NULL;
  308. #ifdef DEBUG
  309. printf ("Setting MAC %d to %s\n", devnum, s);
  310. #endif
  311. for (x = 0; x < 6; ++x) {
  312. dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
  313. if (s)
  314. s = (*e) ? e + 1 : e;
  315. }
  316. DP (printf ("Allocating descriptor and buffer rings\n"));
  317. ethernet_private->p_rx_desc_area_base[0] =
  318. (ETH_RX_DESC *) memalign (16,
  319. RX_DESC_ALIGNED_SIZE *
  320. MV64360_RX_QUEUE_SIZE + 1);
  321. ethernet_private->p_tx_desc_area_base[0] =
  322. (ETH_TX_DESC *) memalign (16,
  323. TX_DESC_ALIGNED_SIZE *
  324. MV64360_TX_QUEUE_SIZE + 1);
  325. ethernet_private->p_rx_buffer_base[0] =
  326. (char *) memalign (16,
  327. MV64360_RX_QUEUE_SIZE *
  328. MV64360_TX_BUFFER_SIZE + 1);
  329. ethernet_private->p_tx_buffer_base[0] =
  330. (char *) memalign (16,
  331. MV64360_RX_QUEUE_SIZE *
  332. MV64360_TX_BUFFER_SIZE + 1);
  333. #ifdef DEBUG_MV_ETH
  334. /* DEBUG OUTPUT prints adresses of globals */
  335. print_globals (dev);
  336. #endif
  337. eth_register (dev);
  338. }
  339. DP (printf ("%s: exit\n", __FUNCTION__));
  340. }
  341. /**********************************************************************
  342. * mv64360_eth_open
  343. *
  344. * This function is called when openning the network device. The function
  345. * should initialize all the hardware, initialize cyclic Rx/Tx
  346. * descriptors chain and buffers and allocate an IRQ to the network
  347. * device.
  348. *
  349. * Input : a pointer to the network device structure
  350. * / / ronen - changed the output to match net/eth.c needs
  351. * Output : nonzero of success , zero if fails.
  352. * under construction
  353. **********************************************************************/
  354. int mv64360_eth_open (struct eth_device *dev)
  355. {
  356. return (mv64360_eth_real_open (dev));
  357. }
  358. /* Helper function for mv64360_eth_open */
  359. static int mv64360_eth_real_open (struct eth_device *dev)
  360. {
  361. unsigned int queue;
  362. ETH_PORT_INFO *ethernet_private;
  363. struct mv64360_eth_priv *port_private;
  364. unsigned int port_num;
  365. u32 port_status, phy_reg_data;
  366. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  367. /* ronen - when we update the MAC env params we only update dev->enetaddr
  368. see ./net/eth.c eth_set_enetaddr() */
  369. memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
  370. port_private =
  371. (struct mv64360_eth_priv *) ethernet_private->port_private;
  372. port_num = port_private->port_num;
  373. /* Stop RX Queues */
  374. MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
  375. 0x0000ff00);
  376. /* Clear the ethernet port interrupts */
  377. MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
  378. MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
  379. /* Unmask RX buffer and TX end interrupt */
  380. MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
  381. INT_CAUSE_UNMASK_ALL);
  382. /* Unmask phy and link status changes interrupts */
  383. MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
  384. INT_CAUSE_UNMASK_ALL_EXT);
  385. /* Set phy address of the port */
  386. ethernet_private->port_phy_addr = 0x8 + port_num;
  387. /* Activate the DMA channels etc */
  388. eth_port_init (ethernet_private);
  389. /* "Allocate" setup TX rings */
  390. for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
  391. unsigned int size;
  392. port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
  393. size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
  394. ethernet_private->tx_desc_area_size[queue] = size;
  395. /* first clear desc area completely */
  396. memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
  397. 0, ethernet_private->tx_desc_area_size[queue]);
  398. /* initialize tx desc ring with low level driver */
  399. if (ether_init_tx_desc_ring
  400. (ethernet_private, ETH_Q0,
  401. port_private->tx_ring_size[queue],
  402. MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
  403. (unsigned int) ethernet_private->
  404. p_tx_desc_area_base[queue],
  405. (unsigned int) ethernet_private->
  406. p_tx_buffer_base[queue]) == false)
  407. printf ("### Error initializing TX Ring\n");
  408. }
  409. /* "Allocate" setup RX rings */
  410. for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
  411. unsigned int size;
  412. /* Meantime RX Ring are fixed - but must be configurable by user */
  413. port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
  414. size = (port_private->rx_ring_size[queue] *
  415. RX_DESC_ALIGNED_SIZE);
  416. ethernet_private->rx_desc_area_size[queue] = size;
  417. /* first clear desc area completely */
  418. memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
  419. 0, ethernet_private->rx_desc_area_size[queue]);
  420. if ((ether_init_rx_desc_ring
  421. (ethernet_private, ETH_Q0,
  422. port_private->rx_ring_size[queue],
  423. MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
  424. (unsigned int) ethernet_private->
  425. p_rx_desc_area_base[queue],
  426. (unsigned int) ethernet_private->
  427. p_rx_buffer_base[queue])) == false)
  428. printf ("### Error initializing RX Ring\n");
  429. }
  430. eth_port_start (ethernet_private);
  431. /* Set maximum receive buffer to 9700 bytes */
  432. MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
  433. (0x5 << 17) |
  434. (MV_REG_READ
  435. (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
  436. & 0xfff1ffff));
  437. /*
  438. * Set ethernet MTU for leaky bucket mechanism to 0 - this will
  439. * disable the leaky bucket mechanism .
  440. */
  441. MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
  442. port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
  443. /* Check Link status on phy */
  444. eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
  445. if (!(phy_reg_data & 0x20)) {
  446. /* Reset PHY */
  447. if ((ethernet_phy_reset (port_num)) != true) {
  448. printf ("$$ Warnning: No link on port %d \n",
  449. port_num);
  450. return 0;
  451. } else {
  452. eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
  453. if (!(phy_reg_data & 0x20)) {
  454. printf ("### Error: Phy is not active\n");
  455. return 0;
  456. }
  457. }
  458. } else {
  459. mv64360_eth_print_phy_status (dev);
  460. }
  461. port_private->eth_running = MAGIC_ETH_RUNNING;
  462. return 1;
  463. }
  464. static int mv64360_eth_free_tx_rings (struct eth_device *dev)
  465. {
  466. unsigned int queue;
  467. ETH_PORT_INFO *ethernet_private;
  468. struct mv64360_eth_priv *port_private;
  469. unsigned int port_num;
  470. volatile ETH_TX_DESC *p_tx_curr_desc;
  471. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  472. port_private =
  473. (struct mv64360_eth_priv *) ethernet_private->port_private;
  474. port_num = port_private->port_num;
  475. /* Stop Tx Queues */
  476. MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
  477. 0x0000ff00);
  478. /* Free TX rings */
  479. DP (printf ("Clearing previously allocated TX queues... "));
  480. for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
  481. /* Free on TX rings */
  482. for (p_tx_curr_desc =
  483. ethernet_private->p_tx_desc_area_base[queue];
  484. ((unsigned int) p_tx_curr_desc <= (unsigned int)
  485. ethernet_private->p_tx_desc_area_base[queue] +
  486. ethernet_private->tx_desc_area_size[queue]);
  487. p_tx_curr_desc =
  488. (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
  489. TX_DESC_ALIGNED_SIZE)) {
  490. /* this is inside for loop */
  491. if (p_tx_curr_desc->return_info != 0) {
  492. p_tx_curr_desc->return_info = 0;
  493. DP (printf ("freed\n"));
  494. }
  495. }
  496. DP (printf ("Done\n"));
  497. }
  498. return 0;
  499. }
  500. static int mv64360_eth_free_rx_rings (struct eth_device *dev)
  501. {
  502. unsigned int queue;
  503. ETH_PORT_INFO *ethernet_private;
  504. struct mv64360_eth_priv *port_private;
  505. unsigned int port_num;
  506. volatile ETH_RX_DESC *p_rx_curr_desc;
  507. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  508. port_private =
  509. (struct mv64360_eth_priv *) ethernet_private->port_private;
  510. port_num = port_private->port_num;
  511. /* Stop RX Queues */
  512. MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
  513. 0x0000ff00);
  514. /* Free RX rings */
  515. DP (printf ("Clearing previously allocated RX queues... "));
  516. for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
  517. /* Free preallocated skb's on RX rings */
  518. for (p_rx_curr_desc =
  519. ethernet_private->p_rx_desc_area_base[queue];
  520. (((unsigned int) p_rx_curr_desc <
  521. ((unsigned int) ethernet_private->
  522. p_rx_desc_area_base[queue] +
  523. ethernet_private->rx_desc_area_size[queue])));
  524. p_rx_curr_desc =
  525. (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
  526. RX_DESC_ALIGNED_SIZE)) {
  527. if (p_rx_curr_desc->return_info != 0) {
  528. p_rx_curr_desc->return_info = 0;
  529. DP (printf ("freed\n"));
  530. }
  531. }
  532. DP (printf ("Done\n"));
  533. }
  534. return 0;
  535. }
  536. /**********************************************************************
  537. * mv64360_eth_stop
  538. *
  539. * This function is used when closing the network device.
  540. * It updates the hardware,
  541. * release all memory that holds buffers and descriptors and release the IRQ.
  542. * Input : a pointer to the device structure
  543. * Output : zero if success , nonzero if fails
  544. *********************************************************************/
  545. int mv64360_eth_stop (struct eth_device *dev)
  546. {
  547. ETH_PORT_INFO *ethernet_private;
  548. struct mv64360_eth_priv *port_private;
  549. unsigned int port_num;
  550. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  551. port_private =
  552. (struct mv64360_eth_priv *) ethernet_private->port_private;
  553. port_num = port_private->port_num;
  554. /* Disable all gigE address decoder */
  555. MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
  556. DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
  557. mv64360_eth_real_stop (dev);
  558. return 0;
  559. };
  560. /* Helper function for mv64360_eth_stop */
  561. static int mv64360_eth_real_stop (struct eth_device *dev)
  562. {
  563. ETH_PORT_INFO *ethernet_private;
  564. struct mv64360_eth_priv *port_private;
  565. unsigned int port_num;
  566. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  567. port_private =
  568. (struct mv64360_eth_priv *) ethernet_private->port_private;
  569. port_num = port_private->port_num;
  570. mv64360_eth_free_tx_rings (dev);
  571. mv64360_eth_free_rx_rings (dev);
  572. eth_port_reset (ethernet_private->port_num);
  573. /* Disable ethernet port interrupts */
  574. MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
  575. MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
  576. /* Mask RX buffer and TX end interrupt */
  577. MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
  578. /* Mask phy and link status changes interrupts */
  579. MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
  580. MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
  581. BIT0 << port_num);
  582. /* Print Network statistics */
  583. #ifndef UPDATE_STATS_BY_SOFTWARE
  584. /*
  585. * Print statistics (only if ethernet is running),
  586. * then zero all the stats fields in memory
  587. */
  588. if (port_private->eth_running == MAGIC_ETH_RUNNING) {
  589. port_private->eth_running = 0;
  590. mv64360_eth_print_stat (dev);
  591. }
  592. memset (port_private->stats, 0, sizeof (struct net_device_stats));
  593. #endif
  594. DP (printf ("\nEthernet stopped ... \n"));
  595. return 0;
  596. }
  597. /**********************************************************************
  598. * mv64360_eth_start_xmit
  599. *
  600. * This function is queues a packet in the Tx descriptor for
  601. * required port.
  602. *
  603. * Input : skb - a pointer to socket buffer
  604. * dev - a pointer to the required port
  605. *
  606. * Output : zero upon success
  607. **********************************************************************/
  608. int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
  609. int dataSize)
  610. {
  611. ETH_PORT_INFO *ethernet_private;
  612. struct mv64360_eth_priv *port_private;
  613. unsigned int port_num;
  614. PKT_INFO pkt_info;
  615. ETH_FUNC_RET_STATUS status;
  616. struct net_device_stats *stats;
  617. ETH_FUNC_RET_STATUS release_result;
  618. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  619. port_private =
  620. (struct mv64360_eth_priv *) ethernet_private->port_private;
  621. port_num = port_private->port_num;
  622. stats = port_private->stats;
  623. /* Update packet info data structure */
  624. pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
  625. pkt_info.byte_cnt = dataSize;
  626. pkt_info.buf_ptr = (unsigned int) dataPtr;
  627. status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
  628. if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
  629. printf ("Error on transmitting packet ..");
  630. if (status == ETH_QUEUE_FULL)
  631. printf ("ETH Queue is full. \n");
  632. if (status == ETH_QUEUE_LAST_RESOURCE)
  633. printf ("ETH Queue: using last available resource. \n");
  634. goto error;
  635. }
  636. /* Update statistics and start of transmittion time */
  637. stats->tx_bytes += dataSize;
  638. stats->tx_packets++;
  639. /* Check if packet(s) is(are) transmitted correctly (release everything) */
  640. do {
  641. release_result =
  642. eth_tx_return_desc (ethernet_private, ETH_Q0,
  643. &pkt_info);
  644. switch (release_result) {
  645. case ETH_OK:
  646. DP (printf ("descriptor released\n"));
  647. if (pkt_info.cmd_sts & BIT0) {
  648. printf ("Error in TX\n");
  649. stats->tx_errors++;
  650. }
  651. break;
  652. case ETH_RETRY:
  653. DP (printf ("transmission still in process\n"));
  654. break;
  655. case ETH_ERROR:
  656. printf ("routine can not access Tx desc ring\n");
  657. break;
  658. case ETH_END_OF_JOB:
  659. DP (printf ("the routine has nothing to release\n"));
  660. break;
  661. default: /* should not happen */
  662. break;
  663. }
  664. } while (release_result == ETH_OK);
  665. return 0; /* success */
  666. error:
  667. return 1; /* Failed - higher layers will free the skb */
  668. }
  669. /**********************************************************************
  670. * mv64360_eth_receive
  671. *
  672. * This function is forward packets that are received from the port's
  673. * queues toward kernel core or FastRoute them to another interface.
  674. *
  675. * Input : dev - a pointer to the required interface
  676. * max - maximum number to receive (0 means unlimted)
  677. *
  678. * Output : number of served packets
  679. **********************************************************************/
  680. int mv64360_eth_receive (struct eth_device *dev)
  681. {
  682. ETH_PORT_INFO *ethernet_private;
  683. struct mv64360_eth_priv *port_private;
  684. unsigned int port_num;
  685. PKT_INFO pkt_info;
  686. struct net_device_stats *stats;
  687. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  688. port_private =
  689. (struct mv64360_eth_priv *) ethernet_private->port_private;
  690. port_num = port_private->port_num;
  691. stats = port_private->stats;
  692. while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
  693. ETH_OK)) {
  694. #ifdef DEBUG_MV_ETH
  695. if (pkt_info.byte_cnt != 0) {
  696. printf ("%s: Received %d byte Packet @ 0x%x\n",
  697. __FUNCTION__, pkt_info.byte_cnt,
  698. pkt_info.buf_ptr);
  699. }
  700. #endif
  701. /* Update statistics. Note byte count includes 4 byte CRC count */
  702. stats->rx_packets++;
  703. stats->rx_bytes += pkt_info.byte_cnt;
  704. /*
  705. * In case received a packet without first / last bits on OR the error
  706. * summary bit is on, the packets needs to be dropeed.
  707. */
  708. if (((pkt_info.
  709. cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
  710. (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
  711. || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
  712. stats->rx_dropped++;
  713. printf ("Received packet spread on multiple descriptors\n");
  714. /* Is this caused by an error ? */
  715. if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
  716. stats->rx_errors++;
  717. }
  718. /* free these descriptors again without forwarding them to the higher layers */
  719. pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
  720. pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
  721. if (eth_rx_return_buff
  722. (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
  723. printf ("Error while returning the RX Desc to Ring\n");
  724. } else {
  725. DP (printf ("RX Desc returned to Ring\n"));
  726. }
  727. /* /free these descriptors again */
  728. } else {
  729. /* !!! call higher layer processing */
  730. #ifdef DEBUG_MV_ETH
  731. printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
  732. #endif
  733. /* let the upper layer handle the packet */
  734. NetReceive ((uchar *) pkt_info.buf_ptr,
  735. (int) pkt_info.byte_cnt);
  736. /* **************************************************************** */
  737. /* free descriptor */
  738. pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
  739. pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
  740. DP (printf
  741. ("RX: pkt_info.buf_ptr = %x\n",
  742. pkt_info.buf_ptr));
  743. if (eth_rx_return_buff
  744. (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
  745. printf ("Error while returning the RX Desc to Ring\n");
  746. } else {
  747. DP (printf ("RX Desc returned to Ring\n"));
  748. }
  749. /* **************************************************************** */
  750. }
  751. }
  752. mv64360_eth_get_stats (dev); /* update statistics */
  753. return 1;
  754. }
  755. /**********************************************************************
  756. * mv64360_eth_get_stats
  757. *
  758. * Returns a pointer to the interface statistics.
  759. *
  760. * Input : dev - a pointer to the required interface
  761. *
  762. * Output : a pointer to the interface's statistics
  763. **********************************************************************/
  764. static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
  765. {
  766. ETH_PORT_INFO *ethernet_private;
  767. struct mv64360_eth_priv *port_private;
  768. unsigned int port_num;
  769. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  770. port_private =
  771. (struct mv64360_eth_priv *) ethernet_private->port_private;
  772. port_num = port_private->port_num;
  773. mv64360_eth_update_stat (dev);
  774. return port_private->stats;
  775. }
  776. /**********************************************************************
  777. * mv64360_eth_update_stat
  778. *
  779. * Update the statistics structure in the private data structure
  780. *
  781. * Input : pointer to ethernet interface network device structure
  782. * Output : N/A
  783. **********************************************************************/
  784. static void mv64360_eth_update_stat (struct eth_device *dev)
  785. {
  786. ETH_PORT_INFO *ethernet_private;
  787. struct mv64360_eth_priv *port_private;
  788. struct net_device_stats *stats;
  789. unsigned int port_num;
  790. volatile unsigned int dummy;
  791. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  792. port_private =
  793. (struct mv64360_eth_priv *) ethernet_private->port_private;
  794. port_num = port_private->port_num;
  795. stats = port_private->stats;
  796. /* These are false updates */
  797. stats->rx_packets += (unsigned long)
  798. eth_read_mib_counter (ethernet_private->port_num,
  799. ETH_MIB_GOOD_FRAMES_RECEIVED);
  800. stats->tx_packets += (unsigned long)
  801. eth_read_mib_counter (ethernet_private->port_num,
  802. ETH_MIB_GOOD_FRAMES_SENT);
  803. stats->rx_bytes += (unsigned long)
  804. eth_read_mib_counter (ethernet_private->port_num,
  805. ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
  806. /*
  807. * Ideally this should be as follows -
  808. *
  809. * stats->rx_bytes += stats->rx_bytes +
  810. * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
  811. * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
  812. *
  813. * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
  814. * is just a dummy read for proper work of the GigE port
  815. */
  816. dummy = eth_read_mib_counter (ethernet_private->port_num,
  817. ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
  818. stats->tx_bytes += (unsigned long)
  819. eth_read_mib_counter (ethernet_private->port_num,
  820. ETH_MIB_GOOD_OCTETS_SENT_LOW);
  821. dummy = eth_read_mib_counter (ethernet_private->port_num,
  822. ETH_MIB_GOOD_OCTETS_SENT_HIGH);
  823. stats->rx_errors += (unsigned long)
  824. eth_read_mib_counter (ethernet_private->port_num,
  825. ETH_MIB_MAC_RECEIVE_ERROR);
  826. /* Rx dropped is for received packet with CRC error */
  827. stats->rx_dropped +=
  828. (unsigned long) eth_read_mib_counter (ethernet_private->
  829. port_num,
  830. ETH_MIB_BAD_CRC_EVENT);
  831. stats->multicast += (unsigned long)
  832. eth_read_mib_counter (ethernet_private->port_num,
  833. ETH_MIB_MULTICAST_FRAMES_RECEIVED);
  834. stats->collisions +=
  835. (unsigned long) eth_read_mib_counter (ethernet_private->
  836. port_num,
  837. ETH_MIB_COLLISION) +
  838. (unsigned long) eth_read_mib_counter (ethernet_private->
  839. port_num,
  840. ETH_MIB_LATE_COLLISION);
  841. /* detailed rx errors */
  842. stats->rx_length_errors +=
  843. (unsigned long) eth_read_mib_counter (ethernet_private->
  844. port_num,
  845. ETH_MIB_UNDERSIZE_RECEIVED)
  846. +
  847. (unsigned long) eth_read_mib_counter (ethernet_private->
  848. port_num,
  849. ETH_MIB_OVERSIZE_RECEIVED);
  850. /* detailed tx errors */
  851. }
  852. #ifndef UPDATE_STATS_BY_SOFTWARE
  853. /**********************************************************************
  854. * mv64360_eth_print_stat
  855. *
  856. * Update the statistics structure in the private data structure
  857. *
  858. * Input : pointer to ethernet interface network device structure
  859. * Output : N/A
  860. **********************************************************************/
  861. static void mv64360_eth_print_stat (struct eth_device *dev)
  862. {
  863. ETH_PORT_INFO *ethernet_private;
  864. struct mv64360_eth_priv *port_private;
  865. struct net_device_stats *stats;
  866. unsigned int port_num;
  867. ethernet_private = (ETH_PORT_INFO *) dev->priv;
  868. port_private =
  869. (struct mv64360_eth_priv *) ethernet_private->port_private;
  870. port_num = port_private->port_num;
  871. stats = port_private->stats;
  872. /* These are false updates */
  873. printf ("\n### Network statistics: ###\n");
  874. printf ("--------------------------\n");
  875. printf (" Packets received: %ld\n", stats->rx_packets);
  876. printf (" Packets send: %ld\n", stats->tx_packets);
  877. printf (" Received bytes: %ld\n", stats->rx_bytes);
  878. printf (" Send bytes: %ld\n", stats->tx_bytes);
  879. if (stats->rx_errors != 0)
  880. printf (" Rx Errors: %ld\n",
  881. stats->rx_errors);
  882. if (stats->rx_dropped != 0)
  883. printf (" Rx dropped (CRC Errors): %ld\n",
  884. stats->rx_dropped);
  885. if (stats->multicast != 0)
  886. printf (" Rx mulicast frames: %ld\n",
  887. stats->multicast);
  888. if (stats->collisions != 0)
  889. printf (" No. of collisions: %ld\n",
  890. stats->collisions);
  891. if (stats->rx_length_errors != 0)
  892. printf (" Rx length errors: %ld\n",
  893. stats->rx_length_errors);
  894. }
  895. #endif
  896. /**************************************************************************
  897. *network_start - Network Kick Off Routine UBoot
  898. *Inputs :
  899. *Outputs :
  900. **************************************************************************/
  901. bool db64360_eth_start (struct eth_device *dev)
  902. {
  903. return (mv64360_eth_open (dev)); /* calls real open */
  904. }
  905. /*************************************************************************
  906. **************************************************************************
  907. **************************************************************************
  908. * The second part is the low level driver of the gigE ethernet ports. *
  909. **************************************************************************
  910. **************************************************************************
  911. *************************************************************************/
  912. /*
  913. * based on Linux code
  914. * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
  915. * Copyright (C) 2002 rabeeh@galileo.co.il
  916. * This program is free software; you can redistribute it and/or
  917. * modify it under the terms of the GNU General Public License
  918. * as published by the Free Software Foundation; either version 2
  919. * of the License, or (at your option) any later version.
  920. * This program is distributed in the hope that it will be useful,
  921. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  922. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  923. * GNU General Public License for more details.
  924. * You should have received a copy of the GNU General Public License
  925. * along with this program; if not, write to the Free Software
  926. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  927. *
  928. */
  929. /********************************************************************************
  930. * Marvell's Gigabit Ethernet controller low level driver
  931. *
  932. * DESCRIPTION:
  933. * This file introduce low level API to Marvell's Gigabit Ethernet
  934. * controller. This Gigabit Ethernet Controller driver API controls
  935. * 1) Operations (i.e. port init, start, reset etc').
  936. * 2) Data flow (i.e. port send, receive etc').
  937. * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
  938. * struct.
  939. * This struct includes user configuration information as well as
  940. * driver internal data needed for its operations.
  941. *
  942. * Supported Features:
  943. * - This low level driver is OS independent. Allocating memory for
  944. * the descriptor rings and buffers are not within the scope of
  945. * this driver.
  946. * - The user is free from Rx/Tx queue managing.
  947. * - This low level driver introduce functionality API that enable
  948. * the to operate Marvell's Gigabit Ethernet Controller in a
  949. * convenient way.
  950. * - Simple Gigabit Ethernet port operation API.
  951. * - Simple Gigabit Ethernet port data flow API.
  952. * - Data flow and operation API support per queue functionality.
  953. * - Support cached descriptors for better performance.
  954. * - Enable access to all four DRAM banks and internal SRAM memory
  955. * spaces.
  956. * - PHY access and control API.
  957. * - Port control register configuration API.
  958. * - Full control over Unicast and Multicast MAC configurations.
  959. *
  960. * Operation flow:
  961. *
  962. * Initialization phase
  963. * This phase complete the initialization of the ETH_PORT_INFO
  964. * struct.
  965. * User information regarding port configuration has to be set
  966. * prior to calling the port initialization routine. For example,
  967. * the user has to assign the port_phy_addr field which is board
  968. * depended parameter.
  969. * In this phase any port Tx/Rx activity is halted, MIB counters
  970. * are cleared, PHY address is set according to user parameter and
  971. * access to DRAM and internal SRAM memory spaces.
  972. *
  973. * Driver ring initialization
  974. * Allocating memory for the descriptor rings and buffers is not
  975. * within the scope of this driver. Thus, the user is required to
  976. * allocate memory for the descriptors ring and buffers. Those
  977. * memory parameters are used by the Rx and Tx ring initialization
  978. * routines in order to curve the descriptor linked list in a form
  979. * of a ring.
  980. * Note: Pay special attention to alignment issues when using
  981. * cached descriptors/buffers. In this phase the driver store
  982. * information in the ETH_PORT_INFO struct regarding each queue
  983. * ring.
  984. *
  985. * Driver start
  986. * This phase prepares the Ethernet port for Rx and Tx activity.
  987. * It uses the information stored in the ETH_PORT_INFO struct to
  988. * initialize the various port registers.
  989. *
  990. * Data flow:
  991. * All packet references to/from the driver are done using PKT_INFO
  992. * struct.
  993. * This struct is a unified struct used with Rx and Tx operations.
  994. * This way the user is not required to be familiar with neither
  995. * Tx nor Rx descriptors structures.
  996. * The driver's descriptors rings are management by indexes.
  997. * Those indexes controls the ring resources and used to indicate
  998. * a SW resource error:
  999. * 'current'
  1000. * This index points to the current available resource for use. For
  1001. * example in Rx process this index will point to the descriptor
  1002. * that will be passed to the user upon calling the receive routine.
  1003. * In Tx process, this index will point to the descriptor
  1004. * that will be assigned with the user packet info and transmitted.
  1005. * 'used'
  1006. * This index points to the descriptor that need to restore its
  1007. * resources. For example in Rx process, using the Rx buffer return
  1008. * API will attach the buffer returned in packet info to the
  1009. * descriptor pointed by 'used'. In Tx process, using the Tx
  1010. * descriptor return will merely return the user packet info with
  1011. * the command status of the transmitted buffer pointed by the
  1012. * 'used' index. Nevertheless, it is essential to use this routine
  1013. * to update the 'used' index.
  1014. * 'first'
  1015. * This index supports Tx Scatter-Gather. It points to the first
  1016. * descriptor of a packet assembled of multiple buffers. For example
  1017. * when in middle of Such packet we have a Tx resource error the
  1018. * 'curr' index get the value of 'first' to indicate that the ring
  1019. * returned to its state before trying to transmit this packet.
  1020. *
  1021. * Receive operation:
  1022. * The eth_port_receive API set the packet information struct,
  1023. * passed by the caller, with received information from the
  1024. * 'current' SDMA descriptor.
  1025. * It is the user responsibility to return this resource back
  1026. * to the Rx descriptor ring to enable the reuse of this source.
  1027. * Return Rx resource is done using the eth_rx_return_buff API.
  1028. *
  1029. * Transmit operation:
  1030. * The eth_port_send API supports Scatter-Gather which enables to
  1031. * send a packet spanned over multiple buffers. This means that
  1032. * for each packet info structure given by the user and put into
  1033. * the Tx descriptors ring, will be transmitted only if the 'LAST'
  1034. * bit will be set in the packet info command status field. This
  1035. * API also consider restriction regarding buffer alignments and
  1036. * sizes.
  1037. * The user must return a Tx resource after ensuring the buffer
  1038. * has been transmitted to enable the Tx ring indexes to update.
  1039. *
  1040. * BOARD LAYOUT
  1041. * This device is on-board. No jumper diagram is necessary.
  1042. *
  1043. * EXTERNAL INTERFACE
  1044. *
  1045. * Prior to calling the initialization routine eth_port_init() the user
  1046. * must set the following fields under ETH_PORT_INFO struct:
  1047. * port_num User Ethernet port number.
  1048. * port_phy_addr User PHY address of Ethernet port.
  1049. * port_mac_addr[6] User defined port MAC address.
  1050. * port_config User port configuration value.
  1051. * port_config_extend User port config extend value.
  1052. * port_sdma_config User port SDMA config value.
  1053. * port_serial_control User port serial control value.
  1054. * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
  1055. * *port_private User scratch pad for user specific data structures.
  1056. *
  1057. * This driver introduce a set of default values:
  1058. * PORT_CONFIG_VALUE Default port configuration value
  1059. * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
  1060. * PORT_SDMA_CONFIG_VALUE Default sdma control value
  1061. * PORT_SERIAL_CONTROL_VALUE Default port serial control value
  1062. *
  1063. * This driver data flow is done using the PKT_INFO struct which is
  1064. * a unified struct for Rx and Tx operations:
  1065. * byte_cnt Tx/Rx descriptor buffer byte count.
  1066. * l4i_chk CPU provided TCP Checksum. For Tx operation only.
  1067. * cmd_sts Tx/Rx descriptor command status.
  1068. * buf_ptr Tx/Rx descriptor buffer pointer.
  1069. * return_info Tx/Rx user resource return information.
  1070. *
  1071. *
  1072. * EXTERNAL SUPPORT REQUIREMENTS
  1073. *
  1074. * This driver requires the following external support:
  1075. *
  1076. * D_CACHE_FLUSH_LINE (address, address offset)
  1077. *
  1078. * This macro applies assembly code to flush and invalidate cache
  1079. * line.
  1080. * address - address base.
  1081. * address offset - address offset
  1082. *
  1083. *
  1084. * CPU_PIPE_FLUSH
  1085. *
  1086. * This macro applies assembly code to flush the CPU pipeline.
  1087. *
  1088. *******************************************************************************/
  1089. /* includes */
  1090. /* defines */
  1091. /* SDMA command macros */
  1092. #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
  1093. MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
  1094. #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
  1095. MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
  1096. (1 << (8 + tx_queue)))
  1097. #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
  1098. MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
  1099. #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
  1100. MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
  1101. #define CURR_RFD_GET(p_curr_desc, queue) \
  1102. ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
  1103. #define CURR_RFD_SET(p_curr_desc, queue) \
  1104. (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
  1105. #define USED_RFD_GET(p_used_desc, queue) \
  1106. ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
  1107. #define USED_RFD_SET(p_used_desc, queue)\
  1108. (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
  1109. #define CURR_TFD_GET(p_curr_desc, queue) \
  1110. ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
  1111. #define CURR_TFD_SET(p_curr_desc, queue) \
  1112. (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
  1113. #define USED_TFD_GET(p_used_desc, queue) \
  1114. ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
  1115. #define USED_TFD_SET(p_used_desc, queue) \
  1116. (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
  1117. #define FIRST_TFD_GET(p_first_desc, queue) \
  1118. ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
  1119. #define FIRST_TFD_SET(p_first_desc, queue) \
  1120. (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
  1121. /* Macros that save access to desc in order to find next desc pointer */
  1122. #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
  1123. #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
  1124. #define LINK_UP_TIMEOUT 100000
  1125. #define PHY_BUSY_TIMEOUT 10000000
  1126. /* locals */
  1127. /* PHY routines */
  1128. static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
  1129. static int ethernet_phy_get (ETH_PORT eth_port_num);
  1130. /* Ethernet Port routines */
  1131. static void eth_set_access_control (ETH_PORT eth_port_num,
  1132. ETH_WIN_PARAM * param);
  1133. static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
  1134. ETH_QUEUE queue, int option);
  1135. #if 0 /* FIXME */
  1136. static bool eth_port_smc_addr (ETH_PORT eth_port_num,
  1137. unsigned char mc_byte,
  1138. ETH_QUEUE queue, int option);
  1139. static bool eth_port_omc_addr (ETH_PORT eth_port_num,
  1140. unsigned char crc8,
  1141. ETH_QUEUE queue, int option);
  1142. #endif
  1143. static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
  1144. int byte_count);
  1145. void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
  1146. typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
  1147. u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
  1148. {
  1149. u32 result = 0;
  1150. u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
  1151. if (enable & (1 << bank))
  1152. return 0;
  1153. if (bank == BANK0)
  1154. result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
  1155. if (bank == BANK1)
  1156. result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
  1157. if (bank == BANK2)
  1158. result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
  1159. if (bank == BANK3)
  1160. result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
  1161. result &= 0x0000ffff;
  1162. result = result << 16;
  1163. return result;
  1164. }
  1165. u32 mv_get_dram_bank_size (MEMORY_BANK bank)
  1166. {
  1167. u32 result = 0;
  1168. u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
  1169. if (enable & (1 << bank))
  1170. return 0;
  1171. if (bank == BANK0)
  1172. result = MV_REG_READ (MV64360_CS_0_SIZE);
  1173. if (bank == BANK1)
  1174. result = MV_REG_READ (MV64360_CS_1_SIZE);
  1175. if (bank == BANK2)
  1176. result = MV_REG_READ (MV64360_CS_2_SIZE);
  1177. if (bank == BANK3)
  1178. result = MV_REG_READ (MV64360_CS_3_SIZE);
  1179. result += 1;
  1180. result &= 0x0000ffff;
  1181. result = result << 16;
  1182. return result;
  1183. }
  1184. u32 mv_get_internal_sram_base (void)
  1185. {
  1186. u32 result;
  1187. result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
  1188. result &= 0x0000ffff;
  1189. result = result << 16;
  1190. return result;
  1191. }
  1192. /*******************************************************************************
  1193. * eth_port_init - Initialize the Ethernet port driver
  1194. *
  1195. * DESCRIPTION:
  1196. * This function prepares the ethernet port to start its activity:
  1197. * 1) Completes the ethernet port driver struct initialization toward port
  1198. * start routine.
  1199. * 2) Resets the device to a quiescent state in case of warm reboot.
  1200. * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
  1201. * 4) Clean MAC tables. The reset status of those tables is unknown.
  1202. * 5) Set PHY address.
  1203. * Note: Call this routine prior to eth_port_start routine and after setting
  1204. * user values in the user fields of Ethernet port control struct (i.e.
  1205. * port_phy_addr).
  1206. *
  1207. * INPUT:
  1208. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
  1209. *
  1210. * OUTPUT:
  1211. * See description.
  1212. *
  1213. * RETURN:
  1214. * None.
  1215. *
  1216. *******************************************************************************/
  1217. static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
  1218. {
  1219. int queue;
  1220. ETH_WIN_PARAM win_param;
  1221. p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
  1222. p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
  1223. p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
  1224. p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
  1225. p_eth_port_ctrl->port_rx_queue_command = 0;
  1226. p_eth_port_ctrl->port_tx_queue_command = 0;
  1227. /* Zero out SW structs */
  1228. for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
  1229. CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
  1230. USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
  1231. p_eth_port_ctrl->rx_resource_err[queue] = false;
  1232. }
  1233. for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
  1234. CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
  1235. USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
  1236. FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
  1237. p_eth_port_ctrl->tx_resource_err[queue] = false;
  1238. }
  1239. eth_port_reset (p_eth_port_ctrl->port_num);
  1240. /* Set access parameters for DRAM bank 0 */
  1241. win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
  1242. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1243. win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
  1244. #ifndef CONFIG_NOT_COHERENT_CACHE
  1245. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1246. #endif
  1247. win_param.high_addr = 0;
  1248. /* Get bank base */
  1249. win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
  1250. win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
  1251. if (win_param.size == 0)
  1252. win_param.enable = 0;
  1253. else
  1254. win_param.enable = 1; /* Enable the access */
  1255. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1256. /* Set the access control for address window (EPAPR) READ & WRITE */
  1257. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1258. /* Set access parameters for DRAM bank 1 */
  1259. win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
  1260. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1261. win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
  1262. #ifndef CONFIG_NOT_COHERENT_CACHE
  1263. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1264. #endif
  1265. win_param.high_addr = 0;
  1266. /* Get bank base */
  1267. win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
  1268. win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
  1269. if (win_param.size == 0)
  1270. win_param.enable = 0;
  1271. else
  1272. win_param.enable = 1; /* Enable the access */
  1273. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1274. /* Set the access control for address window (EPAPR) READ & WRITE */
  1275. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1276. /* Set access parameters for DRAM bank 2 */
  1277. win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
  1278. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1279. win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
  1280. #ifndef CONFIG_NOT_COHERENT_CACHE
  1281. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1282. #endif
  1283. win_param.high_addr = 0;
  1284. /* Get bank base */
  1285. win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
  1286. win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
  1287. if (win_param.size == 0)
  1288. win_param.enable = 0;
  1289. else
  1290. win_param.enable = 1; /* Enable the access */
  1291. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1292. /* Set the access control for address window (EPAPR) READ & WRITE */
  1293. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1294. /* Set access parameters for DRAM bank 3 */
  1295. win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
  1296. win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
  1297. win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
  1298. #ifndef CONFIG_NOT_COHERENT_CACHE
  1299. win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
  1300. #endif
  1301. win_param.high_addr = 0;
  1302. /* Get bank base */
  1303. win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
  1304. win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
  1305. if (win_param.size == 0)
  1306. win_param.enable = 0;
  1307. else
  1308. win_param.enable = 1; /* Enable the access */
  1309. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1310. /* Set the access control for address window (EPAPR) READ & WRITE */
  1311. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1312. /* Set access parameters for Internal SRAM */
  1313. win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
  1314. win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
  1315. win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
  1316. win_param.high_addr = 0;
  1317. win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
  1318. win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */
  1319. win_param.enable = 1; /* Enable the access */
  1320. win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
  1321. /* Set the access control for address window (EPAPR) READ & WRITE */
  1322. eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
  1323. eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
  1324. ethernet_phy_set (p_eth_port_ctrl->port_num,
  1325. p_eth_port_ctrl->port_phy_addr);
  1326. return;
  1327. }
  1328. /*******************************************************************************
  1329. * eth_port_start - Start the Ethernet port activity.
  1330. *
  1331. * DESCRIPTION:
  1332. * This routine prepares the Ethernet port for Rx and Tx activity:
  1333. * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
  1334. * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
  1335. * for Tx and ether_init_rx_desc_ring for Rx)
  1336. * 2. Initialize and enable the Ethernet configuration port by writing to
  1337. * the port's configuration and command registers.
  1338. * 3. Initialize and enable the SDMA by writing to the SDMA's
  1339. * configuration and command registers.
  1340. * After completing these steps, the ethernet port SDMA can starts to
  1341. * perform Rx and Tx activities.
  1342. *
  1343. * Note: Each Rx and Tx queue descriptor's list must be initialized prior
  1344. * to calling this function (use ether_init_tx_desc_ring for Tx queues and
  1345. * ether_init_rx_desc_ring for Rx queues).
  1346. *
  1347. * INPUT:
  1348. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
  1349. *
  1350. * OUTPUT:
  1351. * Ethernet port is ready to receive and transmit.
  1352. *
  1353. * RETURN:
  1354. * false if the port PHY is not up.
  1355. * true otherwise.
  1356. *
  1357. *******************************************************************************/
  1358. static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
  1359. {
  1360. int queue;
  1361. volatile ETH_TX_DESC *p_tx_curr_desc;
  1362. volatile ETH_RX_DESC *p_rx_curr_desc;
  1363. unsigned int phy_reg_data;
  1364. ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
  1365. /* Assignment of Tx CTRP of given queue */
  1366. for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
  1367. CURR_TFD_GET (p_tx_curr_desc, queue);
  1368. MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
  1369. (eth_port_num)
  1370. + (4 * queue)),
  1371. ((unsigned int) p_tx_curr_desc));
  1372. }
  1373. /* Assignment of Rx CRDP of given queue */
  1374. for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
  1375. CURR_RFD_GET (p_rx_curr_desc, queue);
  1376. MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
  1377. (eth_port_num)
  1378. + (4 * queue)),
  1379. ((unsigned int) p_rx_curr_desc));
  1380. if (p_rx_curr_desc != NULL)
  1381. /* Add the assigned Ethernet address to the port's address table */
  1382. eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
  1383. p_eth_port_ctrl->port_mac_addr,
  1384. queue);
  1385. }
  1386. /* Assign port configuration and command. */
  1387. MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
  1388. p_eth_port_ctrl->port_config);
  1389. MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
  1390. p_eth_port_ctrl->port_config_extend);
  1391. MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
  1392. p_eth_port_ctrl->port_serial_control);
  1393. MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
  1394. ETH_SERIAL_PORT_ENABLE);
  1395. /* Assign port SDMA configuration */
  1396. MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
  1397. p_eth_port_ctrl->port_sdma_config);
  1398. MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
  1399. (eth_port_num), 0x3fffffff);
  1400. MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
  1401. (eth_port_num), 0x03fffcff);
  1402. /* Turn off the port/queue bandwidth limitation */
  1403. MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
  1404. /* Enable port Rx. */
  1405. MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
  1406. p_eth_port_ctrl->port_rx_queue_command);
  1407. /* Check if link is up */
  1408. eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
  1409. if (!(phy_reg_data & 0x20))
  1410. return false;
  1411. return true;
  1412. }
  1413. /*******************************************************************************
  1414. * eth_port_uc_addr_set - This function Set the port Unicast address.
  1415. *
  1416. * DESCRIPTION:
  1417. * This function Set the port Ethernet MAC address.
  1418. *
  1419. * INPUT:
  1420. * ETH_PORT eth_port_num Port number.
  1421. * char * p_addr Address to be set
  1422. * ETH_QUEUE queue Rx queue number for this MAC address.
  1423. *
  1424. * OUTPUT:
  1425. * Set MAC address low and high registers. also calls eth_port_uc_addr()
  1426. * To set the unicast table with the proper information.
  1427. *
  1428. * RETURN:
  1429. * N/A.
  1430. *
  1431. *******************************************************************************/
  1432. static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
  1433. unsigned char *p_addr, ETH_QUEUE queue)
  1434. {
  1435. unsigned int mac_h;
  1436. unsigned int mac_l;
  1437. mac_l = (p_addr[4] << 8) | (p_addr[5]);
  1438. mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
  1439. (p_addr[2] << 8) | (p_addr[3] << 0);
  1440. MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
  1441. MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
  1442. /* Accept frames of this address */
  1443. eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
  1444. return;
  1445. }
  1446. /*******************************************************************************
  1447. * eth_port_uc_addr - This function Set the port unicast address table
  1448. *
  1449. * DESCRIPTION:
  1450. * This function locates the proper entry in the Unicast table for the
  1451. * specified MAC nibble and sets its properties according to function
  1452. * parameters.
  1453. *
  1454. * INPUT:
  1455. * ETH_PORT eth_port_num Port number.
  1456. * unsigned char uc_nibble Unicast MAC Address last nibble.
  1457. * ETH_QUEUE queue Rx queue number for this MAC address.
  1458. * int option 0 = Add, 1 = remove address.
  1459. *
  1460. * OUTPUT:
  1461. * This function add/removes MAC addresses from the port unicast address
  1462. * table.
  1463. *
  1464. * RETURN:
  1465. * true is output succeeded.
  1466. * false if option parameter is invalid.
  1467. *
  1468. *******************************************************************************/
  1469. static bool eth_port_uc_addr (ETH_PORT eth_port_num,
  1470. unsigned char uc_nibble,
  1471. ETH_QUEUE queue, int option)
  1472. {
  1473. unsigned int unicast_reg;
  1474. unsigned int tbl_offset;
  1475. unsigned int reg_offset;
  1476. /* Locate the Unicast table entry */
  1477. uc_nibble = (0xf & uc_nibble);
  1478. tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
  1479. reg_offset = uc_nibble % 4; /* Entry offset within the above register */
  1480. switch (option) {
  1481. case REJECT_MAC_ADDR:
  1482. /* Clear accepts frame bit at specified unicast DA table entry */
  1483. unicast_reg =
  1484. MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1485. (eth_port_num)
  1486. + tbl_offset));
  1487. unicast_reg &= (0x0E << (8 * reg_offset));
  1488. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1489. (eth_port_num)
  1490. + tbl_offset), unicast_reg);
  1491. break;
  1492. case ACCEPT_MAC_ADDR:
  1493. /* Set accepts frame bit at unicast DA filter table entry */
  1494. unicast_reg =
  1495. MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1496. (eth_port_num)
  1497. + tbl_offset));
  1498. unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
  1499. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1500. (eth_port_num)
  1501. + tbl_offset), unicast_reg);
  1502. break;
  1503. default:
  1504. return false;
  1505. }
  1506. return true;
  1507. }
  1508. #if 0 /* FIXME */
  1509. /*******************************************************************************
  1510. * eth_port_mc_addr - Multicast address settings.
  1511. *
  1512. * DESCRIPTION:
  1513. * This API controls the MV device MAC multicast support.
  1514. * The MV device supports multicast using two tables:
  1515. * 1) Special Multicast Table for MAC addresses of the form
  1516. * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
  1517. * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
  1518. * Table entries in the DA-Filter table.
  1519. * In this case, the function calls eth_port_smc_addr() routine to set the
  1520. * Special Multicast Table.
  1521. * 2) Other Multicast Table for multicast of another type. A CRC-8bit
  1522. * is used as an index to the Other Multicast Table entries in the
  1523. * DA-Filter table.
  1524. * In this case, the function calculates the CRC-8bit value and calls
  1525. * eth_port_omc_addr() routine to set the Other Multicast Table.
  1526. * INPUT:
  1527. * ETH_PORT eth_port_num Port number.
  1528. * unsigned char *p_addr Unicast MAC Address.
  1529. * ETH_QUEUE queue Rx queue number for this MAC address.
  1530. * int option 0 = Add, 1 = remove address.
  1531. *
  1532. * OUTPUT:
  1533. * See description.
  1534. *
  1535. * RETURN:
  1536. * true is output succeeded.
  1537. * false if add_address_table_entry( ) failed.
  1538. *
  1539. *******************************************************************************/
  1540. static void eth_port_mc_addr (ETH_PORT eth_port_num,
  1541. unsigned char *p_addr,
  1542. ETH_QUEUE queue, int option)
  1543. {
  1544. unsigned int mac_h;
  1545. unsigned int mac_l;
  1546. unsigned char crc_result = 0;
  1547. int mac_array[48];
  1548. int crc[8];
  1549. int i;
  1550. if ((p_addr[0] == 0x01) &&
  1551. (p_addr[1] == 0x00) &&
  1552. (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
  1553. eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
  1554. else {
  1555. /* Calculate CRC-8 out of the given address */
  1556. mac_h = (p_addr[0] << 8) | (p_addr[1]);
  1557. mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
  1558. (p_addr[4] << 8) | (p_addr[5] << 0);
  1559. for (i = 0; i < 32; i++)
  1560. mac_array[i] = (mac_l >> i) & 0x1;
  1561. for (i = 32; i < 48; i++)
  1562. mac_array[i] = (mac_h >> (i - 32)) & 0x1;
  1563. crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
  1564. mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
  1565. mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
  1566. mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
  1567. mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
  1568. mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
  1569. mac_array[6] ^ mac_array[0];
  1570. crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
  1571. mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
  1572. mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
  1573. mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
  1574. mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
  1575. mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
  1576. mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
  1577. mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
  1578. mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
  1579. mac_array[0];
  1580. crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
  1581. mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
  1582. mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
  1583. mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
  1584. mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
  1585. mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
  1586. mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
  1587. mac_array[2] ^ mac_array[1] ^ mac_array[0];
  1588. crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
  1589. mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
  1590. mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
  1591. mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
  1592. mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
  1593. mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
  1594. mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
  1595. mac_array[2] ^ mac_array[1];
  1596. crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
  1597. mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
  1598. mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
  1599. mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
  1600. mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
  1601. mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
  1602. mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
  1603. mac_array[2];
  1604. crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
  1605. mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
  1606. mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
  1607. mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
  1608. mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
  1609. mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
  1610. mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
  1611. mac_array[3];
  1612. crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
  1613. mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
  1614. mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
  1615. mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
  1616. mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
  1617. mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
  1618. mac_array[6] ^ mac_array[5] ^ mac_array[4];
  1619. crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
  1620. mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
  1621. mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
  1622. mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
  1623. mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
  1624. mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
  1625. mac_array[6] ^ mac_array[5];
  1626. for (i = 0; i < 8; i++)
  1627. crc_result = crc_result | (crc[i] << i);
  1628. eth_port_omc_addr (eth_port_num, crc_result, queue, option);
  1629. }
  1630. return;
  1631. }
  1632. /*******************************************************************************
  1633. * eth_port_smc_addr - Special Multicast address settings.
  1634. *
  1635. * DESCRIPTION:
  1636. * This routine controls the MV device special MAC multicast support.
  1637. * The Special Multicast Table for MAC addresses supports MAC of the form
  1638. * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
  1639. * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
  1640. * Table entries in the DA-Filter table.
  1641. * This function set the Special Multicast Table appropriate entry
  1642. * according to the argument given.
  1643. *
  1644. * INPUT:
  1645. * ETH_PORT eth_port_num Port number.
  1646. * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
  1647. * ETH_QUEUE queue Rx queue number for this MAC address.
  1648. * int option 0 = Add, 1 = remove address.
  1649. *
  1650. * OUTPUT:
  1651. * See description.
  1652. *
  1653. * RETURN:
  1654. * true is output succeeded.
  1655. * false if option parameter is invalid.
  1656. *
  1657. *******************************************************************************/
  1658. static bool eth_port_smc_addr (ETH_PORT eth_port_num,
  1659. unsigned char mc_byte,
  1660. ETH_QUEUE queue, int option)
  1661. {
  1662. unsigned int smc_table_reg;
  1663. unsigned int tbl_offset;
  1664. unsigned int reg_offset;
  1665. /* Locate the SMC table entry */
  1666. tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
  1667. reg_offset = mc_byte % 4; /* Entry offset within the above register */
  1668. queue &= 0x7;
  1669. switch (option) {
  1670. case REJECT_MAC_ADDR:
  1671. /* Clear accepts frame bit at specified Special DA table entry */
  1672. smc_table_reg =
  1673. MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1674. smc_table_reg &= (0x0E << (8 * reg_offset));
  1675. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
  1676. break;
  1677. case ACCEPT_MAC_ADDR:
  1678. /* Set accepts frame bit at specified Special DA table entry */
  1679. smc_table_reg =
  1680. MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1681. smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
  1682. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
  1683. break;
  1684. default:
  1685. return false;
  1686. }
  1687. return true;
  1688. }
  1689. /*******************************************************************************
  1690. * eth_port_omc_addr - Multicast address settings.
  1691. *
  1692. * DESCRIPTION:
  1693. * This routine controls the MV device Other MAC multicast support.
  1694. * The Other Multicast Table is used for multicast of another type.
  1695. * A CRC-8bit is used as an index to the Other Multicast Table entries
  1696. * in the DA-Filter table.
  1697. * The function gets the CRC-8bit value from the calling routine and
  1698. * set the Other Multicast Table appropriate entry according to the
  1699. * CRC-8 argument given.
  1700. *
  1701. * INPUT:
  1702. * ETH_PORT eth_port_num Port number.
  1703. * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
  1704. * ETH_QUEUE queue Rx queue number for this MAC address.
  1705. * int option 0 = Add, 1 = remove address.
  1706. *
  1707. * OUTPUT:
  1708. * See description.
  1709. *
  1710. * RETURN:
  1711. * true is output succeeded.
  1712. * false if option parameter is invalid.
  1713. *
  1714. *******************************************************************************/
  1715. static bool eth_port_omc_addr (ETH_PORT eth_port_num,
  1716. unsigned char crc8,
  1717. ETH_QUEUE queue, int option)
  1718. {
  1719. unsigned int omc_table_reg;
  1720. unsigned int tbl_offset;
  1721. unsigned int reg_offset;
  1722. /* Locate the OMC table entry */
  1723. tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
  1724. reg_offset = crc8 % 4; /* Entry offset within the above register */
  1725. queue &= 0x7;
  1726. switch (option) {
  1727. case REJECT_MAC_ADDR:
  1728. /* Clear accepts frame bit at specified Other DA table entry */
  1729. omc_table_reg =
  1730. MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1731. omc_table_reg &= (0x0E << (8 * reg_offset));
  1732. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
  1733. break;
  1734. case ACCEPT_MAC_ADDR:
  1735. /* Set accepts frame bit at specified Other DA table entry */
  1736. omc_table_reg =
  1737. MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
  1738. omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
  1739. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
  1740. break;
  1741. default:
  1742. return false;
  1743. }
  1744. return true;
  1745. }
  1746. #endif
  1747. /*******************************************************************************
  1748. * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
  1749. *
  1750. * DESCRIPTION:
  1751. * Go through all the DA filter tables (Unicast, Special Multicast & Other
  1752. * Multicast) and set each entry to 0.
  1753. *
  1754. * INPUT:
  1755. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1756. *
  1757. * OUTPUT:
  1758. * Multicast and Unicast packets are rejected.
  1759. *
  1760. * RETURN:
  1761. * None.
  1762. *
  1763. *******************************************************************************/
  1764. static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
  1765. {
  1766. int table_index;
  1767. /* Clear DA filter unicast table (Ex_dFUT) */
  1768. for (table_index = 0; table_index <= 0xC; table_index += 4)
  1769. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1770. (eth_port_num) + table_index), 0);
  1771. for (table_index = 0; table_index <= 0xFC; table_index += 4) {
  1772. /* Clear DA filter special multicast table (Ex_dFSMT) */
  1773. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
  1774. /* Clear DA filter other multicast table (Ex_dFOMT) */
  1775. MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
  1776. }
  1777. }
  1778. /*******************************************************************************
  1779. * eth_clear_mib_counters - Clear all MIB counters
  1780. *
  1781. * DESCRIPTION:
  1782. * This function clears all MIB counters of a specific ethernet port.
  1783. * A read from the MIB counter will reset the counter.
  1784. *
  1785. * INPUT:
  1786. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1787. *
  1788. * OUTPUT:
  1789. * After reading all MIB counters, the counters resets.
  1790. *
  1791. * RETURN:
  1792. * MIB counter value.
  1793. *
  1794. *******************************************************************************/
  1795. static void eth_clear_mib_counters (ETH_PORT eth_port_num)
  1796. {
  1797. int i;
  1798. unsigned int dummy;
  1799. /* Perform dummy reads from MIB counters */
  1800. for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
  1801. i += 4)
  1802. dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
  1803. (eth_port_num) + i));
  1804. return;
  1805. }
  1806. /*******************************************************************************
  1807. * eth_read_mib_counter - Read a MIB counter
  1808. *
  1809. * DESCRIPTION:
  1810. * This function reads a MIB counter of a specific ethernet port.
  1811. * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
  1812. * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
  1813. * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
  1814. * ETH_MIB_GOOD_OCTETS_SENT_HIGH
  1815. *
  1816. * INPUT:
  1817. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1818. * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
  1819. *
  1820. * OUTPUT:
  1821. * After reading the MIB counter, the counter resets.
  1822. *
  1823. * RETURN:
  1824. * MIB counter value.
  1825. *
  1826. *******************************************************************************/
  1827. unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
  1828. unsigned int mib_offset)
  1829. {
  1830. return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
  1831. + mib_offset));
  1832. }
  1833. /*******************************************************************************
  1834. * ethernet_phy_set - Set the ethernet port PHY address.
  1835. *
  1836. * DESCRIPTION:
  1837. * This routine set the ethernet port PHY address according to given
  1838. * parameter.
  1839. *
  1840. * INPUT:
  1841. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1842. *
  1843. * OUTPUT:
  1844. * Set PHY Address Register with given PHY address parameter.
  1845. *
  1846. * RETURN:
  1847. * None.
  1848. *
  1849. *******************************************************************************/
  1850. static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
  1851. {
  1852. unsigned int reg_data;
  1853. reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
  1854. reg_data &= ~(0x1F << (5 * eth_port_num));
  1855. reg_data |= (phy_addr << (5 * eth_port_num));
  1856. MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
  1857. return;
  1858. }
  1859. /*******************************************************************************
  1860. * ethernet_phy_get - Get the ethernet port PHY address.
  1861. *
  1862. * DESCRIPTION:
  1863. * This routine returns the given ethernet port PHY address.
  1864. *
  1865. * INPUT:
  1866. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1867. *
  1868. * OUTPUT:
  1869. * None.
  1870. *
  1871. * RETURN:
  1872. * PHY address.
  1873. *
  1874. *******************************************************************************/
  1875. static int ethernet_phy_get (ETH_PORT eth_port_num)
  1876. {
  1877. unsigned int reg_data;
  1878. reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
  1879. return ((reg_data >> (5 * eth_port_num)) & 0x1f);
  1880. }
  1881. /*******************************************************************************
  1882. * ethernet_phy_reset - Reset Ethernet port PHY.
  1883. *
  1884. * DESCRIPTION:
  1885. * This routine utilize the SMI interface to reset the ethernet port PHY.
  1886. * The routine waits until the link is up again or link up is timeout.
  1887. *
  1888. * INPUT:
  1889. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1890. *
  1891. * OUTPUT:
  1892. * The ethernet port PHY renew its link.
  1893. *
  1894. * RETURN:
  1895. * None.
  1896. *
  1897. *******************************************************************************/
  1898. static bool ethernet_phy_reset (ETH_PORT eth_port_num)
  1899. {
  1900. unsigned int time_out = 50;
  1901. unsigned int phy_reg_data;
  1902. /* Reset the PHY */
  1903. eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
  1904. phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
  1905. eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
  1906. /* Poll on the PHY LINK */
  1907. do {
  1908. eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
  1909. if (time_out-- == 0)
  1910. return false;
  1911. }
  1912. while (!(phy_reg_data & 0x20));
  1913. return true;
  1914. }
  1915. /*******************************************************************************
  1916. * eth_port_reset - Reset Ethernet port
  1917. *
  1918. * DESCRIPTION:
  1919. * This routine resets the chip by aborting any SDMA engine activity and
  1920. * clearing the MIB counters. The Receiver and the Transmit unit are in
  1921. * idle state after this command is performed and the port is disabled.
  1922. *
  1923. * INPUT:
  1924. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1925. *
  1926. * OUTPUT:
  1927. * Channel activity is halted.
  1928. *
  1929. * RETURN:
  1930. * None.
  1931. *
  1932. *******************************************************************************/
  1933. static void eth_port_reset (ETH_PORT eth_port_num)
  1934. {
  1935. unsigned int reg_data;
  1936. /* Stop Tx port activity. Check port Tx activity. */
  1937. reg_data =
  1938. MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
  1939. (eth_port_num));
  1940. if (reg_data & 0xFF) {
  1941. /* Issue stop command for active channels only */
  1942. MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
  1943. (eth_port_num), (reg_data << 8));
  1944. /* Wait for all Tx activity to terminate. */
  1945. do {
  1946. /* Check port cause register that all Tx queues are stopped */
  1947. reg_data =
  1948. MV_REG_READ
  1949. (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
  1950. (eth_port_num));
  1951. }
  1952. while (reg_data & 0xFF);
  1953. }
  1954. /* Stop Rx port activity. Check port Rx activity. */
  1955. reg_data =
  1956. MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
  1957. (eth_port_num));
  1958. if (reg_data & 0xFF) {
  1959. /* Issue stop command for active channels only */
  1960. MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
  1961. (eth_port_num), (reg_data << 8));
  1962. /* Wait for all Rx activity to terminate. */
  1963. do {
  1964. /* Check port cause register that all Rx queues are stopped */
  1965. reg_data =
  1966. MV_REG_READ
  1967. (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
  1968. (eth_port_num));
  1969. }
  1970. while (reg_data & 0xFF);
  1971. }
  1972. /* Clear all MIB counters */
  1973. eth_clear_mib_counters (eth_port_num);
  1974. /* Reset the Enable bit in the Configuration Register */
  1975. reg_data =
  1976. MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
  1977. (eth_port_num));
  1978. reg_data &= ~ETH_SERIAL_PORT_ENABLE;
  1979. MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
  1980. reg_data);
  1981. return;
  1982. }
  1983. #if 0 /* Not needed here */
  1984. /*******************************************************************************
  1985. * ethernet_set_config_reg - Set specified bits in configuration register.
  1986. *
  1987. * DESCRIPTION:
  1988. * This function sets specified bits in the given ethernet
  1989. * configuration register.
  1990. *
  1991. * INPUT:
  1992. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  1993. * unsigned int value 32 bit value.
  1994. *
  1995. * OUTPUT:
  1996. * The set bits in the value parameter are set in the configuration
  1997. * register.
  1998. *
  1999. * RETURN:
  2000. * None.
  2001. *
  2002. *******************************************************************************/
  2003. static void ethernet_set_config_reg (ETH_PORT eth_port_num,
  2004. unsigned int value)
  2005. {
  2006. unsigned int eth_config_reg;
  2007. eth_config_reg =
  2008. MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
  2009. eth_config_reg |= value;
  2010. MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
  2011. eth_config_reg);
  2012. return;
  2013. }
  2014. #endif
  2015. #if 0 /* FIXME */
  2016. /*******************************************************************************
  2017. * ethernet_reset_config_reg - Reset specified bits in configuration register.
  2018. *
  2019. * DESCRIPTION:
  2020. * This function resets specified bits in the given Ethernet
  2021. * configuration register.
  2022. *
  2023. * INPUT:
  2024. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2025. * unsigned int value 32 bit value.
  2026. *
  2027. * OUTPUT:
  2028. * The set bits in the value parameter are reset in the configuration
  2029. * register.
  2030. *
  2031. * RETURN:
  2032. * None.
  2033. *
  2034. *******************************************************************************/
  2035. static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
  2036. unsigned int value)
  2037. {
  2038. unsigned int eth_config_reg;
  2039. eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
  2040. (eth_port_num));
  2041. eth_config_reg &= ~value;
  2042. MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
  2043. eth_config_reg);
  2044. return;
  2045. }
  2046. #endif
  2047. #if 0 /* Not needed here */
  2048. /*******************************************************************************
  2049. * ethernet_get_config_reg - Get the port configuration register
  2050. *
  2051. * DESCRIPTION:
  2052. * This function returns the configuration register value of the given
  2053. * ethernet port.
  2054. *
  2055. * INPUT:
  2056. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2057. *
  2058. * OUTPUT:
  2059. * None.
  2060. *
  2061. * RETURN:
  2062. * Port configuration register value.
  2063. *
  2064. *******************************************************************************/
  2065. static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
  2066. {
  2067. unsigned int eth_config_reg;
  2068. eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
  2069. (eth_port_num));
  2070. return eth_config_reg;
  2071. }
  2072. #endif
  2073. /*******************************************************************************
  2074. * eth_port_read_smi_reg - Read PHY registers
  2075. *
  2076. * DESCRIPTION:
  2077. * This routine utilize the SMI interface to interact with the PHY in
  2078. * order to perform PHY register read.
  2079. *
  2080. * INPUT:
  2081. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2082. * unsigned int phy_reg PHY register address offset.
  2083. * unsigned int *value Register value buffer.
  2084. *
  2085. * OUTPUT:
  2086. * Write the value of a specified PHY register into given buffer.
  2087. *
  2088. * RETURN:
  2089. * false if the PHY is busy or read data is not in valid state.
  2090. * true otherwise.
  2091. *
  2092. *******************************************************************************/
  2093. static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
  2094. unsigned int phy_reg, unsigned int *value)
  2095. {
  2096. unsigned int reg_value;
  2097. unsigned int time_out = PHY_BUSY_TIMEOUT;
  2098. int phy_addr;
  2099. phy_addr = ethernet_phy_get (eth_port_num);
  2100. /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
  2101. /* first check that it is not busy */
  2102. do {
  2103. reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
  2104. if (time_out-- == 0) {
  2105. return false;
  2106. }
  2107. }
  2108. while (reg_value & ETH_SMI_BUSY);
  2109. /* not busy */
  2110. MV_REG_WRITE (MV64360_ETH_SMI_REG,
  2111. (phy_addr << 16) | (phy_reg << 21) |
  2112. ETH_SMI_OPCODE_READ);
  2113. time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
  2114. do {
  2115. reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
  2116. if (time_out-- == 0) {
  2117. return false;
  2118. }
  2119. }
  2120. while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
  2121. /* Wait for the data to update in the SMI register */
  2122. #define PHY_UPDATE_TIMEOUT 10000
  2123. for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
  2124. reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
  2125. *value = reg_value & 0xffff;
  2126. return true;
  2127. }
  2128. /*******************************************************************************
  2129. * eth_port_write_smi_reg - Write to PHY registers
  2130. *
  2131. * DESCRIPTION:
  2132. * This routine utilize the SMI interface to interact with the PHY in
  2133. * order to perform writes to PHY registers.
  2134. *
  2135. * INPUT:
  2136. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2137. * unsigned int phy_reg PHY register address offset.
  2138. * unsigned int value Register value.
  2139. *
  2140. * OUTPUT:
  2141. * Write the given value to the specified PHY register.
  2142. *
  2143. * RETURN:
  2144. * false if the PHY is busy.
  2145. * true otherwise.
  2146. *
  2147. *******************************************************************************/
  2148. static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
  2149. unsigned int phy_reg, unsigned int value)
  2150. {
  2151. unsigned int reg_value;
  2152. unsigned int time_out = PHY_BUSY_TIMEOUT;
  2153. int phy_addr;
  2154. phy_addr = ethernet_phy_get (eth_port_num);
  2155. /* first check that it is not busy */
  2156. do {
  2157. reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
  2158. if (time_out-- == 0) {
  2159. return false;
  2160. }
  2161. }
  2162. while (reg_value & ETH_SMI_BUSY);
  2163. /* not busy */
  2164. MV_REG_WRITE (MV64360_ETH_SMI_REG,
  2165. (phy_addr << 16) | (phy_reg << 21) |
  2166. ETH_SMI_OPCODE_WRITE | (value & 0xffff));
  2167. return true;
  2168. }
  2169. /*******************************************************************************
  2170. * eth_set_access_control - Config address decode parameters for Ethernet unit
  2171. *
  2172. * DESCRIPTION:
  2173. * This function configures the address decode parameters for the Gigabit
  2174. * Ethernet Controller according the given parameters struct.
  2175. *
  2176. * INPUT:
  2177. * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
  2178. * ETH_WIN_PARAM *param Address decode parameter struct.
  2179. *
  2180. * OUTPUT:
  2181. * An access window is opened using the given access parameters.
  2182. *
  2183. * RETURN:
  2184. * None.
  2185. *
  2186. *******************************************************************************/
  2187. static void eth_set_access_control (ETH_PORT eth_port_num,
  2188. ETH_WIN_PARAM * param)
  2189. {
  2190. unsigned int access_prot_reg;
  2191. /* Set access control register */
  2192. access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
  2193. (eth_port_num));
  2194. access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
  2195. access_prot_reg |= (param->access_ctrl << (param->win * 2));
  2196. MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
  2197. access_prot_reg);
  2198. /* Set window Size reg (SR) */
  2199. MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
  2200. (ETH_SIZE_REG_GAP * param->win)),
  2201. (((param->size / 0x10000) - 1) << 16));
  2202. /* Set window Base address reg (BA) */
  2203. MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
  2204. (param->target | param->attributes | param->base_addr));
  2205. /* High address remap reg (HARR) */
  2206. if (param->win < 4)
  2207. MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
  2208. (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
  2209. param->high_addr);
  2210. /* Base address enable reg (BARER) */
  2211. if (param->enable == 1)
  2212. MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
  2213. (1 << param->win));
  2214. else
  2215. MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
  2216. (1 << param->win));
  2217. }
  2218. /*******************************************************************************
  2219. * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
  2220. *
  2221. * DESCRIPTION:
  2222. * This function prepares a Rx chained list of descriptors and packet
  2223. * buffers in a form of a ring. The routine must be called after port
  2224. * initialization routine and before port start routine.
  2225. * The Ethernet SDMA engine uses CPU bus addresses to access the various
  2226. * devices in the system (i.e. DRAM). This function uses the ethernet
  2227. * struct 'virtual to physical' routine (set by the user) to set the ring
  2228. * with physical addresses.
  2229. *
  2230. * INPUT:
  2231. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2232. * ETH_QUEUE rx_queue Number of Rx queue.
  2233. * int rx_desc_num Number of Rx descriptors
  2234. * int rx_buff_size Size of Rx buffer
  2235. * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
  2236. * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
  2237. *
  2238. * OUTPUT:
  2239. * The routine updates the Ethernet port control struct with information
  2240. * regarding the Rx descriptors and buffers.
  2241. *
  2242. * RETURN:
  2243. * false if the given descriptors memory area is not aligned according to
  2244. * Ethernet SDMA specifications.
  2245. * true otherwise.
  2246. *
  2247. *******************************************************************************/
  2248. static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  2249. ETH_QUEUE rx_queue,
  2250. int rx_desc_num,
  2251. int rx_buff_size,
  2252. unsigned int rx_desc_base_addr,
  2253. unsigned int rx_buff_base_addr)
  2254. {
  2255. ETH_RX_DESC *p_rx_desc;
  2256. ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
  2257. unsigned int buffer_addr;
  2258. int ix; /* a counter */
  2259. p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
  2260. p_rx_prev_desc = p_rx_desc;
  2261. buffer_addr = rx_buff_base_addr;
  2262. /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
  2263. if (rx_buff_base_addr & 0xF)
  2264. return false;
  2265. /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
  2266. if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
  2267. return false;
  2268. /* Rx buffers must be 64-bit aligned. */
  2269. if ((rx_buff_base_addr + rx_buff_size) & 0x7)
  2270. return false;
  2271. /* initialize the Rx descriptors ring */
  2272. for (ix = 0; ix < rx_desc_num; ix++) {
  2273. p_rx_desc->buf_size = rx_buff_size;
  2274. p_rx_desc->byte_cnt = 0x0000;
  2275. p_rx_desc->cmd_sts =
  2276. ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
  2277. p_rx_desc->next_desc_ptr =
  2278. ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
  2279. p_rx_desc->buf_ptr = buffer_addr;
  2280. p_rx_desc->return_info = 0x00000000;
  2281. D_CACHE_FLUSH_LINE (p_rx_desc, 0);
  2282. buffer_addr += rx_buff_size;
  2283. p_rx_prev_desc = p_rx_desc;
  2284. p_rx_desc = (ETH_RX_DESC *)
  2285. ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
  2286. }
  2287. /* Closing Rx descriptors ring */
  2288. p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
  2289. D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
  2290. /* Save Rx desc pointer to driver struct. */
  2291. CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
  2292. USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
  2293. p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
  2294. (ETH_RX_DESC *) rx_desc_base_addr;
  2295. p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
  2296. rx_desc_num * RX_DESC_ALIGNED_SIZE;
  2297. p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
  2298. return true;
  2299. }
  2300. /*******************************************************************************
  2301. * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
  2302. *
  2303. * DESCRIPTION:
  2304. * This function prepares a Tx chained list of descriptors and packet
  2305. * buffers in a form of a ring. The routine must be called after port
  2306. * initialization routine and before port start routine.
  2307. * The Ethernet SDMA engine uses CPU bus addresses to access the various
  2308. * devices in the system (i.e. DRAM). This function uses the ethernet
  2309. * struct 'virtual to physical' routine (set by the user) to set the ring
  2310. * with physical addresses.
  2311. *
  2312. * INPUT:
  2313. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2314. * ETH_QUEUE tx_queue Number of Tx queue.
  2315. * int tx_desc_num Number of Tx descriptors
  2316. * int tx_buff_size Size of Tx buffer
  2317. * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
  2318. * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
  2319. *
  2320. * OUTPUT:
  2321. * The routine updates the Ethernet port control struct with information
  2322. * regarding the Tx descriptors and buffers.
  2323. *
  2324. * RETURN:
  2325. * false if the given descriptors memory area is not aligned according to
  2326. * Ethernet SDMA specifications.
  2327. * true otherwise.
  2328. *
  2329. *******************************************************************************/
  2330. static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
  2331. ETH_QUEUE tx_queue,
  2332. int tx_desc_num,
  2333. int tx_buff_size,
  2334. unsigned int tx_desc_base_addr,
  2335. unsigned int tx_buff_base_addr)
  2336. {
  2337. ETH_TX_DESC *p_tx_desc;
  2338. ETH_TX_DESC *p_tx_prev_desc;
  2339. unsigned int buffer_addr;
  2340. int ix; /* a counter */
  2341. /* save the first desc pointer to link with the last descriptor */
  2342. p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
  2343. p_tx_prev_desc = p_tx_desc;
  2344. buffer_addr = tx_buff_base_addr;
  2345. /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
  2346. if (tx_buff_base_addr & 0xF)
  2347. return false;
  2348. /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
  2349. if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
  2350. || (tx_buff_size < TX_BUFFER_MIN_SIZE))
  2351. return false;
  2352. /* Initialize the Tx descriptors ring */
  2353. for (ix = 0; ix < tx_desc_num; ix++) {
  2354. p_tx_desc->byte_cnt = 0x0000;
  2355. p_tx_desc->l4i_chk = 0x0000;
  2356. p_tx_desc->cmd_sts = 0x00000000;
  2357. p_tx_desc->next_desc_ptr =
  2358. ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
  2359. p_tx_desc->buf_ptr = buffer_addr;
  2360. p_tx_desc->return_info = 0x00000000;
  2361. D_CACHE_FLUSH_LINE (p_tx_desc, 0);
  2362. buffer_addr += tx_buff_size;
  2363. p_tx_prev_desc = p_tx_desc;
  2364. p_tx_desc = (ETH_TX_DESC *)
  2365. ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
  2366. }
  2367. /* Closing Tx descriptors ring */
  2368. p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
  2369. D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
  2370. /* Set Tx desc pointer in driver struct. */
  2371. CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
  2372. USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
  2373. /* Init Tx ring base and size parameters */
  2374. p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
  2375. (ETH_TX_DESC *) tx_desc_base_addr;
  2376. p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
  2377. (tx_desc_num * TX_DESC_ALIGNED_SIZE);
  2378. /* Add the queue to the list of Tx queues of this port */
  2379. p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
  2380. return true;
  2381. }
  2382. /*******************************************************************************
  2383. * eth_port_send - Send an Ethernet packet
  2384. *
  2385. * DESCRIPTION:
  2386. * This routine send a given packet described by p_pktinfo parameter. It
  2387. * supports transmitting of a packet spaned over multiple buffers. The
  2388. * routine updates 'curr' and 'first' indexes according to the packet
  2389. * segment passed to the routine. In case the packet segment is first,
  2390. * the 'first' index is update. In any case, the 'curr' index is updated.
  2391. * If the routine get into Tx resource error it assigns 'curr' index as
  2392. * 'first'. This way the function can abort Tx process of multiple
  2393. * descriptors per packet.
  2394. *
  2395. * INPUT:
  2396. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2397. * ETH_QUEUE tx_queue Number of Tx queue.
  2398. * PKT_INFO *p_pkt_info User packet buffer.
  2399. *
  2400. * OUTPUT:
  2401. * Tx ring 'curr' and 'first' indexes are updated.
  2402. *
  2403. * RETURN:
  2404. * ETH_QUEUE_FULL in case of Tx resource error.
  2405. * ETH_ERROR in case the routine can not access Tx desc ring.
  2406. * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
  2407. * ETH_OK otherwise.
  2408. *
  2409. *******************************************************************************/
  2410. static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
  2411. ETH_QUEUE tx_queue,
  2412. PKT_INFO * p_pkt_info)
  2413. {
  2414. volatile ETH_TX_DESC *p_tx_desc_first;
  2415. volatile ETH_TX_DESC *p_tx_desc_curr;
  2416. volatile ETH_TX_DESC *p_tx_next_desc_curr;
  2417. volatile ETH_TX_DESC *p_tx_desc_used;
  2418. unsigned int command_status;
  2419. /* Do not process Tx ring in case of Tx ring resource error */
  2420. if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
  2421. return ETH_QUEUE_FULL;
  2422. /* Get the Tx Desc ring indexes */
  2423. CURR_TFD_GET (p_tx_desc_curr, tx_queue);
  2424. USED_TFD_GET (p_tx_desc_used, tx_queue);
  2425. if (p_tx_desc_curr == NULL)
  2426. return ETH_ERROR;
  2427. /* The following parameters are used to save readings from memory */
  2428. p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
  2429. command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
  2430. if (command_status & (ETH_TX_FIRST_DESC)) {
  2431. /* Update first desc */
  2432. FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
  2433. p_tx_desc_first = p_tx_desc_curr;
  2434. } else {
  2435. FIRST_TFD_GET (p_tx_desc_first, tx_queue);
  2436. command_status |= ETH_BUFFER_OWNED_BY_DMA;
  2437. }
  2438. /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
  2439. /* boundary. We use the memory allocated for Tx descriptor. This memory */
  2440. /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
  2441. if (p_pkt_info->byte_cnt <= 8) {
  2442. printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
  2443. return ETH_ERROR;
  2444. p_tx_desc_curr->buf_ptr =
  2445. (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
  2446. eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
  2447. p_pkt_info->byte_cnt);
  2448. } else
  2449. p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
  2450. p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
  2451. p_tx_desc_curr->return_info = p_pkt_info->return_info;
  2452. if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
  2453. /* Set last desc with DMA ownership and interrupt enable. */
  2454. p_tx_desc_curr->cmd_sts = command_status |
  2455. ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
  2456. if (p_tx_desc_curr != p_tx_desc_first)
  2457. p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
  2458. /* Flush CPU pipe */
  2459. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
  2460. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
  2461. CPU_PIPE_FLUSH;
  2462. /* Apply send command */
  2463. ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
  2464. /* Finish Tx packet. Update first desc in case of Tx resource error */
  2465. p_tx_desc_first = p_tx_next_desc_curr;
  2466. FIRST_TFD_SET (p_tx_desc_first, tx_queue);
  2467. } else {
  2468. p_tx_desc_curr->cmd_sts = command_status;
  2469. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
  2470. }
  2471. /* Check for ring index overlap in the Tx desc ring */
  2472. if (p_tx_next_desc_curr == p_tx_desc_used) {
  2473. /* Update the current descriptor */
  2474. CURR_TFD_SET (p_tx_desc_first, tx_queue);
  2475. p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
  2476. return ETH_QUEUE_LAST_RESOURCE;
  2477. } else {
  2478. /* Update the current descriptor */
  2479. CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
  2480. return ETH_OK;
  2481. }
  2482. }
  2483. /*******************************************************************************
  2484. * eth_tx_return_desc - Free all used Tx descriptors
  2485. *
  2486. * DESCRIPTION:
  2487. * This routine returns the transmitted packet information to the caller.
  2488. * It uses the 'first' index to support Tx desc return in case a transmit
  2489. * of a packet spanned over multiple buffer still in process.
  2490. * In case the Tx queue was in "resource error" condition, where there are
  2491. * no available Tx resources, the function resets the resource error flag.
  2492. *
  2493. * INPUT:
  2494. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2495. * ETH_QUEUE tx_queue Number of Tx queue.
  2496. * PKT_INFO *p_pkt_info User packet buffer.
  2497. *
  2498. * OUTPUT:
  2499. * Tx ring 'first' and 'used' indexes are updated.
  2500. *
  2501. * RETURN:
  2502. * ETH_ERROR in case the routine can not access Tx desc ring.
  2503. * ETH_RETRY in case there is transmission in process.
  2504. * ETH_END_OF_JOB if the routine has nothing to release.
  2505. * ETH_OK otherwise.
  2506. *
  2507. *******************************************************************************/
  2508. static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
  2509. p_eth_port_ctrl,
  2510. ETH_QUEUE tx_queue,
  2511. PKT_INFO * p_pkt_info)
  2512. {
  2513. volatile ETH_TX_DESC *p_tx_desc_used = NULL;
  2514. volatile ETH_TX_DESC *p_tx_desc_first = NULL;
  2515. unsigned int command_status;
  2516. /* Get the Tx Desc ring indexes */
  2517. USED_TFD_GET (p_tx_desc_used, tx_queue);
  2518. FIRST_TFD_GET (p_tx_desc_first, tx_queue);
  2519. /* Sanity check */
  2520. if (p_tx_desc_used == NULL)
  2521. return ETH_ERROR;
  2522. command_status = p_tx_desc_used->cmd_sts;
  2523. /* Still transmitting... */
  2524. if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
  2525. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
  2526. return ETH_RETRY;
  2527. }
  2528. /* Stop release. About to overlap the current available Tx descriptor */
  2529. if ((p_tx_desc_used == p_tx_desc_first) &&
  2530. (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
  2531. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
  2532. return ETH_END_OF_JOB;
  2533. }
  2534. /* Pass the packet information to the caller */
  2535. p_pkt_info->cmd_sts = command_status;
  2536. p_pkt_info->return_info = p_tx_desc_used->return_info;
  2537. p_tx_desc_used->return_info = 0;
  2538. /* Update the next descriptor to release. */
  2539. USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
  2540. /* Any Tx return cancels the Tx resource error status */
  2541. if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
  2542. p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
  2543. D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
  2544. return ETH_OK;
  2545. }
  2546. /*******************************************************************************
  2547. * eth_port_receive - Get received information from Rx ring.
  2548. *
  2549. * DESCRIPTION:
  2550. * This routine returns the received data to the caller. There is no
  2551. * data copying during routine operation. All information is returned
  2552. * using pointer to packet information struct passed from the caller.
  2553. * If the routine exhausts Rx ring resources then the resource error flag
  2554. * is set.
  2555. *
  2556. * INPUT:
  2557. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2558. * ETH_QUEUE rx_queue Number of Rx queue.
  2559. * PKT_INFO *p_pkt_info User packet buffer.
  2560. *
  2561. * OUTPUT:
  2562. * Rx ring current and used indexes are updated.
  2563. *
  2564. * RETURN:
  2565. * ETH_ERROR in case the routine can not access Rx desc ring.
  2566. * ETH_QUEUE_FULL if Rx ring resources are exhausted.
  2567. * ETH_END_OF_JOB if there is no received data.
  2568. * ETH_OK otherwise.
  2569. *
  2570. *******************************************************************************/
  2571. static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
  2572. ETH_QUEUE rx_queue,
  2573. PKT_INFO * p_pkt_info)
  2574. {
  2575. volatile ETH_RX_DESC *p_rx_curr_desc;
  2576. volatile ETH_RX_DESC *p_rx_next_curr_desc;
  2577. volatile ETH_RX_DESC *p_rx_used_desc;
  2578. unsigned int command_status;
  2579. /* Do not process Rx ring in case of Rx ring resource error */
  2580. if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
  2581. printf ("\nRx Queue is full ...\n");
  2582. return ETH_QUEUE_FULL;
  2583. }
  2584. /* Get the Rx Desc ring 'curr and 'used' indexes */
  2585. CURR_RFD_GET (p_rx_curr_desc, rx_queue);
  2586. USED_RFD_GET (p_rx_used_desc, rx_queue);
  2587. /* Sanity check */
  2588. if (p_rx_curr_desc == NULL)
  2589. return ETH_ERROR;
  2590. /* The following parameters are used to save readings from memory */
  2591. p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
  2592. command_status = p_rx_curr_desc->cmd_sts;
  2593. /* Nothing to receive... */
  2594. if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
  2595. /* DP(printf("Rx: command_status: %08x\n", command_status)); */
  2596. D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
  2597. /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
  2598. return ETH_END_OF_JOB;
  2599. }
  2600. p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
  2601. p_pkt_info->cmd_sts = command_status;
  2602. p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
  2603. p_pkt_info->return_info = p_rx_curr_desc->return_info;
  2604. p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
  2605. /* Clean the return info field to indicate that the packet has been */
  2606. /* moved to the upper layers */
  2607. p_rx_curr_desc->return_info = 0;
  2608. /* Update 'curr' in data structure */
  2609. CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
  2610. /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
  2611. if (p_rx_next_curr_desc == p_rx_used_desc)
  2612. p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
  2613. D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
  2614. CPU_PIPE_FLUSH;
  2615. return ETH_OK;
  2616. }
  2617. /*******************************************************************************
  2618. * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
  2619. *
  2620. * DESCRIPTION:
  2621. * This routine returns a Rx buffer back to the Rx ring. It retrieves the
  2622. * next 'used' descriptor and attached the returned buffer to it.
  2623. * In case the Rx ring was in "resource error" condition, where there are
  2624. * no available Rx resources, the function resets the resource error flag.
  2625. *
  2626. * INPUT:
  2627. * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
  2628. * ETH_QUEUE rx_queue Number of Rx queue.
  2629. * PKT_INFO *p_pkt_info Information on the returned buffer.
  2630. *
  2631. * OUTPUT:
  2632. * New available Rx resource in Rx descriptor ring.
  2633. *
  2634. * RETURN:
  2635. * ETH_ERROR in case the routine can not access Rx desc ring.
  2636. * ETH_OK otherwise.
  2637. *
  2638. *******************************************************************************/
  2639. static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
  2640. p_eth_port_ctrl,
  2641. ETH_QUEUE rx_queue,
  2642. PKT_INFO * p_pkt_info)
  2643. {
  2644. volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
  2645. /* Get 'used' Rx descriptor */
  2646. USED_RFD_GET (p_used_rx_desc, rx_queue);
  2647. /* Sanity check */
  2648. if (p_used_rx_desc == NULL)
  2649. return ETH_ERROR;
  2650. p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
  2651. p_used_rx_desc->return_info = p_pkt_info->return_info;
  2652. p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
  2653. p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */
  2654. /* Flush the write pipe */
  2655. CPU_PIPE_FLUSH;
  2656. /* Return the descriptor to DMA ownership */
  2657. p_used_rx_desc->cmd_sts =
  2658. ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
  2659. /* Flush descriptor and CPU pipe */
  2660. D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
  2661. CPU_PIPE_FLUSH;
  2662. /* Move the used descriptor pointer to the next descriptor */
  2663. USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
  2664. /* Any Rx return cancels the Rx resource error status */
  2665. if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
  2666. p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
  2667. return ETH_OK;
  2668. }
  2669. /*******************************************************************************
  2670. * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
  2671. *
  2672. * DESCRIPTION:
  2673. * This routine sets the RX coalescing interrupt mechanism parameter.
  2674. * This parameter is a timeout counter, that counts in 64 t_clk
  2675. * chunks ; that when timeout event occurs a maskable interrupt
  2676. * occurs.
  2677. * The parameter is calculated using the tClk of the MV-643xx chip
  2678. * , and the required delay of the interrupt in usec.
  2679. *
  2680. * INPUT:
  2681. * ETH_PORT eth_port_num Ethernet port number
  2682. * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
  2683. * unsigned int delay Delay in usec
  2684. *
  2685. * OUTPUT:
  2686. * Interrupt coalescing mechanism value is set in MV-643xx chip.
  2687. *
  2688. * RETURN:
  2689. * The interrupt coalescing value set in the gigE port.
  2690. *
  2691. *******************************************************************************/
  2692. #if 0 /* FIXME */
  2693. static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
  2694. unsigned int t_clk,
  2695. unsigned int delay)
  2696. {
  2697. unsigned int coal;
  2698. coal = ((t_clk / 1000000) * delay) / 64;
  2699. /* Set RX Coalescing mechanism */
  2700. MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
  2701. ((coal & 0x3fff) << 8) |
  2702. (MV_REG_READ
  2703. (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
  2704. & 0xffc000ff));
  2705. return coal;
  2706. }
  2707. #endif
  2708. /*******************************************************************************
  2709. * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
  2710. *
  2711. * DESCRIPTION:
  2712. * This routine sets the TX coalescing interrupt mechanism parameter.
  2713. * This parameter is a timeout counter, that counts in 64 t_clk
  2714. * chunks ; that when timeout event occurs a maskable interrupt
  2715. * occurs.
  2716. * The parameter is calculated using the t_cLK frequency of the
  2717. * MV-643xx chip and the required delay in the interrupt in uSec
  2718. *
  2719. * INPUT:
  2720. * ETH_PORT eth_port_num Ethernet port number
  2721. * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
  2722. * unsigned int delay Delay in uSeconds
  2723. *
  2724. * OUTPUT:
  2725. * Interrupt coalescing mechanism value is set in MV-643xx chip.
  2726. *
  2727. * RETURN:
  2728. * The interrupt coalescing value set in the gigE port.
  2729. *
  2730. *******************************************************************************/
  2731. #if 0 /* FIXME */
  2732. static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
  2733. unsigned int t_clk,
  2734. unsigned int delay)
  2735. {
  2736. unsigned int coal;
  2737. coal = ((t_clk / 1000000) * delay) / 64;
  2738. /* Set TX Coalescing mechanism */
  2739. MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
  2740. coal << 4);
  2741. return coal;
  2742. }
  2743. #endif
  2744. /*******************************************************************************
  2745. * eth_b_copy - Copy bytes from source to destination
  2746. *
  2747. * DESCRIPTION:
  2748. * This function supports the eight bytes limitation on Tx buffer size.
  2749. * The routine will zero eight bytes starting from the destination address
  2750. * followed by copying bytes from the source address to the destination.
  2751. *
  2752. * INPUT:
  2753. * unsigned int src_addr 32 bit source address.
  2754. * unsigned int dst_addr 32 bit destination address.
  2755. * int byte_count Number of bytes to copy.
  2756. *
  2757. * OUTPUT:
  2758. * See description.
  2759. *
  2760. * RETURN:
  2761. * None.
  2762. *
  2763. *******************************************************************************/
  2764. static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
  2765. int byte_count)
  2766. {
  2767. /* Zero the dst_addr area */
  2768. *(unsigned int *) dst_addr = 0x0;
  2769. while (byte_count != 0) {
  2770. *(char *) dst_addr = *(char *) src_addr;
  2771. dst_addr++;
  2772. src_addr++;
  2773. byte_count--;
  2774. }
  2775. }