xhci.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * USB HOST XHCI Controller stack
  4. *
  5. * Based on xHCI host controller driver in linux-kernel
  6. * by Sarah Sharp.
  7. *
  8. * Copyright (C) 2008 Intel Corp.
  9. * Author: Sarah Sharp
  10. *
  11. * Copyright (C) 2013 Samsung Electronics Co.Ltd
  12. * Authors: Vivek Gautam <gautam.vivek@samsung.com>
  13. * Vikas Sajjan <vikas.sajjan@samsung.com>
  14. */
  15. /**
  16. * This file gives the xhci stack for usb3.0 looking into
  17. * xhci specification Rev1.0 (5/21/10).
  18. * The quirk devices support hasn't been given yet.
  19. */
  20. #include <common.h>
  21. #include <cpu_func.h>
  22. #include <dm.h>
  23. #include <log.h>
  24. #include <asm/byteorder.h>
  25. #include <usb.h>
  26. #include <malloc.h>
  27. #include <watchdog.h>
  28. #include <asm/cache.h>
  29. #include <asm/unaligned.h>
  30. #include <linux/bug.h>
  31. #include <linux/errno.h>
  32. #include <usb/xhci.h>
  33. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  34. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  35. #endif
  36. static struct descriptor {
  37. struct usb_hub_descriptor hub;
  38. struct usb_device_descriptor device;
  39. struct usb_config_descriptor config;
  40. struct usb_interface_descriptor interface;
  41. struct usb_endpoint_descriptor endpoint;
  42. struct usb_ss_ep_comp_descriptor ep_companion;
  43. } __attribute__ ((packed)) descriptor = {
  44. {
  45. 0xc, /* bDescLength */
  46. 0x2a, /* bDescriptorType: hub descriptor */
  47. 2, /* bNrPorts -- runtime modified */
  48. cpu_to_le16(0x8), /* wHubCharacteristics */
  49. 10, /* bPwrOn2PwrGood */
  50. 0, /* bHubCntrCurrent */
  51. { /* Device removable */
  52. } /* at most 7 ports! XXX */
  53. },
  54. {
  55. 0x12, /* bLength */
  56. 1, /* bDescriptorType: UDESC_DEVICE */
  57. cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
  58. 9, /* bDeviceClass: UDCLASS_HUB */
  59. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  60. 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
  61. 9, /* bMaxPacketSize: 512 bytes 2^9 */
  62. 0x0000, /* idVendor */
  63. 0x0000, /* idProduct */
  64. cpu_to_le16(0x0100), /* bcdDevice */
  65. 1, /* iManufacturer */
  66. 2, /* iProduct */
  67. 0, /* iSerialNumber */
  68. 1 /* bNumConfigurations: 1 */
  69. },
  70. {
  71. 0x9,
  72. 2, /* bDescriptorType: UDESC_CONFIG */
  73. cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
  74. 1, /* bNumInterface */
  75. 1, /* bConfigurationValue */
  76. 0, /* iConfiguration */
  77. 0x40, /* bmAttributes: UC_SELF_POWER */
  78. 0 /* bMaxPower */
  79. },
  80. {
  81. 0x9, /* bLength */
  82. 4, /* bDescriptorType: UDESC_INTERFACE */
  83. 0, /* bInterfaceNumber */
  84. 0, /* bAlternateSetting */
  85. 1, /* bNumEndpoints */
  86. 9, /* bInterfaceClass: UICLASS_HUB */
  87. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  88. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  89. 0 /* iInterface */
  90. },
  91. {
  92. 0x7, /* bLength */
  93. 5, /* bDescriptorType: UDESC_ENDPOINT */
  94. 0x81, /* bEndpointAddress: IN endpoint 1 */
  95. 3, /* bmAttributes: UE_INTERRUPT */
  96. 8, /* wMaxPacketSize */
  97. 255 /* bInterval */
  98. },
  99. {
  100. 0x06, /* ss_bLength */
  101. 0x30, /* ss_bDescriptorType: SS EP Companion */
  102. 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
  103. /* ss_bmAttributes: 1 packet per service interval */
  104. 0x00,
  105. /* ss_wBytesPerInterval: 15 bits for max 15 ports */
  106. cpu_to_le16(0x02),
  107. },
  108. };
  109. #if !CONFIG_IS_ENABLED(DM_USB)
  110. static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
  111. #endif
  112. struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
  113. {
  114. #if CONFIG_IS_ENABLED(DM_USB)
  115. struct udevice *dev;
  116. /* Find the USB controller */
  117. for (dev = udev->dev;
  118. device_get_uclass_id(dev) != UCLASS_USB;
  119. dev = dev->parent)
  120. ;
  121. return dev_get_priv(dev);
  122. #else
  123. return udev->controller;
  124. #endif
  125. }
  126. /**
  127. * Waits for as per specified amount of time
  128. * for the "result" to match with "done"
  129. *
  130. * @param ptr pointer to the register to be read
  131. * @param mask mask for the value read
  132. * @param done value to be campared with result
  133. * @param usec time to wait till
  134. * @return 0 if handshake is success else < 0 on failure
  135. */
  136. static int handshake(uint32_t volatile *ptr, uint32_t mask,
  137. uint32_t done, int usec)
  138. {
  139. uint32_t result;
  140. do {
  141. result = xhci_readl(ptr);
  142. if (result == ~(uint32_t)0)
  143. return -ENODEV;
  144. result &= mask;
  145. if (result == done)
  146. return 0;
  147. usec--;
  148. udelay(1);
  149. } while (usec > 0);
  150. return -ETIMEDOUT;
  151. }
  152. /**
  153. * Set the run bit and wait for the host to be running.
  154. *
  155. * @param hcor pointer to host controller operation registers
  156. * @return status of the Handshake
  157. */
  158. static int xhci_start(struct xhci_hcor *hcor)
  159. {
  160. u32 temp;
  161. int ret;
  162. puts("Starting the controller\n");
  163. temp = xhci_readl(&hcor->or_usbcmd);
  164. temp |= (CMD_RUN);
  165. xhci_writel(&hcor->or_usbcmd, temp);
  166. /*
  167. * Wait for the HCHalted Status bit to be 0 to indicate the host is
  168. * running.
  169. */
  170. ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
  171. if (ret)
  172. debug("Host took too long to start, "
  173. "waited %u microseconds.\n",
  174. XHCI_MAX_HALT_USEC);
  175. return ret;
  176. }
  177. /**
  178. * Resets the XHCI Controller
  179. *
  180. * @param hcor pointer to host controller operation registers
  181. * @return -EBUSY if XHCI Controller is not halted else status of handshake
  182. */
  183. static int xhci_reset(struct xhci_hcor *hcor)
  184. {
  185. u32 cmd;
  186. u32 state;
  187. int ret;
  188. /* Halting the Host first */
  189. debug("// Halt the HC: %p\n", hcor);
  190. state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
  191. if (!state) {
  192. cmd = xhci_readl(&hcor->or_usbcmd);
  193. cmd &= ~CMD_RUN;
  194. xhci_writel(&hcor->or_usbcmd, cmd);
  195. }
  196. ret = handshake(&hcor->or_usbsts,
  197. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  198. if (ret) {
  199. printf("Host not halted after %u microseconds.\n",
  200. XHCI_MAX_HALT_USEC);
  201. return -EBUSY;
  202. }
  203. debug("// Reset the HC\n");
  204. cmd = xhci_readl(&hcor->or_usbcmd);
  205. cmd |= CMD_RESET;
  206. xhci_writel(&hcor->or_usbcmd, cmd);
  207. ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
  208. if (ret)
  209. return ret;
  210. /*
  211. * xHCI cannot write to any doorbells or operational registers other
  212. * than status until the "Controller Not Ready" flag is cleared.
  213. */
  214. return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
  215. }
  216. /**
  217. * Used for passing endpoint bitmasks between the core and HCDs.
  218. * Find the index for an endpoint given its descriptor.
  219. * Use the return value to right shift 1 for the bitmask.
  220. *
  221. * Index = (epnum * 2) + direction - 1,
  222. * where direction = 0 for OUT, 1 for IN.
  223. * For control endpoints, the IN index is used (OUT index is unused), so
  224. * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
  225. *
  226. * @param desc USB enpdoint Descriptor
  227. * @return index of the Endpoint
  228. */
  229. static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
  230. {
  231. unsigned int index;
  232. if (usb_endpoint_xfer_control(desc))
  233. index = (unsigned int)(usb_endpoint_num(desc) * 2);
  234. else
  235. index = (unsigned int)((usb_endpoint_num(desc) * 2) -
  236. (usb_endpoint_dir_in(desc) ? 0 : 1));
  237. return index;
  238. }
  239. /*
  240. * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
  241. * microframes, rounded down to nearest power of 2.
  242. */
  243. static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval,
  244. unsigned int min_exponent,
  245. unsigned int max_exponent)
  246. {
  247. unsigned int interval;
  248. interval = fls(desc_interval) - 1;
  249. interval = clamp_val(interval, min_exponent, max_exponent);
  250. if ((1 << interval) != desc_interval)
  251. debug("rounding interval to %d microframes, "\
  252. "ep desc says %d microframes\n",
  253. 1 << interval, desc_interval);
  254. return interval;
  255. }
  256. static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
  257. struct usb_endpoint_descriptor *endpt_desc)
  258. {
  259. if (endpt_desc->bInterval == 0)
  260. return 0;
  261. return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15);
  262. }
  263. static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
  264. struct usb_endpoint_descriptor *endpt_desc)
  265. {
  266. return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10);
  267. }
  268. /*
  269. * Convert interval expressed as 2^(bInterval - 1) == interval into
  270. * straight exponent value 2^n == interval.
  271. */
  272. static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
  273. struct usb_endpoint_descriptor *endpt_desc)
  274. {
  275. unsigned int interval;
  276. interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1;
  277. if (interval != endpt_desc->bInterval - 1)
  278. debug("ep %#x - rounding interval to %d %sframes\n",
  279. endpt_desc->bEndpointAddress, 1 << interval,
  280. udev->speed == USB_SPEED_FULL ? "" : "micro");
  281. if (udev->speed == USB_SPEED_FULL) {
  282. /*
  283. * Full speed isoc endpoints specify interval in frames,
  284. * not microframes. We are using microframes everywhere,
  285. * so adjust accordingly.
  286. */
  287. interval += 3; /* 1 frame = 2^3 uframes */
  288. }
  289. return interval;
  290. }
  291. /*
  292. * Return the polling or NAK interval.
  293. *
  294. * The polling interval is expressed in "microframes". If xHCI's Interval field
  295. * is set to N, it will service the endpoint every 2^(Interval)*125us.
  296. *
  297. * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
  298. * is set to 0.
  299. */
  300. static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
  301. struct usb_endpoint_descriptor *endpt_desc)
  302. {
  303. unsigned int interval = 0;
  304. switch (udev->speed) {
  305. case USB_SPEED_HIGH:
  306. /* Max NAK rate */
  307. if (usb_endpoint_xfer_control(endpt_desc) ||
  308. usb_endpoint_xfer_bulk(endpt_desc)) {
  309. interval = xhci_parse_microframe_interval(udev,
  310. endpt_desc);
  311. break;
  312. }
  313. /* Fall through - SS and HS isoc/int have same decoding */
  314. case USB_SPEED_SUPER:
  315. if (usb_endpoint_xfer_int(endpt_desc) ||
  316. usb_endpoint_xfer_isoc(endpt_desc)) {
  317. interval = xhci_parse_exponent_interval(udev,
  318. endpt_desc);
  319. }
  320. break;
  321. case USB_SPEED_FULL:
  322. if (usb_endpoint_xfer_isoc(endpt_desc)) {
  323. interval = xhci_parse_exponent_interval(udev,
  324. endpt_desc);
  325. break;
  326. }
  327. /*
  328. * Fall through for interrupt endpoint interval decoding
  329. * since it uses the same rules as low speed interrupt
  330. * endpoints.
  331. */
  332. case USB_SPEED_LOW:
  333. if (usb_endpoint_xfer_int(endpt_desc) ||
  334. usb_endpoint_xfer_isoc(endpt_desc)) {
  335. interval = xhci_parse_frame_interval(udev, endpt_desc);
  336. }
  337. break;
  338. default:
  339. BUG();
  340. }
  341. return interval;
  342. }
  343. /*
  344. * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
  345. * High speed endpoint descriptors can define "the number of additional
  346. * transaction opportunities per microframe", but that goes in the Max Burst
  347. * endpoint context field.
  348. */
  349. static u32 xhci_get_endpoint_mult(struct usb_device *udev,
  350. struct usb_endpoint_descriptor *endpt_desc,
  351. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  352. {
  353. if (udev->speed < USB_SPEED_SUPER ||
  354. !usb_endpoint_xfer_isoc(endpt_desc))
  355. return 0;
  356. return ss_ep_comp_desc->bmAttributes;
  357. }
  358. static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
  359. struct usb_endpoint_descriptor *endpt_desc,
  360. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  361. {
  362. /* Super speed and Plus have max burst in ep companion desc */
  363. if (udev->speed >= USB_SPEED_SUPER)
  364. return ss_ep_comp_desc->bMaxBurst;
  365. if (udev->speed == USB_SPEED_HIGH &&
  366. (usb_endpoint_xfer_isoc(endpt_desc) ||
  367. usb_endpoint_xfer_int(endpt_desc)))
  368. return usb_endpoint_maxp_mult(endpt_desc) - 1;
  369. return 0;
  370. }
  371. /*
  372. * Return the maximum endpoint service interval time (ESIT) payload.
  373. * Basically, this is the maxpacket size, multiplied by the burst size
  374. * and mult size.
  375. */
  376. static u32 xhci_get_max_esit_payload(struct usb_device *udev,
  377. struct usb_endpoint_descriptor *endpt_desc,
  378. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  379. {
  380. int max_burst;
  381. int max_packet;
  382. /* Only applies for interrupt or isochronous endpoints */
  383. if (usb_endpoint_xfer_control(endpt_desc) ||
  384. usb_endpoint_xfer_bulk(endpt_desc))
  385. return 0;
  386. /* SuperSpeed Isoc ep with less than 48k per esit */
  387. if (udev->speed >= USB_SPEED_SUPER)
  388. return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval);
  389. max_packet = usb_endpoint_maxp(endpt_desc);
  390. max_burst = usb_endpoint_maxp_mult(endpt_desc);
  391. /* A 0 in max burst means 1 transfer per ESIT */
  392. return max_packet * max_burst;
  393. }
  394. /**
  395. * Issue a configure endpoint command or evaluate context command
  396. * and wait for it to finish.
  397. *
  398. * @param udev pointer to the Device Data Structure
  399. * @param ctx_change flag to indicate the Context has changed or NOT
  400. * @return 0 on success, -1 on failure
  401. */
  402. static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
  403. {
  404. struct xhci_container_ctx *in_ctx;
  405. struct xhci_virt_device *virt_dev;
  406. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  407. union xhci_trb *event;
  408. virt_dev = ctrl->devs[udev->slot_id];
  409. in_ctx = virt_dev->in_ctx;
  410. xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
  411. xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
  412. ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
  413. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  414. BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
  415. != udev->slot_id);
  416. switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
  417. case COMP_SUCCESS:
  418. debug("Successful %s command\n",
  419. ctx_change ? "Evaluate Context" : "Configure Endpoint");
  420. break;
  421. default:
  422. printf("ERROR: %s command returned completion code %d.\n",
  423. ctx_change ? "Evaluate Context" : "Configure Endpoint",
  424. GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
  425. return -EINVAL;
  426. }
  427. xhci_acknowledge_event(ctrl);
  428. return 0;
  429. }
  430. /**
  431. * Configure the endpoint, programming the device contexts.
  432. *
  433. * @param udev pointer to the USB device structure
  434. * @return returns the status of the xhci_configure_endpoints
  435. */
  436. static int xhci_set_configuration(struct usb_device *udev)
  437. {
  438. struct xhci_container_ctx *in_ctx;
  439. struct xhci_container_ctx *out_ctx;
  440. struct xhci_input_control_ctx *ctrl_ctx;
  441. struct xhci_slot_ctx *slot_ctx;
  442. struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
  443. int cur_ep;
  444. int max_ep_flag = 0;
  445. int ep_index;
  446. unsigned int dir;
  447. unsigned int ep_type;
  448. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  449. int num_of_ep;
  450. int ep_flag = 0;
  451. u64 trb_64 = 0;
  452. int slot_id = udev->slot_id;
  453. struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
  454. struct usb_interface *ifdesc;
  455. u32 max_esit_payload;
  456. unsigned int interval;
  457. unsigned int mult;
  458. unsigned int max_burst;
  459. unsigned int avg_trb_len;
  460. unsigned int err_count = 0;
  461. out_ctx = virt_dev->out_ctx;
  462. in_ctx = virt_dev->in_ctx;
  463. num_of_ep = udev->config.if_desc[0].no_of_ep;
  464. ifdesc = &udev->config.if_desc[0];
  465. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  466. /* Initialize the input context control */
  467. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  468. ctrl_ctx->drop_flags = 0;
  469. /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
  470. for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
  471. ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
  472. ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
  473. if (max_ep_flag < ep_flag)
  474. max_ep_flag = ep_flag;
  475. }
  476. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  477. /* slot context */
  478. xhci_slot_copy(ctrl, in_ctx, out_ctx);
  479. slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  480. slot_ctx->dev_info &= ~(cpu_to_le32(LAST_CTX_MASK));
  481. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
  482. xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
  483. /* filling up ep contexts */
  484. for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
  485. struct usb_endpoint_descriptor *endpt_desc = NULL;
  486. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL;
  487. endpt_desc = &ifdesc->ep_desc[cur_ep];
  488. ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep];
  489. trb_64 = 0;
  490. /*
  491. * Get values to fill the endpoint context, mostly from ep
  492. * descriptor. The average TRB buffer lengt for bulk endpoints
  493. * is unclear as we have no clue on scatter gather list entry
  494. * size. For Isoc and Int, set it to max available.
  495. * See xHCI 1.1 spec 4.14.1.1 for details.
  496. */
  497. max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc,
  498. ss_ep_comp_desc);
  499. interval = xhci_get_endpoint_interval(udev, endpt_desc);
  500. mult = xhci_get_endpoint_mult(udev, endpt_desc,
  501. ss_ep_comp_desc);
  502. max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc,
  503. ss_ep_comp_desc);
  504. avg_trb_len = max_esit_payload;
  505. ep_index = xhci_get_ep_index(endpt_desc);
  506. ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  507. /* Allocate the ep rings */
  508. virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
  509. if (!virt_dev->eps[ep_index].ring)
  510. return -ENOMEM;
  511. /*NOTE: ep_desc[0] actually represents EP1 and so on */
  512. dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
  513. ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
  514. ep_ctx[ep_index]->ep_info =
  515. cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
  516. EP_INTERVAL(interval) | EP_MULT(mult));
  517. ep_ctx[ep_index]->ep_info2 =
  518. cpu_to_le32(ep_type << EP_TYPE_SHIFT);
  519. ep_ctx[ep_index]->ep_info2 |=
  520. cpu_to_le32(MAX_PACKET
  521. (get_unaligned(&endpt_desc->wMaxPacketSize)));
  522. /* Allow 3 retries for everything but isoc, set CErr = 3 */
  523. if (!usb_endpoint_xfer_isoc(endpt_desc))
  524. err_count = 3;
  525. ep_ctx[ep_index]->ep_info2 |=
  526. cpu_to_le32(MAX_BURST(max_burst) |
  527. ERROR_COUNT(err_count));
  528. trb_64 = (uintptr_t)
  529. virt_dev->eps[ep_index].ring->enqueue;
  530. ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
  531. virt_dev->eps[ep_index].ring->cycle_state);
  532. /*
  533. * xHCI spec 6.2.3:
  534. * 'Average TRB Length' should be 8 for control endpoints.
  535. */
  536. if (usb_endpoint_xfer_control(endpt_desc))
  537. avg_trb_len = 8;
  538. ep_ctx[ep_index]->tx_info =
  539. cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
  540. EP_AVG_TRB_LENGTH(avg_trb_len));
  541. /*
  542. * The MediaTek xHCI defines some extra SW parameters which
  543. * are put into reserved DWs in Slot and Endpoint Contexts
  544. * for synchronous endpoints.
  545. */
  546. if (IS_ENABLED(CONFIG_USB_XHCI_MTK)) {
  547. ep_ctx[ep_index]->reserved[0] =
  548. cpu_to_le32(EP_BPKTS(1) | EP_BBM(1));
  549. }
  550. }
  551. return xhci_configure_endpoints(udev, false);
  552. }
  553. /**
  554. * Issue an Address Device command (which will issue a SetAddress request to
  555. * the device).
  556. *
  557. * @param udev pointer to the Device Data Structure
  558. * @return 0 if successful else error code on failure
  559. */
  560. static int xhci_address_device(struct usb_device *udev, int root_portnr)
  561. {
  562. int ret = 0;
  563. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  564. struct xhci_slot_ctx *slot_ctx;
  565. struct xhci_input_control_ctx *ctrl_ctx;
  566. struct xhci_virt_device *virt_dev;
  567. int slot_id = udev->slot_id;
  568. union xhci_trb *event;
  569. virt_dev = ctrl->devs[slot_id];
  570. /*
  571. * This is the first Set Address since device plug-in
  572. * so setting up the slot context.
  573. */
  574. debug("Setting up addressable devices %p\n", ctrl->dcbaa);
  575. xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
  576. ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
  577. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
  578. ctrl_ctx->drop_flags = 0;
  579. xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
  580. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  581. BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
  582. switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
  583. case COMP_CTX_STATE:
  584. case COMP_EBADSLT:
  585. printf("Setup ERROR: address device command for slot %d.\n",
  586. slot_id);
  587. ret = -EINVAL;
  588. break;
  589. case COMP_TX_ERR:
  590. puts("Device not responding to set address.\n");
  591. ret = -EPROTO;
  592. break;
  593. case COMP_DEV_ERR:
  594. puts("ERROR: Incompatible device"
  595. "for address device command.\n");
  596. ret = -ENODEV;
  597. break;
  598. case COMP_SUCCESS:
  599. debug("Successful Address Device command\n");
  600. udev->status = 0;
  601. break;
  602. default:
  603. printf("ERROR: unexpected command completion code 0x%x.\n",
  604. GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
  605. ret = -EINVAL;
  606. break;
  607. }
  608. xhci_acknowledge_event(ctrl);
  609. if (ret < 0)
  610. /*
  611. * TODO: Unsuccessful Address Device command shall leave the
  612. * slot in default state. So, issue Disable Slot command now.
  613. */
  614. return ret;
  615. xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
  616. virt_dev->out_ctx->size);
  617. slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
  618. debug("xHC internal address is: %d\n",
  619. le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
  620. return 0;
  621. }
  622. /**
  623. * Issue Enable slot command to the controller to allocate
  624. * device slot and assign the slot id. It fails if the xHC
  625. * ran out of device slots, the Enable Slot command timed out,
  626. * or allocating memory failed.
  627. *
  628. * @param udev pointer to the Device Data Structure
  629. * @return Returns 0 on succes else return error code on failure
  630. */
  631. static int _xhci_alloc_device(struct usb_device *udev)
  632. {
  633. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  634. union xhci_trb *event;
  635. int ret;
  636. /*
  637. * Root hub will be first device to be initailized.
  638. * If this device is root-hub, don't do any xHC related
  639. * stuff.
  640. */
  641. if (ctrl->rootdev == 0) {
  642. udev->speed = USB_SPEED_SUPER;
  643. return 0;
  644. }
  645. xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
  646. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  647. BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
  648. != COMP_SUCCESS);
  649. udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
  650. xhci_acknowledge_event(ctrl);
  651. ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
  652. if (ret < 0) {
  653. /*
  654. * TODO: Unsuccessful Address Device command shall leave
  655. * the slot in default. So, issue Disable Slot command now.
  656. */
  657. puts("Could not allocate xHCI USB device data structures\n");
  658. return ret;
  659. }
  660. return 0;
  661. }
  662. #if !CONFIG_IS_ENABLED(DM_USB)
  663. int usb_alloc_device(struct usb_device *udev)
  664. {
  665. return _xhci_alloc_device(udev);
  666. }
  667. #endif
  668. /*
  669. * Full speed devices may have a max packet size greater than 8 bytes, but the
  670. * USB core doesn't know that until it reads the first 8 bytes of the
  671. * descriptor. If the usb_device's max packet size changes after that point,
  672. * we need to issue an evaluate context command and wait on it.
  673. *
  674. * @param udev pointer to the Device Data Structure
  675. * @return returns the status of the xhci_configure_endpoints
  676. */
  677. int xhci_check_maxpacket(struct usb_device *udev)
  678. {
  679. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  680. unsigned int slot_id = udev->slot_id;
  681. int ep_index = 0; /* control endpoint */
  682. struct xhci_container_ctx *in_ctx;
  683. struct xhci_container_ctx *out_ctx;
  684. struct xhci_input_control_ctx *ctrl_ctx;
  685. struct xhci_ep_ctx *ep_ctx;
  686. int max_packet_size;
  687. int hw_max_packet_size;
  688. int ret = 0;
  689. out_ctx = ctrl->devs[slot_id]->out_ctx;
  690. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  691. ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
  692. hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
  693. max_packet_size = udev->epmaxpacketin[0];
  694. if (hw_max_packet_size != max_packet_size) {
  695. debug("Max Packet Size for ep 0 changed.\n");
  696. debug("Max packet size in usb_device = %d\n", max_packet_size);
  697. debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
  698. debug("Issuing evaluate context command.\n");
  699. /* Set up the modified control endpoint 0 */
  700. xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
  701. ctrl->devs[slot_id]->out_ctx, ep_index);
  702. in_ctx = ctrl->devs[slot_id]->in_ctx;
  703. ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  704. ep_ctx->ep_info2 &= cpu_to_le32(~((0xffff & MAX_PACKET_MASK)
  705. << MAX_PACKET_SHIFT));
  706. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
  707. /*
  708. * Set up the input context flags for the command
  709. * FIXME: This won't work if a non-default control endpoint
  710. * changes max packet sizes.
  711. */
  712. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  713. ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
  714. ctrl_ctx->drop_flags = 0;
  715. ret = xhci_configure_endpoints(udev, true);
  716. }
  717. return ret;
  718. }
  719. /**
  720. * Clears the Change bits of the Port Status Register
  721. *
  722. * @param wValue request value
  723. * @param wIndex request index
  724. * @param addr address of posrt status register
  725. * @param port_status state of port status register
  726. * @return none
  727. */
  728. static void xhci_clear_port_change_bit(u16 wValue,
  729. u16 wIndex, volatile uint32_t *addr, u32 port_status)
  730. {
  731. char *port_change_bit;
  732. u32 status;
  733. switch (wValue) {
  734. case USB_PORT_FEAT_C_RESET:
  735. status = PORT_RC;
  736. port_change_bit = "reset";
  737. break;
  738. case USB_PORT_FEAT_C_CONNECTION:
  739. status = PORT_CSC;
  740. port_change_bit = "connect";
  741. break;
  742. case USB_PORT_FEAT_C_OVER_CURRENT:
  743. status = PORT_OCC;
  744. port_change_bit = "over-current";
  745. break;
  746. case USB_PORT_FEAT_C_ENABLE:
  747. status = PORT_PEC;
  748. port_change_bit = "enable/disable";
  749. break;
  750. case USB_PORT_FEAT_C_SUSPEND:
  751. status = PORT_PLC;
  752. port_change_bit = "suspend/resume";
  753. break;
  754. default:
  755. /* Should never happen */
  756. return;
  757. }
  758. /* Change bits are all write 1 to clear */
  759. xhci_writel(addr, port_status | status);
  760. port_status = xhci_readl(addr);
  761. debug("clear port %s change, actual port %d status = 0x%x\n",
  762. port_change_bit, wIndex, port_status);
  763. }
  764. /**
  765. * Save Read Only (RO) bits and save read/write bits where
  766. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  767. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  768. *
  769. * @param state state of the Port Status and Control Regsiter
  770. * @return a value that would result in the port being in the
  771. * same state, if the value was written to the port
  772. * status control register.
  773. */
  774. static u32 xhci_port_state_to_neutral(u32 state)
  775. {
  776. /* Save read-only status and port state */
  777. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  778. }
  779. /**
  780. * Submits the Requests to the XHCI Host Controller
  781. *
  782. * @param udev pointer to the USB device structure
  783. * @param pipe contains the DIR_IN or OUT , devnum
  784. * @param buffer buffer to be read/written based on the request
  785. * @return returns 0 if successful else -1 on failure
  786. */
  787. static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
  788. void *buffer, struct devrequest *req)
  789. {
  790. uint8_t tmpbuf[4];
  791. u16 typeReq;
  792. void *srcptr = NULL;
  793. int len, srclen;
  794. uint32_t reg;
  795. volatile uint32_t *status_reg;
  796. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  797. struct xhci_hccr *hccr = ctrl->hccr;
  798. struct xhci_hcor *hcor = ctrl->hcor;
  799. int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
  800. if ((req->requesttype & USB_RT_PORT) &&
  801. le16_to_cpu(req->index) > max_ports) {
  802. printf("The request port(%d) exceeds maximum port number\n",
  803. le16_to_cpu(req->index) - 1);
  804. return -EINVAL;
  805. }
  806. status_reg = (volatile uint32_t *)
  807. (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
  808. srclen = 0;
  809. typeReq = req->request | req->requesttype << 8;
  810. switch (typeReq) {
  811. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  812. switch (le16_to_cpu(req->value) >> 8) {
  813. case USB_DT_DEVICE:
  814. debug("USB_DT_DEVICE request\n");
  815. srcptr = &descriptor.device;
  816. srclen = 0x12;
  817. break;
  818. case USB_DT_CONFIG:
  819. debug("USB_DT_CONFIG config\n");
  820. srcptr = &descriptor.config;
  821. srclen = 0x19;
  822. break;
  823. case USB_DT_STRING:
  824. debug("USB_DT_STRING config\n");
  825. switch (le16_to_cpu(req->value) & 0xff) {
  826. case 0: /* Language */
  827. srcptr = "\4\3\11\4";
  828. srclen = 4;
  829. break;
  830. case 1: /* Vendor String */
  831. srcptr = "\16\3U\0-\0B\0o\0o\0t\0";
  832. srclen = 14;
  833. break;
  834. case 2: /* Product Name */
  835. srcptr = "\52\3X\0H\0C\0I\0 "
  836. "\0H\0o\0s\0t\0 "
  837. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  838. srclen = 42;
  839. break;
  840. default:
  841. printf("unknown value DT_STRING %x\n",
  842. le16_to_cpu(req->value));
  843. goto unknown;
  844. }
  845. break;
  846. default:
  847. printf("unknown value %x\n", le16_to_cpu(req->value));
  848. goto unknown;
  849. }
  850. break;
  851. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  852. switch (le16_to_cpu(req->value) >> 8) {
  853. case USB_DT_HUB:
  854. case USB_DT_SS_HUB:
  855. debug("USB_DT_HUB config\n");
  856. srcptr = &descriptor.hub;
  857. srclen = 0x8;
  858. break;
  859. default:
  860. printf("unknown value %x\n", le16_to_cpu(req->value));
  861. goto unknown;
  862. }
  863. break;
  864. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  865. debug("USB_REQ_SET_ADDRESS\n");
  866. ctrl->rootdev = le16_to_cpu(req->value);
  867. break;
  868. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  869. /* Do nothing */
  870. break;
  871. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  872. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  873. tmpbuf[1] = 0;
  874. srcptr = tmpbuf;
  875. srclen = 2;
  876. break;
  877. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  878. memset(tmpbuf, 0, 4);
  879. reg = xhci_readl(status_reg);
  880. if (reg & PORT_CONNECT) {
  881. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  882. switch (reg & DEV_SPEED_MASK) {
  883. case XDEV_FS:
  884. debug("SPEED = FULLSPEED\n");
  885. break;
  886. case XDEV_LS:
  887. debug("SPEED = LOWSPEED\n");
  888. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  889. break;
  890. case XDEV_HS:
  891. debug("SPEED = HIGHSPEED\n");
  892. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  893. break;
  894. case XDEV_SS:
  895. debug("SPEED = SUPERSPEED\n");
  896. tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
  897. break;
  898. }
  899. }
  900. if (reg & PORT_PE)
  901. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  902. if ((reg & PORT_PLS_MASK) == XDEV_U3)
  903. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  904. if (reg & PORT_OC)
  905. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  906. if (reg & PORT_RESET)
  907. tmpbuf[0] |= USB_PORT_STAT_RESET;
  908. if (reg & PORT_POWER)
  909. /*
  910. * XXX: This Port power bit (for USB 3.0 hub)
  911. * we are faking in USB 2.0 hub port status;
  912. * since there's a change in bit positions in
  913. * two:
  914. * USB 2.0 port status PP is at position[8]
  915. * USB 3.0 port status PP is at position[9]
  916. * So, we are still keeping it at position [8]
  917. */
  918. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  919. if (reg & PORT_CSC)
  920. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  921. if (reg & PORT_PEC)
  922. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  923. if (reg & PORT_OCC)
  924. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  925. if (reg & PORT_RC)
  926. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  927. srcptr = tmpbuf;
  928. srclen = 4;
  929. break;
  930. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  931. reg = xhci_readl(status_reg);
  932. reg = xhci_port_state_to_neutral(reg);
  933. switch (le16_to_cpu(req->value)) {
  934. case USB_PORT_FEAT_ENABLE:
  935. reg |= PORT_PE;
  936. xhci_writel(status_reg, reg);
  937. break;
  938. case USB_PORT_FEAT_POWER:
  939. reg |= PORT_POWER;
  940. xhci_writel(status_reg, reg);
  941. break;
  942. case USB_PORT_FEAT_RESET:
  943. reg |= PORT_RESET;
  944. xhci_writel(status_reg, reg);
  945. break;
  946. default:
  947. printf("unknown feature %x\n", le16_to_cpu(req->value));
  948. goto unknown;
  949. }
  950. break;
  951. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  952. reg = xhci_readl(status_reg);
  953. reg = xhci_port_state_to_neutral(reg);
  954. switch (le16_to_cpu(req->value)) {
  955. case USB_PORT_FEAT_ENABLE:
  956. reg &= ~PORT_PE;
  957. break;
  958. case USB_PORT_FEAT_POWER:
  959. reg &= ~PORT_POWER;
  960. break;
  961. case USB_PORT_FEAT_C_RESET:
  962. case USB_PORT_FEAT_C_CONNECTION:
  963. case USB_PORT_FEAT_C_OVER_CURRENT:
  964. case USB_PORT_FEAT_C_ENABLE:
  965. xhci_clear_port_change_bit((le16_to_cpu(req->value)),
  966. le16_to_cpu(req->index),
  967. status_reg, reg);
  968. break;
  969. default:
  970. printf("unknown feature %x\n", le16_to_cpu(req->value));
  971. goto unknown;
  972. }
  973. xhci_writel(status_reg, reg);
  974. break;
  975. default:
  976. puts("Unknown request\n");
  977. goto unknown;
  978. }
  979. debug("scrlen = %d\n req->length = %d\n",
  980. srclen, le16_to_cpu(req->length));
  981. len = min(srclen, (int)le16_to_cpu(req->length));
  982. if (srcptr != NULL && len > 0)
  983. memcpy(buffer, srcptr, len);
  984. else
  985. debug("Len is 0\n");
  986. udev->act_len = len;
  987. udev->status = 0;
  988. return 0;
  989. unknown:
  990. udev->act_len = 0;
  991. udev->status = USB_ST_STALLED;
  992. return -ENODEV;
  993. }
  994. /**
  995. * Submits the INT request to XHCI Host cotroller
  996. *
  997. * @param udev pointer to the USB device
  998. * @param pipe contains the DIR_IN or OUT , devnum
  999. * @param buffer buffer to be read/written based on the request
  1000. * @param length length of the buffer
  1001. * @param interval interval of the interrupt
  1002. * @return 0
  1003. */
  1004. static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
  1005. void *buffer, int length, int interval,
  1006. bool nonblock)
  1007. {
  1008. if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
  1009. printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
  1010. return -EINVAL;
  1011. }
  1012. /*
  1013. * xHCI uses normal TRBs for both bulk and interrupt. When the
  1014. * interrupt endpoint is to be serviced, the xHC will consume
  1015. * (at most) one TD. A TD (comprised of sg list entries) can
  1016. * take several service intervals to transmit.
  1017. */
  1018. return xhci_bulk_tx(udev, pipe, length, buffer);
  1019. }
  1020. /**
  1021. * submit the BULK type of request to the USB Device
  1022. *
  1023. * @param udev pointer to the USB device
  1024. * @param pipe contains the DIR_IN or OUT , devnum
  1025. * @param buffer buffer to be read/written based on the request
  1026. * @param length length of the buffer
  1027. * @return returns 0 if successful else -1 on failure
  1028. */
  1029. static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
  1030. void *buffer, int length)
  1031. {
  1032. if (usb_pipetype(pipe) != PIPE_BULK) {
  1033. printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  1034. return -EINVAL;
  1035. }
  1036. return xhci_bulk_tx(udev, pipe, length, buffer);
  1037. }
  1038. /**
  1039. * submit the control type of request to the Root hub/Device based on the devnum
  1040. *
  1041. * @param udev pointer to the USB device
  1042. * @param pipe contains the DIR_IN or OUT , devnum
  1043. * @param buffer buffer to be read/written based on the request
  1044. * @param length length of the buffer
  1045. * @param setup Request type
  1046. * @param root_portnr Root port number that this device is on
  1047. * @return returns 0 if successful else -1 on failure
  1048. */
  1049. static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe,
  1050. void *buffer, int length,
  1051. struct devrequest *setup, int root_portnr)
  1052. {
  1053. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  1054. int ret = 0;
  1055. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  1056. printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
  1057. return -EINVAL;
  1058. }
  1059. if (usb_pipedevice(pipe) == ctrl->rootdev)
  1060. return xhci_submit_root(udev, pipe, buffer, setup);
  1061. if (setup->request == USB_REQ_SET_ADDRESS &&
  1062. (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
  1063. return xhci_address_device(udev, root_portnr);
  1064. if (setup->request == USB_REQ_SET_CONFIGURATION &&
  1065. (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  1066. ret = xhci_set_configuration(udev);
  1067. if (ret) {
  1068. puts("Failed to configure xHCI endpoint\n");
  1069. return ret;
  1070. }
  1071. }
  1072. return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
  1073. }
  1074. static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
  1075. {
  1076. struct xhci_hccr *hccr;
  1077. struct xhci_hcor *hcor;
  1078. uint32_t val;
  1079. uint32_t val2;
  1080. uint32_t reg;
  1081. hccr = ctrl->hccr;
  1082. hcor = ctrl->hcor;
  1083. /*
  1084. * Program the Number of Device Slots Enabled field in the CONFIG
  1085. * register with the max value of slots the HC can handle.
  1086. */
  1087. val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
  1088. val2 = xhci_readl(&hcor->or_config);
  1089. val |= (val2 & ~HCS_SLOTS_MASK);
  1090. xhci_writel(&hcor->or_config, val);
  1091. /* initializing xhci data structures */
  1092. if (xhci_mem_init(ctrl, hccr, hcor) < 0)
  1093. return -ENOMEM;
  1094. reg = xhci_readl(&hccr->cr_hcsparams1);
  1095. descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
  1096. HCS_MAX_PORTS_SHIFT);
  1097. printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  1098. /* Port Indicators */
  1099. reg = xhci_readl(&hccr->cr_hccparams);
  1100. if (HCS_INDICATOR(reg))
  1101. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  1102. | 0x80, &descriptor.hub.wHubCharacteristics);
  1103. /* Port Power Control */
  1104. if (HCC_PPC(reg))
  1105. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  1106. | 0x01, &descriptor.hub.wHubCharacteristics);
  1107. if (xhci_start(hcor)) {
  1108. xhci_reset(hcor);
  1109. return -ENODEV;
  1110. }
  1111. /* Zero'ing IRQ control register and IRQ pending register */
  1112. xhci_writel(&ctrl->ir_set->irq_control, 0x0);
  1113. xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
  1114. reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
  1115. printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
  1116. return 0;
  1117. }
  1118. static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
  1119. {
  1120. u32 temp;
  1121. xhci_reset(ctrl->hcor);
  1122. debug("// Disabling event ring interrupts\n");
  1123. temp = xhci_readl(&ctrl->hcor->or_usbsts);
  1124. xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
  1125. temp = xhci_readl(&ctrl->ir_set->irq_pending);
  1126. xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
  1127. return 0;
  1128. }
  1129. #if !CONFIG_IS_ENABLED(DM_USB)
  1130. int submit_control_msg(struct usb_device *udev, unsigned long pipe,
  1131. void *buffer, int length, struct devrequest *setup)
  1132. {
  1133. struct usb_device *hop = udev;
  1134. if (hop->parent)
  1135. while (hop->parent->parent)
  1136. hop = hop->parent;
  1137. return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
  1138. hop->portnr);
  1139. }
  1140. int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
  1141. int length)
  1142. {
  1143. return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
  1144. }
  1145. int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
  1146. int length, int interval, bool nonblock)
  1147. {
  1148. return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
  1149. nonblock);
  1150. }
  1151. /**
  1152. * Intialises the XHCI host controller
  1153. * and allocates the necessary data structures
  1154. *
  1155. * @param index index to the host controller data structure
  1156. * @return pointer to the intialised controller
  1157. */
  1158. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1159. {
  1160. struct xhci_hccr *hccr;
  1161. struct xhci_hcor *hcor;
  1162. struct xhci_ctrl *ctrl;
  1163. int ret;
  1164. *controller = NULL;
  1165. if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
  1166. return -ENODEV;
  1167. if (xhci_reset(hcor) != 0)
  1168. return -ENODEV;
  1169. ctrl = &xhcic[index];
  1170. ctrl->hccr = hccr;
  1171. ctrl->hcor = hcor;
  1172. ret = xhci_lowlevel_init(ctrl);
  1173. if (ret) {
  1174. ctrl->hccr = NULL;
  1175. ctrl->hcor = NULL;
  1176. } else {
  1177. *controller = &xhcic[index];
  1178. }
  1179. return ret;
  1180. }
  1181. /**
  1182. * Stops the XHCI host controller
  1183. * and cleans up all the related data structures
  1184. *
  1185. * @param index index to the host controller data structure
  1186. * @return none
  1187. */
  1188. int usb_lowlevel_stop(int index)
  1189. {
  1190. struct xhci_ctrl *ctrl = (xhcic + index);
  1191. if (ctrl->hcor) {
  1192. xhci_lowlevel_stop(ctrl);
  1193. xhci_hcd_stop(index);
  1194. xhci_cleanup(ctrl);
  1195. }
  1196. return 0;
  1197. }
  1198. #endif /* CONFIG_IS_ENABLED(DM_USB) */
  1199. #if CONFIG_IS_ENABLED(DM_USB)
  1200. static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1201. unsigned long pipe, void *buffer, int length,
  1202. struct devrequest *setup)
  1203. {
  1204. struct usb_device *uhop;
  1205. struct udevice *hub;
  1206. int root_portnr = 0;
  1207. debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
  1208. dev->name, udev, udev->dev->name, udev->portnr);
  1209. hub = udev->dev;
  1210. if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
  1211. /* Figure out our port number on the root hub */
  1212. if (usb_hub_is_root_hub(hub)) {
  1213. root_portnr = udev->portnr;
  1214. } else {
  1215. while (!usb_hub_is_root_hub(hub->parent))
  1216. hub = hub->parent;
  1217. uhop = dev_get_parent_priv(hub);
  1218. root_portnr = uhop->portnr;
  1219. }
  1220. }
  1221. /*
  1222. struct usb_device *hop = udev;
  1223. if (hop->parent)
  1224. while (hop->parent->parent)
  1225. hop = hop->parent;
  1226. */
  1227. return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
  1228. root_portnr);
  1229. }
  1230. static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1231. unsigned long pipe, void *buffer, int length)
  1232. {
  1233. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1234. return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
  1235. }
  1236. static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1237. unsigned long pipe, void *buffer, int length,
  1238. int interval, bool nonblock)
  1239. {
  1240. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1241. return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
  1242. nonblock);
  1243. }
  1244. static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
  1245. {
  1246. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1247. return _xhci_alloc_device(udev);
  1248. }
  1249. static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
  1250. {
  1251. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1252. struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
  1253. struct xhci_virt_device *virt_dev;
  1254. struct xhci_input_control_ctx *ctrl_ctx;
  1255. struct xhci_container_ctx *out_ctx;
  1256. struct xhci_container_ctx *in_ctx;
  1257. struct xhci_slot_ctx *slot_ctx;
  1258. int slot_id = udev->slot_id;
  1259. unsigned think_time;
  1260. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1261. /* Ignore root hubs */
  1262. if (usb_hub_is_root_hub(udev->dev))
  1263. return 0;
  1264. virt_dev = ctrl->devs[slot_id];
  1265. BUG_ON(!virt_dev);
  1266. out_ctx = virt_dev->out_ctx;
  1267. in_ctx = virt_dev->in_ctx;
  1268. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  1269. /* Initialize the input context control */
  1270. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  1271. ctrl_ctx->drop_flags = 0;
  1272. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  1273. /* slot context */
  1274. xhci_slot_copy(ctrl, in_ctx, out_ctx);
  1275. slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  1276. /* Update hub related fields */
  1277. slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
  1278. /*
  1279. * refer to section 6.2.2: MTT should be 0 for full speed hub,
  1280. * but it may be already set to 1 when setup an xHCI virtual
  1281. * device, so clear it anyway.
  1282. */
  1283. if (hub->tt.multi)
  1284. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  1285. else if (udev->speed == USB_SPEED_FULL)
  1286. slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
  1287. slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
  1288. /*
  1289. * Set TT think time - convert from ns to FS bit times.
  1290. * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
  1291. *
  1292. * 0 = 8 FS bit times, 1 = 16 FS bit times,
  1293. * 2 = 24 FS bit times, 3 = 32 FS bit times.
  1294. *
  1295. * This field shall be 0 if the device is not a high-spped hub.
  1296. */
  1297. think_time = hub->tt.think_time;
  1298. if (think_time != 0)
  1299. think_time = (think_time / 666) - 1;
  1300. if (udev->speed == USB_SPEED_HIGH)
  1301. slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
  1302. slot_ctx->dev_state = 0;
  1303. return xhci_configure_endpoints(udev, false);
  1304. }
  1305. static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size)
  1306. {
  1307. /*
  1308. * xHCD allocates one segment which includes 64 TRBs for each endpoint
  1309. * and the last TRB in this segment is configured as a link TRB to form
  1310. * a TRB ring. Each TRB can transfer up to 64K bytes, however data
  1311. * buffers referenced by transfer TRBs shall not span 64KB boundaries.
  1312. * Hence the maximum number of TRBs we can use in one transfer is 62.
  1313. */
  1314. *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE;
  1315. return 0;
  1316. }
  1317. int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
  1318. struct xhci_hcor *hcor)
  1319. {
  1320. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1321. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  1322. int ret;
  1323. debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name,
  1324. ctrl, hccr, hcor);
  1325. ctrl->dev = dev;
  1326. /*
  1327. * XHCI needs to issue a Address device command to setup
  1328. * proper device context structures, before it can interact
  1329. * with the device. So a get_descriptor will fail before any
  1330. * of that is done for XHCI unlike EHCI.
  1331. */
  1332. priv->desc_before_addr = false;
  1333. ret = xhci_reset(hcor);
  1334. if (ret)
  1335. goto err;
  1336. ctrl->hccr = hccr;
  1337. ctrl->hcor = hcor;
  1338. ret = xhci_lowlevel_init(ctrl);
  1339. if (ret)
  1340. goto err;
  1341. return 0;
  1342. err:
  1343. free(ctrl);
  1344. debug("%s: failed, ret=%d\n", __func__, ret);
  1345. return ret;
  1346. }
  1347. int xhci_deregister(struct udevice *dev)
  1348. {
  1349. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1350. xhci_lowlevel_stop(ctrl);
  1351. xhci_cleanup(ctrl);
  1352. return 0;
  1353. }
  1354. struct dm_usb_ops xhci_usb_ops = {
  1355. .control = xhci_submit_control_msg,
  1356. .bulk = xhci_submit_bulk_msg,
  1357. .interrupt = xhci_submit_int_msg,
  1358. .alloc_device = xhci_alloc_device,
  1359. .update_hub_device = xhci_update_hub_device,
  1360. .get_max_xfer_size = xhci_get_max_xfer_size,
  1361. };
  1362. #endif