dwc2_udc_otg.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/usb/gadget/dwc2_udc_otg.c
  4. * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
  5. *
  6. * Copyright (C) 2008 for Samsung Electronics
  7. *
  8. * BSP Support for Samsung's UDC driver
  9. * available at:
  10. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  11. *
  12. * State machine bugfixes:
  13. * Marek Szyprowski <m.szyprowski@samsung.com>
  14. *
  15. * Ported to u-boot:
  16. * Marek Szyprowski <m.szyprowski@samsung.com>
  17. * Lukasz Majewski <l.majewski@samsumg.com>
  18. */
  19. #undef DEBUG
  20. #include <common.h>
  21. #include <clk.h>
  22. #include <dm.h>
  23. #include <generic-phy.h>
  24. #include <log.h>
  25. #include <malloc.h>
  26. #include <reset.h>
  27. #include <dm/device_compat.h>
  28. #include <dm/devres.h>
  29. #include <linux/bug.h>
  30. #include <linux/errno.h>
  31. #include <linux/list.h>
  32. #include <linux/usb/ch9.h>
  33. #include <linux/usb/otg.h>
  34. #include <linux/usb/gadget.h>
  35. #include <phys2bus.h>
  36. #include <asm/byteorder.h>
  37. #include <asm/unaligned.h>
  38. #include <asm/io.h>
  39. #include <asm/mach-types.h>
  40. #include <power/regulator.h>
  41. #include "dwc2_udc_otg_regs.h"
  42. #include "dwc2_udc_otg_priv.h"
  43. /***********************************************************/
  44. #define OTG_DMA_MODE 1
  45. #define DEBUG_SETUP 0
  46. #define DEBUG_EP0 0
  47. #define DEBUG_ISR 0
  48. #define DEBUG_OUT_EP 0
  49. #define DEBUG_IN_EP 0
  50. #include <usb/dwc2_udc.h>
  51. #define EP0_CON 0
  52. #define EP_MASK 0xF
  53. static char *state_names[] = {
  54. "WAIT_FOR_SETUP",
  55. "DATA_STATE_XMIT",
  56. "DATA_STATE_NEED_ZLP",
  57. "WAIT_FOR_OUT_STATUS",
  58. "DATA_STATE_RECV",
  59. "WAIT_FOR_COMPLETE",
  60. "WAIT_FOR_OUT_COMPLETE",
  61. "WAIT_FOR_IN_COMPLETE",
  62. "WAIT_FOR_NULL_COMPLETE",
  63. };
  64. #define DRIVER_VERSION "15 March 2009"
  65. struct dwc2_udc *the_controller;
  66. static const char driver_name[] = "dwc2-udc";
  67. static const char ep0name[] = "ep0-control";
  68. /* Max packet size*/
  69. static unsigned int ep0_fifo_size = 64;
  70. static unsigned int ep_fifo_size = 512;
  71. static unsigned int ep_fifo_size2 = 1024;
  72. static int reset_available = 1;
  73. static struct usb_ctrlrequest *usb_ctrl;
  74. static dma_addr_t usb_ctrl_dma_addr;
  75. /*
  76. Local declarations.
  77. */
  78. static int dwc2_ep_enable(struct usb_ep *ep,
  79. const struct usb_endpoint_descriptor *);
  80. static int dwc2_ep_disable(struct usb_ep *ep);
  81. static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
  82. gfp_t gfp_flags);
  83. static void dwc2_free_request(struct usb_ep *ep, struct usb_request *);
  84. static int dwc2_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
  85. static int dwc2_dequeue(struct usb_ep *ep, struct usb_request *);
  86. static int dwc2_fifo_status(struct usb_ep *ep);
  87. static void dwc2_fifo_flush(struct usb_ep *ep);
  88. static void dwc2_ep0_read(struct dwc2_udc *dev);
  89. static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep);
  90. static void dwc2_handle_ep0(struct dwc2_udc *dev);
  91. static int dwc2_ep0_write(struct dwc2_udc *dev);
  92. static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req);
  93. static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status);
  94. static void stop_activity(struct dwc2_udc *dev,
  95. struct usb_gadget_driver *driver);
  96. static int udc_enable(struct dwc2_udc *dev);
  97. static void udc_set_address(struct dwc2_udc *dev, unsigned char address);
  98. static void reconfig_usbd(struct dwc2_udc *dev);
  99. static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed);
  100. static void nuke(struct dwc2_ep *ep, int status);
  101. static int dwc2_udc_set_halt(struct usb_ep *_ep, int value);
  102. static void dwc2_udc_set_nak(struct dwc2_ep *ep);
  103. void set_udc_gadget_private_data(void *p)
  104. {
  105. debug_cond(DEBUG_SETUP != 0,
  106. "%s: the_controller: 0x%p, p: 0x%p\n", __func__,
  107. the_controller, p);
  108. the_controller->gadget.dev.device_data = p;
  109. }
  110. void *get_udc_gadget_private_data(struct usb_gadget *gadget)
  111. {
  112. return gadget->dev.device_data;
  113. }
  114. static struct usb_ep_ops dwc2_ep_ops = {
  115. .enable = dwc2_ep_enable,
  116. .disable = dwc2_ep_disable,
  117. .alloc_request = dwc2_alloc_request,
  118. .free_request = dwc2_free_request,
  119. .queue = dwc2_queue,
  120. .dequeue = dwc2_dequeue,
  121. .set_halt = dwc2_udc_set_halt,
  122. .fifo_status = dwc2_fifo_status,
  123. .fifo_flush = dwc2_fifo_flush,
  124. };
  125. #define create_proc_files() do {} while (0)
  126. #define remove_proc_files() do {} while (0)
  127. /***********************************************************/
  128. struct dwc2_usbotg_reg *reg;
  129. bool dfu_usb_get_reset(void)
  130. {
  131. return !!(readl(&reg->gintsts) & INT_RESET);
  132. }
  133. __weak void otg_phy_init(struct dwc2_udc *dev) {}
  134. __weak void otg_phy_off(struct dwc2_udc *dev) {}
  135. /***********************************************************/
  136. #include "dwc2_udc_otg_xfer_dma.c"
  137. /*
  138. * udc_disable - disable USB device controller
  139. */
  140. static void udc_disable(struct dwc2_udc *dev)
  141. {
  142. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  143. udc_set_address(dev, 0);
  144. dev->ep0state = WAIT_FOR_SETUP;
  145. dev->gadget.speed = USB_SPEED_UNKNOWN;
  146. dev->usb_address = 0;
  147. otg_phy_off(dev);
  148. }
  149. /*
  150. * udc_reinit - initialize software state
  151. */
  152. static void udc_reinit(struct dwc2_udc *dev)
  153. {
  154. unsigned int i;
  155. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  156. /* device/ep0 records init */
  157. INIT_LIST_HEAD(&dev->gadget.ep_list);
  158. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  159. dev->ep0state = WAIT_FOR_SETUP;
  160. /* basic endpoint records init */
  161. for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
  162. struct dwc2_ep *ep = &dev->ep[i];
  163. if (i != 0)
  164. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  165. ep->desc = 0;
  166. ep->stopped = 0;
  167. INIT_LIST_HEAD(&ep->queue);
  168. ep->pio_irqs = 0;
  169. }
  170. /* the rest was statically initialized, and is read-only */
  171. }
  172. #define BYTES2MAXP(x) (x / 8)
  173. #define MAXP2BYTES(x) (x * 8)
  174. /* until it's enabled, this UDC should be completely invisible
  175. * to any USB host.
  176. */
  177. static int udc_enable(struct dwc2_udc *dev)
  178. {
  179. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  180. otg_phy_init(dev);
  181. reconfig_usbd(dev);
  182. debug_cond(DEBUG_SETUP != 0,
  183. "DWC2 USB 2.0 OTG Controller Core Initialized : 0x%x\n",
  184. readl(&reg->gintmsk));
  185. dev->gadget.speed = USB_SPEED_UNKNOWN;
  186. return 0;
  187. }
  188. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  189. /*
  190. Register entry point for the peripheral controller driver.
  191. */
  192. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  193. {
  194. struct dwc2_udc *dev = the_controller;
  195. int retval = 0;
  196. unsigned long flags = 0;
  197. debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
  198. if (!driver
  199. || (driver->speed != USB_SPEED_FULL
  200. && driver->speed != USB_SPEED_HIGH)
  201. || !driver->bind || !driver->disconnect || !driver->setup)
  202. return -EINVAL;
  203. if (!dev)
  204. return -ENODEV;
  205. if (dev->driver)
  206. return -EBUSY;
  207. spin_lock_irqsave(&dev->lock, flags);
  208. /* first hook up the driver ... */
  209. dev->driver = driver;
  210. spin_unlock_irqrestore(&dev->lock, flags);
  211. if (retval) { /* TODO */
  212. printf("target device_add failed, error %d\n", retval);
  213. return retval;
  214. }
  215. retval = driver->bind(&dev->gadget);
  216. if (retval) {
  217. debug_cond(DEBUG_SETUP != 0,
  218. "%s: bind to driver --> error %d\n",
  219. dev->gadget.name, retval);
  220. dev->driver = 0;
  221. return retval;
  222. }
  223. enable_irq(IRQ_OTG);
  224. debug_cond(DEBUG_SETUP != 0,
  225. "Registered gadget driver %s\n", dev->gadget.name);
  226. udc_enable(dev);
  227. return 0;
  228. }
  229. /*
  230. * Unregister entry point for the peripheral controller driver.
  231. */
  232. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  233. {
  234. struct dwc2_udc *dev = the_controller;
  235. unsigned long flags = 0;
  236. if (!dev)
  237. return -ENODEV;
  238. if (!driver || driver != dev->driver)
  239. return -EINVAL;
  240. spin_lock_irqsave(&dev->lock, flags);
  241. dev->driver = 0;
  242. stop_activity(dev, driver);
  243. spin_unlock_irqrestore(&dev->lock, flags);
  244. driver->unbind(&dev->gadget);
  245. disable_irq(IRQ_OTG);
  246. udc_disable(dev);
  247. return 0;
  248. }
  249. #else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  250. static int dwc2_gadget_start(struct usb_gadget *g,
  251. struct usb_gadget_driver *driver)
  252. {
  253. struct dwc2_udc *dev = the_controller;
  254. debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
  255. if (!driver ||
  256. (driver->speed != USB_SPEED_FULL &&
  257. driver->speed != USB_SPEED_HIGH) ||
  258. !driver->bind || !driver->disconnect || !driver->setup)
  259. return -EINVAL;
  260. if (!dev)
  261. return -ENODEV;
  262. if (dev->driver)
  263. return -EBUSY;
  264. /* first hook up the driver ... */
  265. dev->driver = driver;
  266. debug_cond(DEBUG_SETUP != 0,
  267. "Registered gadget driver %s\n", dev->gadget.name);
  268. return udc_enable(dev);
  269. }
  270. static int dwc2_gadget_stop(struct usb_gadget *g)
  271. {
  272. struct dwc2_udc *dev = the_controller;
  273. if (!dev)
  274. return -ENODEV;
  275. if (!dev->driver)
  276. return -EINVAL;
  277. dev->driver = 0;
  278. stop_activity(dev, dev->driver);
  279. udc_disable(dev);
  280. return 0;
  281. }
  282. #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  283. /*
  284. * done - retire a request; caller blocked irqs
  285. */
  286. static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status)
  287. {
  288. unsigned int stopped = ep->stopped;
  289. debug("%s: %s %p, req = %p, stopped = %d\n",
  290. __func__, ep->ep.name, ep, &req->req, stopped);
  291. list_del_init(&req->queue);
  292. if (likely(req->req.status == -EINPROGRESS))
  293. req->req.status = status;
  294. else
  295. status = req->req.status;
  296. if (status && status != -ESHUTDOWN) {
  297. debug("complete %s req %p stat %d len %u/%u\n",
  298. ep->ep.name, &req->req, status,
  299. req->req.actual, req->req.length);
  300. }
  301. /* don't modify queue heads during completion callback */
  302. ep->stopped = 1;
  303. #ifdef DEBUG
  304. printf("calling complete callback\n");
  305. {
  306. int i, len = req->req.length;
  307. printf("pkt[%d] = ", req->req.length);
  308. if (len > 64)
  309. len = 64;
  310. for (i = 0; i < len; i++) {
  311. printf("%02x", ((u8 *)req->req.buf)[i]);
  312. if ((i & 7) == 7)
  313. printf(" ");
  314. }
  315. printf("\n");
  316. }
  317. #endif
  318. spin_unlock(&ep->dev->lock);
  319. req->req.complete(&ep->ep, &req->req);
  320. spin_lock(&ep->dev->lock);
  321. debug("callback completed\n");
  322. ep->stopped = stopped;
  323. }
  324. /*
  325. * nuke - dequeue ALL requests
  326. */
  327. static void nuke(struct dwc2_ep *ep, int status)
  328. {
  329. struct dwc2_request *req;
  330. debug("%s: %s %p\n", __func__, ep->ep.name, ep);
  331. /* called with irqs blocked */
  332. while (!list_empty(&ep->queue)) {
  333. req = list_entry(ep->queue.next, struct dwc2_request, queue);
  334. done(ep, req, status);
  335. }
  336. }
  337. static void stop_activity(struct dwc2_udc *dev,
  338. struct usb_gadget_driver *driver)
  339. {
  340. int i;
  341. /* don't disconnect drivers more than once */
  342. if (dev->gadget.speed == USB_SPEED_UNKNOWN)
  343. driver = 0;
  344. dev->gadget.speed = USB_SPEED_UNKNOWN;
  345. /* prevent new request submissions, kill any outstanding requests */
  346. for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
  347. struct dwc2_ep *ep = &dev->ep[i];
  348. ep->stopped = 1;
  349. nuke(ep, -ESHUTDOWN);
  350. }
  351. /* report disconnect; the driver is already quiesced */
  352. if (driver) {
  353. spin_unlock(&dev->lock);
  354. driver->disconnect(&dev->gadget);
  355. spin_lock(&dev->lock);
  356. }
  357. /* re-init driver-visible data structures */
  358. udc_reinit(dev);
  359. }
  360. static void reconfig_usbd(struct dwc2_udc *dev)
  361. {
  362. /* 2. Soft-reset OTG Core and then unreset again. */
  363. int i;
  364. unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
  365. uint32_t dflt_gusbcfg;
  366. uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
  367. u32 max_hw_ep;
  368. int pdata_hw_ep;
  369. debug("Reseting OTG controller\n");
  370. dflt_gusbcfg =
  371. 0<<15 /* PHY Low Power Clock sel*/
  372. |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
  373. |0x5<<10 /* Turnaround time*/
  374. |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
  375. /* 1:SRP enable] H1= 1,1*/
  376. |0<<7 /* Ulpi DDR sel*/
  377. |0<<6 /* 0: high speed utmi+, 1: full speed serial*/
  378. |0<<4 /* 0: utmi+, 1:ulpi*/
  379. #ifdef CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
  380. |0<<3 /* phy i/f 0:8bit, 1:16bit*/
  381. #else
  382. |1<<3 /* phy i/f 0:8bit, 1:16bit*/
  383. #endif
  384. |0x7<<0; /* HS/FS Timeout**/
  385. if (dev->pdata->usb_gusbcfg)
  386. dflt_gusbcfg = dev->pdata->usb_gusbcfg;
  387. writel(dflt_gusbcfg, &reg->gusbcfg);
  388. /* 3. Put the OTG device core in the disconnected state.*/
  389. uTemp = readl(&reg->dctl);
  390. uTemp |= SOFT_DISCONNECT;
  391. writel(uTemp, &reg->dctl);
  392. udelay(20);
  393. /* 4. Make the OTG device core exit from the disconnected state.*/
  394. uTemp = readl(&reg->dctl);
  395. uTemp = uTemp & ~SOFT_DISCONNECT;
  396. writel(uTemp, &reg->dctl);
  397. /* 5. Configure OTG Core to initial settings of device mode.*/
  398. /* [][1: full speed(30Mhz) 0:high speed]*/
  399. writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->dcfg);
  400. mdelay(1);
  401. /* 6. Unmask the core interrupts*/
  402. writel(GINTMSK_INIT, &reg->gintmsk);
  403. /* 7. Set NAK bit of EP0, EP1, EP2*/
  404. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
  405. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
  406. for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) {
  407. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
  408. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
  409. }
  410. /* 8. Unmask EPO interrupts*/
  411. writel(((1 << EP0_CON) << DAINT_OUT_BIT)
  412. | (1 << EP0_CON), &reg->daintmsk);
  413. /* 9. Unmask device OUT EP common interrupts*/
  414. writel(DOEPMSK_INIT, &reg->doepmsk);
  415. /* 10. Unmask device IN EP common interrupts*/
  416. writel(DIEPMSK_INIT, &reg->diepmsk);
  417. rx_fifo_sz = RX_FIFO_SIZE;
  418. np_tx_fifo_sz = NPTX_FIFO_SIZE;
  419. tx_fifo_sz = PTX_FIFO_SIZE;
  420. if (dev->pdata->rx_fifo_sz)
  421. rx_fifo_sz = dev->pdata->rx_fifo_sz;
  422. if (dev->pdata->np_tx_fifo_sz)
  423. np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz;
  424. if (dev->pdata->tx_fifo_sz)
  425. tx_fifo_sz = dev->pdata->tx_fifo_sz;
  426. /* 11. Set Rx FIFO Size (in 32-bit words) */
  427. writel(rx_fifo_sz, &reg->grxfsiz);
  428. /* 12. Set Non Periodic Tx FIFO Size */
  429. writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
  430. &reg->gnptxfsiz);
  431. /* retrieve the number of IN Endpoints (excluding ep0) */
  432. max_hw_ep = (readl(&reg->ghwcfg4) & GHWCFG4_NUM_IN_EPS_MASK) >>
  433. GHWCFG4_NUM_IN_EPS_SHIFT;
  434. pdata_hw_ep = dev->pdata->tx_fifo_sz_nb;
  435. /* tx_fifo_sz_nb should equal to number of IN Endpoint */
  436. if (pdata_hw_ep && max_hw_ep != pdata_hw_ep)
  437. pr_warn("Got %d hw endpoint but %d tx-fifo-size in array !!\n",
  438. max_hw_ep, pdata_hw_ep);
  439. for (i = 0; i < max_hw_ep; i++) {
  440. if (pdata_hw_ep)
  441. tx_fifo_sz = dev->pdata->tx_fifo_sz_array[i];
  442. writel((rx_fifo_sz + np_tx_fifo_sz + (tx_fifo_sz * i)) |
  443. tx_fifo_sz << 16, &reg->dieptxf[i]);
  444. }
  445. /* Flush the RX FIFO */
  446. writel(RX_FIFO_FLUSH, &reg->grstctl);
  447. while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
  448. debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
  449. /* Flush all the Tx FIFO's */
  450. writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
  451. writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
  452. while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
  453. debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
  454. /* 13. Clear NAK bit of EP0, EP1, EP2*/
  455. /* For Slave mode*/
  456. /* EP0: Control OUT */
  457. writel(DEPCTL_EPDIS | DEPCTL_CNAK,
  458. &reg->out_endp[EP0_CON].doepctl);
  459. /* 14. Initialize OTG Link Core.*/
  460. writel(GAHBCFG_INIT, &reg->gahbcfg);
  461. }
  462. static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed)
  463. {
  464. unsigned int ep_ctrl;
  465. int i;
  466. if (speed == USB_SPEED_HIGH) {
  467. ep0_fifo_size = 64;
  468. ep_fifo_size = 512;
  469. ep_fifo_size2 = 1024;
  470. dev->gadget.speed = USB_SPEED_HIGH;
  471. } else {
  472. ep0_fifo_size = 64;
  473. ep_fifo_size = 64;
  474. ep_fifo_size2 = 64;
  475. dev->gadget.speed = USB_SPEED_FULL;
  476. }
  477. dev->ep[0].ep.maxpacket = ep0_fifo_size;
  478. for (i = 1; i < DWC2_MAX_ENDPOINTS; i++)
  479. dev->ep[i].ep.maxpacket = ep_fifo_size;
  480. /* EP0 - Control IN (64 bytes)*/
  481. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  482. writel(ep_ctrl|(0<<0), &reg->in_endp[EP0_CON].diepctl);
  483. /* EP0 - Control OUT (64 bytes)*/
  484. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  485. writel(ep_ctrl|(0<<0), &reg->out_endp[EP0_CON].doepctl);
  486. }
  487. static int dwc2_ep_enable(struct usb_ep *_ep,
  488. const struct usb_endpoint_descriptor *desc)
  489. {
  490. struct dwc2_ep *ep;
  491. struct dwc2_udc *dev;
  492. unsigned long flags = 0;
  493. debug("%s: %p\n", __func__, _ep);
  494. ep = container_of(_ep, struct dwc2_ep, ep);
  495. if (!_ep || !desc || ep->desc || _ep->name == ep0name
  496. || desc->bDescriptorType != USB_DT_ENDPOINT
  497. || ep->bEndpointAddress != desc->bEndpointAddress
  498. || ep_maxpacket(ep) <
  499. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
  500. debug("%s: bad ep or descriptor\n", __func__);
  501. return -EINVAL;
  502. }
  503. /* xfer types must match, except that interrupt ~= bulk */
  504. if (ep->bmAttributes != desc->bmAttributes
  505. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  506. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  507. debug("%s: %s type mismatch\n", __func__, _ep->name);
  508. return -EINVAL;
  509. }
  510. /* hardware _could_ do smaller, but driver doesn't */
  511. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK &&
  512. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) >
  513. ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
  514. debug("%s: bad %s maxpacket\n", __func__, _ep->name);
  515. return -ERANGE;
  516. }
  517. dev = ep->dev;
  518. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
  519. debug("%s: bogus device state\n", __func__);
  520. return -ESHUTDOWN;
  521. }
  522. ep->stopped = 0;
  523. ep->desc = desc;
  524. ep->pio_irqs = 0;
  525. ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
  526. /* Reset halt state */
  527. dwc2_udc_set_nak(ep);
  528. dwc2_udc_set_halt(_ep, 0);
  529. spin_lock_irqsave(&ep->dev->lock, flags);
  530. dwc2_udc_ep_activate(ep);
  531. spin_unlock_irqrestore(&ep->dev->lock, flags);
  532. debug("%s: enabled %s, stopped = %d, maxpacket = %d\n",
  533. __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
  534. return 0;
  535. }
  536. /*
  537. * Disable EP
  538. */
  539. static int dwc2_ep_disable(struct usb_ep *_ep)
  540. {
  541. struct dwc2_ep *ep;
  542. unsigned long flags = 0;
  543. debug("%s: %p\n", __func__, _ep);
  544. ep = container_of(_ep, struct dwc2_ep, ep);
  545. if (!_ep || !ep->desc) {
  546. debug("%s: %s not enabled\n", __func__,
  547. _ep ? ep->ep.name : NULL);
  548. return -EINVAL;
  549. }
  550. spin_lock_irqsave(&ep->dev->lock, flags);
  551. /* Nuke all pending requests */
  552. nuke(ep, -ESHUTDOWN);
  553. ep->desc = 0;
  554. ep->stopped = 1;
  555. spin_unlock_irqrestore(&ep->dev->lock, flags);
  556. debug("%s: disabled %s\n", __func__, _ep->name);
  557. return 0;
  558. }
  559. static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
  560. gfp_t gfp_flags)
  561. {
  562. struct dwc2_request *req;
  563. debug("%s: %s %p\n", __func__, ep->name, ep);
  564. req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req));
  565. if (!req)
  566. return 0;
  567. memset(req, 0, sizeof *req);
  568. INIT_LIST_HEAD(&req->queue);
  569. return &req->req;
  570. }
  571. static void dwc2_free_request(struct usb_ep *ep, struct usb_request *_req)
  572. {
  573. struct dwc2_request *req;
  574. debug("%s: %p\n", __func__, ep);
  575. req = container_of(_req, struct dwc2_request, req);
  576. WARN_ON(!list_empty(&req->queue));
  577. kfree(req);
  578. }
  579. /* dequeue JUST ONE request */
  580. static int dwc2_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  581. {
  582. struct dwc2_ep *ep;
  583. struct dwc2_request *req;
  584. unsigned long flags = 0;
  585. debug("%s: %p\n", __func__, _ep);
  586. ep = container_of(_ep, struct dwc2_ep, ep);
  587. if (!_ep || ep->ep.name == ep0name)
  588. return -EINVAL;
  589. spin_lock_irqsave(&ep->dev->lock, flags);
  590. /* make sure it's actually queued on this endpoint */
  591. list_for_each_entry(req, &ep->queue, queue) {
  592. if (&req->req == _req)
  593. break;
  594. }
  595. if (&req->req != _req) {
  596. spin_unlock_irqrestore(&ep->dev->lock, flags);
  597. return -EINVAL;
  598. }
  599. done(ep, req, -ECONNRESET);
  600. spin_unlock_irqrestore(&ep->dev->lock, flags);
  601. return 0;
  602. }
  603. /*
  604. * Return bytes in EP FIFO
  605. */
  606. static int dwc2_fifo_status(struct usb_ep *_ep)
  607. {
  608. int count = 0;
  609. struct dwc2_ep *ep;
  610. ep = container_of(_ep, struct dwc2_ep, ep);
  611. if (!_ep) {
  612. debug("%s: bad ep\n", __func__);
  613. return -ENODEV;
  614. }
  615. debug("%s: %d\n", __func__, ep_index(ep));
  616. /* LPD can't report unclaimed bytes from IN fifos */
  617. if (ep_is_in(ep))
  618. return -EOPNOTSUPP;
  619. return count;
  620. }
  621. /*
  622. * Flush EP FIFO
  623. */
  624. static void dwc2_fifo_flush(struct usb_ep *_ep)
  625. {
  626. struct dwc2_ep *ep;
  627. ep = container_of(_ep, struct dwc2_ep, ep);
  628. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  629. debug("%s: bad ep\n", __func__);
  630. return;
  631. }
  632. debug("%s: %d\n", __func__, ep_index(ep));
  633. }
  634. static const struct usb_gadget_ops dwc2_udc_ops = {
  635. /* current versions must always be self-powered */
  636. #if CONFIG_IS_ENABLED(DM_USB_GADGET)
  637. .udc_start = dwc2_gadget_start,
  638. .udc_stop = dwc2_gadget_stop,
  639. #endif
  640. };
  641. static struct dwc2_udc memory = {
  642. .usb_address = 0,
  643. .gadget = {
  644. .ops = &dwc2_udc_ops,
  645. .ep0 = &memory.ep[0].ep,
  646. .name = driver_name,
  647. },
  648. /* control endpoint */
  649. .ep[0] = {
  650. .ep = {
  651. .name = ep0name,
  652. .ops = &dwc2_ep_ops,
  653. .maxpacket = EP0_FIFO_SIZE,
  654. },
  655. .dev = &memory,
  656. .bEndpointAddress = 0,
  657. .bmAttributes = 0,
  658. .ep_type = ep_control,
  659. },
  660. /* first group of endpoints */
  661. .ep[1] = {
  662. .ep = {
  663. .name = "ep1in-bulk",
  664. .ops = &dwc2_ep_ops,
  665. .maxpacket = EP_FIFO_SIZE,
  666. },
  667. .dev = &memory,
  668. .bEndpointAddress = USB_DIR_IN | 1,
  669. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  670. .ep_type = ep_bulk_out,
  671. .fifo_num = 1,
  672. },
  673. .ep[2] = {
  674. .ep = {
  675. .name = "ep2out-bulk",
  676. .ops = &dwc2_ep_ops,
  677. .maxpacket = EP_FIFO_SIZE,
  678. },
  679. .dev = &memory,
  680. .bEndpointAddress = USB_DIR_OUT | 2,
  681. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  682. .ep_type = ep_bulk_in,
  683. .fifo_num = 2,
  684. },
  685. .ep[3] = {
  686. .ep = {
  687. .name = "ep3in-int",
  688. .ops = &dwc2_ep_ops,
  689. .maxpacket = EP_FIFO_SIZE,
  690. },
  691. .dev = &memory,
  692. .bEndpointAddress = USB_DIR_IN | 3,
  693. .bmAttributes = USB_ENDPOINT_XFER_INT,
  694. .ep_type = ep_interrupt,
  695. .fifo_num = 3,
  696. },
  697. };
  698. /*
  699. * probe - binds to the platform device
  700. */
  701. int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata)
  702. {
  703. struct dwc2_udc *dev = &memory;
  704. int retval = 0;
  705. debug("%s: %p\n", __func__, pdata);
  706. dev->pdata = pdata;
  707. reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
  708. dev->gadget.is_dualspeed = 1; /* Hack only*/
  709. dev->gadget.is_otg = 0;
  710. dev->gadget.is_a_peripheral = 0;
  711. dev->gadget.b_hnp_enable = 0;
  712. dev->gadget.a_hnp_support = 0;
  713. dev->gadget.a_alt_hnp_support = 0;
  714. the_controller = dev;
  715. usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE,
  716. ROUND(sizeof(struct usb_ctrlrequest),
  717. CONFIG_SYS_CACHELINE_SIZE));
  718. if (!usb_ctrl) {
  719. pr_err("No memory available for UDC!\n");
  720. return -ENOMEM;
  721. }
  722. usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl;
  723. udc_reinit(dev);
  724. return retval;
  725. }
  726. int dwc2_udc_handle_interrupt(void)
  727. {
  728. u32 intr_status = readl(&reg->gintsts);
  729. u32 gintmsk = readl(&reg->gintmsk);
  730. if (intr_status & gintmsk)
  731. return dwc2_udc_irq(1, (void *)the_controller);
  732. return 0;
  733. }
  734. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  735. int usb_gadget_handle_interrupts(int index)
  736. {
  737. return dwc2_udc_handle_interrupt();
  738. }
  739. #else /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
  740. struct dwc2_priv_data {
  741. struct clk_bulk clks;
  742. struct reset_ctl_bulk resets;
  743. struct phy_bulk phys;
  744. struct udevice *usb33d_supply;
  745. };
  746. int dm_usb_gadget_handle_interrupts(struct udevice *dev)
  747. {
  748. return dwc2_udc_handle_interrupt();
  749. }
  750. static int dwc2_phy_setup(struct udevice *dev, struct phy_bulk *phys)
  751. {
  752. int ret;
  753. ret = generic_phy_get_bulk(dev, phys);
  754. if (ret)
  755. return ret;
  756. ret = generic_phy_init_bulk(phys);
  757. if (ret)
  758. return ret;
  759. ret = generic_phy_power_on_bulk(phys);
  760. if (ret)
  761. generic_phy_exit_bulk(phys);
  762. return ret;
  763. }
  764. static void dwc2_phy_shutdown(struct udevice *dev, struct phy_bulk *phys)
  765. {
  766. generic_phy_power_off_bulk(phys);
  767. generic_phy_exit_bulk(phys);
  768. }
  769. static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev)
  770. {
  771. struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
  772. ulong drvdata;
  773. void (*set_params)(struct dwc2_plat_otg_data *data);
  774. int ret;
  775. if (usb_get_dr_mode(dev->node) != USB_DR_MODE_PERIPHERAL &&
  776. usb_get_dr_mode(dev->node) != USB_DR_MODE_OTG) {
  777. dev_dbg(dev, "Invalid mode\n");
  778. return -ENODEV;
  779. }
  780. platdata->regs_otg = dev_read_addr(dev);
  781. platdata->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0);
  782. platdata->np_tx_fifo_sz = dev_read_u32_default(dev,
  783. "g-np-tx-fifo-size", 0);
  784. platdata->tx_fifo_sz_nb =
  785. dev_read_size(dev, "g-tx-fifo-size") / sizeof(u32);
  786. if (platdata->tx_fifo_sz_nb > DWC2_MAX_HW_ENDPOINTS)
  787. platdata->tx_fifo_sz_nb = DWC2_MAX_HW_ENDPOINTS;
  788. if (platdata->tx_fifo_sz_nb) {
  789. ret = dev_read_u32_array(dev, "g-tx-fifo-size",
  790. platdata->tx_fifo_sz_array,
  791. platdata->tx_fifo_sz_nb);
  792. if (ret)
  793. return ret;
  794. }
  795. platdata->force_b_session_valid =
  796. dev_read_bool(dev, "u-boot,force-b-session-valid");
  797. /* force platdata according compatible */
  798. drvdata = dev_get_driver_data(dev);
  799. if (drvdata) {
  800. set_params = (void *)drvdata;
  801. set_params(platdata);
  802. }
  803. return 0;
  804. }
  805. static void dwc2_set_stm32mp1_hsotg_params(struct dwc2_plat_otg_data *p)
  806. {
  807. p->activate_stm_id_vb_detection = true;
  808. p->usb_gusbcfg =
  809. 0 << 15 /* PHY Low Power Clock sel*/
  810. | 0x9 << 10 /* USB Turnaround time (0x9 for HS phy) */
  811. | 0 << 9 /* [0:HNP disable,1:HNP enable]*/
  812. | 0 << 8 /* [0:SRP disable 1:SRP enable]*/
  813. | 0 << 6 /* 0: high speed utmi+, 1: full speed serial*/
  814. | 0x7 << 0; /* FS timeout calibration**/
  815. if (p->force_b_session_valid)
  816. p->usb_gusbcfg |= 1 << 30; /* FDMOD: Force device mode */
  817. }
  818. static int dwc2_udc_otg_reset_init(struct udevice *dev,
  819. struct reset_ctl_bulk *resets)
  820. {
  821. int ret;
  822. ret = reset_get_bulk(dev, resets);
  823. if (ret == -ENOTSUPP)
  824. return 0;
  825. if (ret)
  826. return ret;
  827. ret = reset_assert_bulk(resets);
  828. if (!ret) {
  829. udelay(2);
  830. ret = reset_deassert_bulk(resets);
  831. }
  832. if (ret) {
  833. reset_release_bulk(resets);
  834. return ret;
  835. }
  836. return 0;
  837. }
  838. static int dwc2_udc_otg_clk_init(struct udevice *dev,
  839. struct clk_bulk *clks)
  840. {
  841. int ret;
  842. ret = clk_get_bulk(dev, clks);
  843. if (ret == -ENOSYS)
  844. return 0;
  845. if (ret)
  846. return ret;
  847. ret = clk_enable_bulk(clks);
  848. if (ret) {
  849. clk_release_bulk(clks);
  850. return ret;
  851. }
  852. return 0;
  853. }
  854. static int dwc2_udc_otg_probe(struct udevice *dev)
  855. {
  856. struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
  857. struct dwc2_priv_data *priv = dev_get_priv(dev);
  858. struct dwc2_usbotg_reg *usbotg_reg =
  859. (struct dwc2_usbotg_reg *)platdata->regs_otg;
  860. int ret;
  861. ret = dwc2_udc_otg_clk_init(dev, &priv->clks);
  862. if (ret)
  863. return ret;
  864. ret = dwc2_udc_otg_reset_init(dev, &priv->resets);
  865. if (ret)
  866. return ret;
  867. ret = dwc2_phy_setup(dev, &priv->phys);
  868. if (ret)
  869. return ret;
  870. if (CONFIG_IS_ENABLED(DM_REGULATOR) &&
  871. platdata->activate_stm_id_vb_detection &&
  872. !platdata->force_b_session_valid) {
  873. ret = device_get_supply_regulator(dev, "usb33d-supply",
  874. &priv->usb33d_supply);
  875. if (ret) {
  876. dev_err(dev, "can't get voltage level detector supply\n");
  877. return ret;
  878. }
  879. ret = regulator_set_enable(priv->usb33d_supply, true);
  880. if (ret) {
  881. dev_err(dev, "can't enable voltage level detector supply\n");
  882. return ret;
  883. }
  884. /* Enable vbus sensing */
  885. setbits_le32(&usbotg_reg->ggpio,
  886. GGPIO_STM32_OTG_GCCFG_VBDEN |
  887. GGPIO_STM32_OTG_GCCFG_IDEN);
  888. }
  889. if (platdata->force_b_session_valid)
  890. /* Override B session bits : value and enable */
  891. setbits_le32(&usbotg_reg->gotgctl,
  892. A_VALOEN | A_VALOVAL | B_VALOEN | B_VALOVAL);
  893. ret = dwc2_udc_probe(platdata);
  894. if (ret)
  895. return ret;
  896. the_controller->driver = 0;
  897. ret = usb_add_gadget_udc((struct device *)dev, &the_controller->gadget);
  898. return ret;
  899. }
  900. static int dwc2_udc_otg_remove(struct udevice *dev)
  901. {
  902. struct dwc2_priv_data *priv = dev_get_priv(dev);
  903. usb_del_gadget_udc(&the_controller->gadget);
  904. reset_release_bulk(&priv->resets);
  905. clk_release_bulk(&priv->clks);
  906. dwc2_phy_shutdown(dev, &priv->phys);
  907. return dm_scan_fdt_dev(dev);
  908. }
  909. static const struct udevice_id dwc2_udc_otg_ids[] = {
  910. { .compatible = "snps,dwc2" },
  911. { .compatible = "brcm,bcm2835-usb" },
  912. { .compatible = "st,stm32mp1-hsotg",
  913. .data = (ulong)dwc2_set_stm32mp1_hsotg_params },
  914. {},
  915. };
  916. U_BOOT_DRIVER(dwc2_udc_otg) = {
  917. .name = "dwc2-udc-otg",
  918. .id = UCLASS_USB_GADGET_GENERIC,
  919. .of_match = dwc2_udc_otg_ids,
  920. .ofdata_to_platdata = dwc2_udc_otg_ofdata_to_platdata,
  921. .probe = dwc2_udc_otg_probe,
  922. .remove = dwc2_udc_otg_remove,
  923. .platdata_auto_alloc_size = sizeof(struct dwc2_plat_otg_data),
  924. .priv_auto_alloc_size = sizeof(struct dwc2_priv_data),
  925. };
  926. int dwc2_udc_B_session_valid(struct udevice *dev)
  927. {
  928. struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
  929. struct dwc2_usbotg_reg *usbotg_reg =
  930. (struct dwc2_usbotg_reg *)platdata->regs_otg;
  931. return readl(&usbotg_reg->gotgctl) & B_SESSION_VALID;
  932. }
  933. #endif /* CONFIG_IS_ENABLED(DM_USB_GADGET) */