ep0.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
  11. * to uboot.
  12. *
  13. * commit c00552ebaf : Merge 3.18-rc7 into usb-next
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <dm/device_compat.h>
  18. #include <linux/bug.h>
  19. #include <linux/kernel.h>
  20. #include <linux/list.h>
  21. #include <linux/usb/ch9.h>
  22. #include <linux/usb/gadget.h>
  23. #include <linux/usb/composite.h>
  24. #include "core.h"
  25. #include "gadget.h"
  26. #include "io.h"
  27. #include "linux-compat.h"
  28. static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  29. static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  30. struct dwc3_ep *dep, struct dwc3_request *req);
  31. static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  32. {
  33. switch (state) {
  34. case EP0_UNCONNECTED:
  35. return "Unconnected";
  36. case EP0_SETUP_PHASE:
  37. return "Setup Phase";
  38. case EP0_DATA_PHASE:
  39. return "Data Phase";
  40. case EP0_STATUS_PHASE:
  41. return "Status Phase";
  42. default:
  43. return "UNKNOWN";
  44. }
  45. }
  46. static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  47. u32 len, u32 type, unsigned chain)
  48. {
  49. struct dwc3_gadget_ep_cmd_params params;
  50. struct dwc3_trb *trb;
  51. struct dwc3_ep *dep;
  52. int ret;
  53. dep = dwc->eps[epnum];
  54. if (dep->flags & DWC3_EP_BUSY) {
  55. dev_vdbg(dwc->dev, "%s still busy", dep->name);
  56. return 0;
  57. }
  58. trb = &dwc->ep0_trb[dep->free_slot];
  59. if (chain)
  60. dep->free_slot++;
  61. trb->bpl = lower_32_bits(buf_dma);
  62. trb->bph = upper_32_bits(buf_dma);
  63. trb->size = len;
  64. trb->ctrl = type;
  65. trb->ctrl |= (DWC3_TRB_CTRL_HWO
  66. | DWC3_TRB_CTRL_ISP_IMI);
  67. if (chain)
  68. trb->ctrl |= DWC3_TRB_CTRL_CHN;
  69. else
  70. trb->ctrl |= (DWC3_TRB_CTRL_IOC
  71. | DWC3_TRB_CTRL_LST);
  72. dwc3_flush_cache((uintptr_t)buf_dma, len);
  73. dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
  74. if (chain)
  75. return 0;
  76. memset(&params, 0, sizeof(params));
  77. params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  78. params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  79. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  80. DWC3_DEPCMD_STARTTRANSFER, &params);
  81. if (ret < 0) {
  82. dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
  83. return ret;
  84. }
  85. dep->flags |= DWC3_EP_BUSY;
  86. dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
  87. dep->number);
  88. dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  89. return 0;
  90. }
  91. static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  92. struct dwc3_request *req)
  93. {
  94. struct dwc3 *dwc = dep->dwc;
  95. req->request.actual = 0;
  96. req->request.status = -EINPROGRESS;
  97. req->epnum = dep->number;
  98. list_add_tail(&req->list, &dep->request_list);
  99. /*
  100. * Gadget driver might not be quick enough to queue a request
  101. * before we get a Transfer Not Ready event on this endpoint.
  102. *
  103. * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
  104. * flag is set, it's telling us that as soon as Gadget queues the
  105. * required request, we should kick the transfer here because the
  106. * IRQ we were waiting for is long gone.
  107. */
  108. if (dep->flags & DWC3_EP_PENDING_REQUEST) {
  109. unsigned direction;
  110. direction = !!(dep->flags & DWC3_EP0_DIR_IN);
  111. if (dwc->ep0state != EP0_DATA_PHASE) {
  112. dev_WARN(dwc->dev, "Unexpected pending request\n");
  113. return 0;
  114. }
  115. __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
  116. dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
  117. DWC3_EP0_DIR_IN);
  118. return 0;
  119. }
  120. /*
  121. * In case gadget driver asked us to delay the STATUS phase,
  122. * handle it here.
  123. */
  124. if (dwc->delayed_status) {
  125. unsigned direction;
  126. direction = !dwc->ep0_expect_in;
  127. dwc->delayed_status = false;
  128. usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
  129. if (dwc->ep0state == EP0_STATUS_PHASE)
  130. __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
  131. else
  132. dev_dbg(dwc->dev, "too early for delayed status");
  133. return 0;
  134. }
  135. /*
  136. * Unfortunately we have uncovered a limitation wrt the Data Phase.
  137. *
  138. * Section 9.4 says we can wait for the XferNotReady(DATA) event to
  139. * come before issueing Start Transfer command, but if we do, we will
  140. * miss situations where the host starts another SETUP phase instead of
  141. * the DATA phase. Such cases happen at least on TD.7.6 of the Link
  142. * Layer Compliance Suite.
  143. *
  144. * The problem surfaces due to the fact that in case of back-to-back
  145. * SETUP packets there will be no XferNotReady(DATA) generated and we
  146. * will be stuck waiting for XferNotReady(DATA) forever.
  147. *
  148. * By looking at tables 9-13 and 9-14 of the Databook, we can see that
  149. * it tells us to start Data Phase right away. It also mentions that if
  150. * we receive a SETUP phase instead of the DATA phase, core will issue
  151. * XferComplete for the DATA phase, before actually initiating it in
  152. * the wire, with the TRB's status set to "SETUP_PENDING". Such status
  153. * can only be used to print some debugging logs, as the core expects
  154. * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
  155. * just so it completes right away, without transferring anything and,
  156. * only then, we can go back to the SETUP phase.
  157. *
  158. * Because of this scenario, SNPS decided to change the programming
  159. * model of control transfers and support on-demand transfers only for
  160. * the STATUS phase. To fix the issue we have now, we will always wait
  161. * for gadget driver to queue the DATA phase's struct usb_request, then
  162. * start it right away.
  163. *
  164. * If we're actually in a 2-stage transfer, we will wait for
  165. * XferNotReady(STATUS).
  166. */
  167. if (dwc->three_stage_setup) {
  168. unsigned direction;
  169. direction = dwc->ep0_expect_in;
  170. dwc->ep0state = EP0_DATA_PHASE;
  171. __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
  172. dep->flags &= ~DWC3_EP0_DIR_IN;
  173. }
  174. return 0;
  175. }
  176. int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
  177. gfp_t gfp_flags)
  178. {
  179. struct dwc3_request *req = to_dwc3_request(request);
  180. struct dwc3_ep *dep = to_dwc3_ep(ep);
  181. struct dwc3 *dwc = dep->dwc;
  182. unsigned long flags;
  183. int ret;
  184. spin_lock_irqsave(&dwc->lock, flags);
  185. if (!dep->endpoint.desc) {
  186. dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
  187. request, dep->name);
  188. ret = -ESHUTDOWN;
  189. goto out;
  190. }
  191. /* we share one TRB for ep0/1 */
  192. if (!list_empty(&dep->request_list)) {
  193. ret = -EBUSY;
  194. goto out;
  195. }
  196. dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
  197. request, dep->name, request->length,
  198. dwc3_ep0_state_string(dwc->ep0state));
  199. ret = __dwc3_gadget_ep0_queue(dep, req);
  200. out:
  201. spin_unlock_irqrestore(&dwc->lock, flags);
  202. return ret;
  203. }
  204. static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
  205. {
  206. struct dwc3_ep *dep;
  207. /* reinitialize physical ep1 */
  208. dep = dwc->eps[1];
  209. dep->flags = DWC3_EP_ENABLED;
  210. /* stall is always issued on EP0 */
  211. dep = dwc->eps[0];
  212. __dwc3_gadget_ep_set_halt(dep, 1, false);
  213. dep->flags = DWC3_EP_ENABLED;
  214. dwc->delayed_status = false;
  215. if (!list_empty(&dep->request_list)) {
  216. struct dwc3_request *req;
  217. req = next_request(&dep->request_list);
  218. dwc3_gadget_giveback(dep, req, -ECONNRESET);
  219. }
  220. dwc->ep0state = EP0_SETUP_PHASE;
  221. dwc3_ep0_out_start(dwc);
  222. }
  223. int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
  224. {
  225. struct dwc3_ep *dep = to_dwc3_ep(ep);
  226. struct dwc3 *dwc = dep->dwc;
  227. dwc3_ep0_stall_and_restart(dwc);
  228. return 0;
  229. }
  230. int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
  231. {
  232. unsigned long flags;
  233. int ret;
  234. spin_lock_irqsave(&dwc->lock, flags);
  235. ret = __dwc3_gadget_ep0_set_halt(ep, value);
  236. spin_unlock_irqrestore(&dwc->lock, flags);
  237. return ret;
  238. }
  239. void dwc3_ep0_out_start(struct dwc3 *dwc)
  240. {
  241. int ret;
  242. ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
  243. DWC3_TRBCTL_CONTROL_SETUP, 0);
  244. WARN_ON(ret < 0);
  245. }
  246. static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
  247. {
  248. struct dwc3_ep *dep;
  249. u32 windex = le16_to_cpu(wIndex_le);
  250. u32 epnum;
  251. epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
  252. if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
  253. epnum |= 1;
  254. dep = dwc->eps[epnum];
  255. if (dep->flags & DWC3_EP_ENABLED)
  256. return dep;
  257. return NULL;
  258. }
  259. static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
  260. {
  261. }
  262. /*
  263. * ch 9.4.5
  264. */
  265. static int dwc3_ep0_handle_status(struct dwc3 *dwc,
  266. struct usb_ctrlrequest *ctrl)
  267. {
  268. struct dwc3_ep *dep;
  269. u32 recip;
  270. u32 reg;
  271. u16 usb_status = 0;
  272. __le16 *response_pkt;
  273. recip = ctrl->bRequestType & USB_RECIP_MASK;
  274. switch (recip) {
  275. case USB_RECIP_DEVICE:
  276. /*
  277. * LTM will be set once we know how to set this in HW.
  278. */
  279. usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
  280. if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
  281. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  282. if (reg & DWC3_DCTL_INITU1ENA)
  283. usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
  284. if (reg & DWC3_DCTL_INITU2ENA)
  285. usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
  286. }
  287. break;
  288. case USB_RECIP_INTERFACE:
  289. /*
  290. * Function Remote Wake Capable D0
  291. * Function Remote Wakeup D1
  292. */
  293. break;
  294. case USB_RECIP_ENDPOINT:
  295. dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
  296. if (!dep)
  297. return -EINVAL;
  298. if (dep->flags & DWC3_EP_STALL)
  299. usb_status = 1 << USB_ENDPOINT_HALT;
  300. break;
  301. default:
  302. return -EINVAL;
  303. }
  304. response_pkt = (__le16 *) dwc->setup_buf;
  305. *response_pkt = cpu_to_le16(usb_status);
  306. dep = dwc->eps[0];
  307. dwc->ep0_usb_req.dep = dep;
  308. dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
  309. dwc->ep0_usb_req.request.buf = dwc->setup_buf;
  310. dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
  311. return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
  312. }
  313. static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
  314. struct usb_ctrlrequest *ctrl, int set)
  315. {
  316. struct dwc3_ep *dep;
  317. u32 recip;
  318. u32 wValue;
  319. u32 wIndex;
  320. u32 reg;
  321. int ret;
  322. enum usb_device_state state;
  323. wValue = le16_to_cpu(ctrl->wValue);
  324. wIndex = le16_to_cpu(ctrl->wIndex);
  325. recip = ctrl->bRequestType & USB_RECIP_MASK;
  326. state = dwc->gadget.state;
  327. switch (recip) {
  328. case USB_RECIP_DEVICE:
  329. switch (wValue) {
  330. case USB_DEVICE_REMOTE_WAKEUP:
  331. break;
  332. /*
  333. * 9.4.1 says only only for SS, in AddressState only for
  334. * default control pipe
  335. */
  336. case USB_DEVICE_U1_ENABLE:
  337. if (state != USB_STATE_CONFIGURED)
  338. return -EINVAL;
  339. if (dwc->speed != DWC3_DSTS_SUPERSPEED)
  340. return -EINVAL;
  341. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  342. if (set)
  343. reg |= DWC3_DCTL_INITU1ENA;
  344. else
  345. reg &= ~DWC3_DCTL_INITU1ENA;
  346. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  347. break;
  348. case USB_DEVICE_U2_ENABLE:
  349. if (state != USB_STATE_CONFIGURED)
  350. return -EINVAL;
  351. if (dwc->speed != DWC3_DSTS_SUPERSPEED)
  352. return -EINVAL;
  353. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  354. if (set)
  355. reg |= DWC3_DCTL_INITU2ENA;
  356. else
  357. reg &= ~DWC3_DCTL_INITU2ENA;
  358. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  359. break;
  360. case USB_DEVICE_LTM_ENABLE:
  361. return -EINVAL;
  362. case USB_DEVICE_TEST_MODE:
  363. if ((wIndex & 0xff) != 0)
  364. return -EINVAL;
  365. if (!set)
  366. return -EINVAL;
  367. dwc->test_mode_nr = wIndex >> 8;
  368. dwc->test_mode = true;
  369. break;
  370. default:
  371. return -EINVAL;
  372. }
  373. break;
  374. case USB_RECIP_INTERFACE:
  375. switch (wValue) {
  376. case USB_INTRF_FUNC_SUSPEND:
  377. if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
  378. /* XXX enable Low power suspend */
  379. ;
  380. if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
  381. /* XXX enable remote wakeup */
  382. ;
  383. break;
  384. default:
  385. return -EINVAL;
  386. }
  387. break;
  388. case USB_RECIP_ENDPOINT:
  389. switch (wValue) {
  390. case USB_ENDPOINT_HALT:
  391. dep = dwc3_wIndex_to_dep(dwc, wIndex);
  392. if (!dep)
  393. return -EINVAL;
  394. if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
  395. break;
  396. ret = __dwc3_gadget_ep_set_halt(dep, set, true);
  397. if (ret)
  398. return -EINVAL;
  399. break;
  400. default:
  401. return -EINVAL;
  402. }
  403. break;
  404. default:
  405. return -EINVAL;
  406. }
  407. return 0;
  408. }
  409. static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  410. {
  411. enum usb_device_state state = dwc->gadget.state;
  412. u32 addr;
  413. u32 reg;
  414. addr = le16_to_cpu(ctrl->wValue);
  415. if (addr > 127) {
  416. dev_dbg(dwc->dev, "invalid device address %d", addr);
  417. return -EINVAL;
  418. }
  419. if (state == USB_STATE_CONFIGURED) {
  420. dev_dbg(dwc->dev, "trying to set address when configured");
  421. return -EINVAL;
  422. }
  423. reg = dwc3_readl(dwc->regs, DWC3_DCFG);
  424. reg &= ~(DWC3_DCFG_DEVADDR_MASK);
  425. reg |= DWC3_DCFG_DEVADDR(addr);
  426. dwc3_writel(dwc->regs, DWC3_DCFG, reg);
  427. if (addr)
  428. usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
  429. else
  430. usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
  431. return 0;
  432. }
  433. static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  434. {
  435. int ret;
  436. spin_unlock(&dwc->lock);
  437. ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
  438. spin_lock(&dwc->lock);
  439. return ret;
  440. }
  441. static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  442. {
  443. enum usb_device_state state = dwc->gadget.state;
  444. u32 cfg;
  445. int ret;
  446. u32 reg;
  447. dwc->start_config_issued = false;
  448. cfg = le16_to_cpu(ctrl->wValue);
  449. switch (state) {
  450. case USB_STATE_DEFAULT:
  451. return -EINVAL;
  452. case USB_STATE_ADDRESS:
  453. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  454. /* if the cfg matches and the cfg is non zero */
  455. if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
  456. /*
  457. * only change state if set_config has already
  458. * been processed. If gadget driver returns
  459. * USB_GADGET_DELAYED_STATUS, we will wait
  460. * to change the state on the next usb_ep_queue()
  461. */
  462. if (ret == 0)
  463. usb_gadget_set_state(&dwc->gadget,
  464. USB_STATE_CONFIGURED);
  465. /*
  466. * Enable transition to U1/U2 state when
  467. * nothing is pending from application.
  468. */
  469. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  470. reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
  471. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  472. dwc->resize_fifos = true;
  473. dev_dbg(dwc->dev, "resize FIFOs flag SET");
  474. }
  475. break;
  476. case USB_STATE_CONFIGURED:
  477. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  478. if (!cfg && !ret)
  479. usb_gadget_set_state(&dwc->gadget,
  480. USB_STATE_ADDRESS);
  481. break;
  482. default:
  483. ret = -EINVAL;
  484. }
  485. return ret;
  486. }
  487. static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
  488. {
  489. struct dwc3_ep *dep = to_dwc3_ep(ep);
  490. struct dwc3 *dwc = dep->dwc;
  491. u32 param = 0;
  492. u32 reg;
  493. struct timing {
  494. u8 u1sel;
  495. u8 u1pel;
  496. u16 u2sel;
  497. u16 u2pel;
  498. } __packed timing;
  499. int ret;
  500. memcpy(&timing, req->buf, sizeof(timing));
  501. dwc->u1sel = timing.u1sel;
  502. dwc->u1pel = timing.u1pel;
  503. dwc->u2sel = le16_to_cpu(timing.u2sel);
  504. dwc->u2pel = le16_to_cpu(timing.u2pel);
  505. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  506. if (reg & DWC3_DCTL_INITU2ENA)
  507. param = dwc->u2pel;
  508. if (reg & DWC3_DCTL_INITU1ENA)
  509. param = dwc->u1pel;
  510. /*
  511. * According to Synopsys Databook, if parameter is
  512. * greater than 125, a value of zero should be
  513. * programmed in the register.
  514. */
  515. if (param > 125)
  516. param = 0;
  517. /* now that we have the time, issue DGCMD Set Sel */
  518. ret = dwc3_send_gadget_generic_command(dwc,
  519. DWC3_DGCMD_SET_PERIODIC_PAR, param);
  520. WARN_ON(ret < 0);
  521. }
  522. static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  523. {
  524. struct dwc3_ep *dep;
  525. enum usb_device_state state = dwc->gadget.state;
  526. u16 wLength;
  527. if (state == USB_STATE_DEFAULT)
  528. return -EINVAL;
  529. wLength = le16_to_cpu(ctrl->wLength);
  530. if (wLength != 6) {
  531. dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
  532. wLength);
  533. return -EINVAL;
  534. }
  535. /*
  536. * To handle Set SEL we need to receive 6 bytes from Host. So let's
  537. * queue a usb_request for 6 bytes.
  538. *
  539. * Remember, though, this controller can't handle non-wMaxPacketSize
  540. * aligned transfers on the OUT direction, so we queue a request for
  541. * wMaxPacketSize instead.
  542. */
  543. dep = dwc->eps[0];
  544. dwc->ep0_usb_req.dep = dep;
  545. dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
  546. dwc->ep0_usb_req.request.buf = dwc->setup_buf;
  547. dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
  548. return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
  549. }
  550. static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  551. {
  552. u16 wLength;
  553. u16 wValue;
  554. u16 wIndex;
  555. wValue = le16_to_cpu(ctrl->wValue);
  556. wLength = le16_to_cpu(ctrl->wLength);
  557. wIndex = le16_to_cpu(ctrl->wIndex);
  558. if (wIndex || wLength)
  559. return -EINVAL;
  560. /*
  561. * REVISIT It's unclear from Databook what to do with this
  562. * value. For now, just cache it.
  563. */
  564. dwc->isoch_delay = wValue;
  565. return 0;
  566. }
  567. static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  568. {
  569. int ret;
  570. switch (ctrl->bRequest) {
  571. case USB_REQ_GET_STATUS:
  572. dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
  573. ret = dwc3_ep0_handle_status(dwc, ctrl);
  574. break;
  575. case USB_REQ_CLEAR_FEATURE:
  576. dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
  577. ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
  578. break;
  579. case USB_REQ_SET_FEATURE:
  580. dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
  581. ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
  582. break;
  583. case USB_REQ_SET_ADDRESS:
  584. dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
  585. ret = dwc3_ep0_set_address(dwc, ctrl);
  586. break;
  587. case USB_REQ_SET_CONFIGURATION:
  588. dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
  589. ret = dwc3_ep0_set_config(dwc, ctrl);
  590. break;
  591. case USB_REQ_SET_SEL:
  592. dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
  593. ret = dwc3_ep0_set_sel(dwc, ctrl);
  594. break;
  595. case USB_REQ_SET_ISOCH_DELAY:
  596. dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
  597. ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
  598. break;
  599. default:
  600. dev_vdbg(dwc->dev, "Forwarding to gadget driver");
  601. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  602. break;
  603. }
  604. return ret;
  605. }
  606. static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
  607. const struct dwc3_event_depevt *event)
  608. {
  609. struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
  610. int ret = -EINVAL;
  611. u32 len;
  612. if (!dwc->gadget_driver)
  613. goto out;
  614. len = le16_to_cpu(ctrl->wLength);
  615. if (!len) {
  616. dwc->three_stage_setup = false;
  617. dwc->ep0_expect_in = false;
  618. dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
  619. } else {
  620. dwc->three_stage_setup = true;
  621. dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
  622. dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
  623. }
  624. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
  625. ret = dwc3_ep0_std_request(dwc, ctrl);
  626. else
  627. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  628. if (ret == USB_GADGET_DELAYED_STATUS)
  629. dwc->delayed_status = true;
  630. out:
  631. if (ret < 0)
  632. dwc3_ep0_stall_and_restart(dwc);
  633. }
  634. static void dwc3_ep0_complete_data(struct dwc3 *dwc,
  635. const struct dwc3_event_depevt *event)
  636. {
  637. struct dwc3_request *r = NULL;
  638. struct usb_request *ur;
  639. struct dwc3_trb *trb;
  640. struct dwc3_ep *ep0;
  641. unsigned transfer_size = 0;
  642. unsigned maxp;
  643. void *buf;
  644. u32 transferred = 0;
  645. u32 status;
  646. u32 length;
  647. u8 epnum;
  648. epnum = event->endpoint_number;
  649. ep0 = dwc->eps[0];
  650. dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
  651. trb = dwc->ep0_trb;
  652. r = next_request(&ep0->request_list);
  653. if (!r)
  654. return;
  655. dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
  656. status = DWC3_TRB_SIZE_TRBSTS(trb->size);
  657. if (status == DWC3_TRBSTS_SETUP_PENDING) {
  658. dev_dbg(dwc->dev, "Setup Pending received");
  659. if (r)
  660. dwc3_gadget_giveback(ep0, r, -ECONNRESET);
  661. return;
  662. }
  663. ur = &r->request;
  664. buf = ur->buf;
  665. length = trb->size & DWC3_TRB_SIZE_MASK;
  666. maxp = ep0->endpoint.maxpacket;
  667. if (dwc->ep0_bounced) {
  668. /*
  669. * Handle the first TRB before handling the bounce buffer if
  670. * the request length is greater than the bounce buffer size.
  671. */
  672. if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
  673. transfer_size = (ur->length / maxp) * maxp;
  674. transferred = transfer_size - length;
  675. buf = (u8 *)buf + transferred;
  676. ur->actual += transferred;
  677. trb++;
  678. dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
  679. length = trb->size & DWC3_TRB_SIZE_MASK;
  680. ep0->free_slot = 0;
  681. }
  682. transfer_size = roundup((ur->length - transfer_size),
  683. maxp);
  684. transferred = min_t(u32, ur->length - transferred,
  685. transfer_size - length);
  686. dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
  687. memcpy(buf, dwc->ep0_bounce, transferred);
  688. } else {
  689. transferred = ur->length - length;
  690. }
  691. ur->actual += transferred;
  692. if ((epnum & 1) && ur->actual < ur->length) {
  693. /* for some reason we did not get everything out */
  694. dwc3_ep0_stall_and_restart(dwc);
  695. } else {
  696. dwc3_gadget_giveback(ep0, r, 0);
  697. if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
  698. ur->length && ur->zero) {
  699. int ret;
  700. dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  701. ret = dwc3_ep0_start_trans(dwc, epnum,
  702. dwc->ctrl_req_addr, 0,
  703. DWC3_TRBCTL_CONTROL_DATA, 0);
  704. WARN_ON(ret < 0);
  705. }
  706. }
  707. }
  708. static void dwc3_ep0_complete_status(struct dwc3 *dwc,
  709. const struct dwc3_event_depevt *event)
  710. {
  711. struct dwc3_request *r;
  712. struct dwc3_ep *dep;
  713. struct dwc3_trb *trb;
  714. u32 status;
  715. dep = dwc->eps[0];
  716. trb = dwc->ep0_trb;
  717. if (!list_empty(&dep->request_list)) {
  718. r = next_request(&dep->request_list);
  719. dwc3_gadget_giveback(dep, r, 0);
  720. }
  721. if (dwc->test_mode) {
  722. int ret;
  723. ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
  724. if (ret < 0) {
  725. dev_dbg(dwc->dev, "Invalid Test #%d",
  726. dwc->test_mode_nr);
  727. dwc3_ep0_stall_and_restart(dwc);
  728. return;
  729. }
  730. }
  731. status = DWC3_TRB_SIZE_TRBSTS(trb->size);
  732. if (status == DWC3_TRBSTS_SETUP_PENDING)
  733. dev_dbg(dwc->dev, "Setup Pending received");
  734. dwc->ep0state = EP0_SETUP_PHASE;
  735. dwc3_ep0_out_start(dwc);
  736. }
  737. static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
  738. const struct dwc3_event_depevt *event)
  739. {
  740. struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
  741. dep->flags &= ~DWC3_EP_BUSY;
  742. dep->resource_index = 0;
  743. dwc->setup_packet_pending = false;
  744. switch (dwc->ep0state) {
  745. case EP0_SETUP_PHASE:
  746. dev_vdbg(dwc->dev, "Setup Phase");
  747. dwc3_ep0_inspect_setup(dwc, event);
  748. break;
  749. case EP0_DATA_PHASE:
  750. dev_vdbg(dwc->dev, "Data Phase");
  751. dwc3_ep0_complete_data(dwc, event);
  752. break;
  753. case EP0_STATUS_PHASE:
  754. dev_vdbg(dwc->dev, "Status Phase");
  755. dwc3_ep0_complete_status(dwc, event);
  756. break;
  757. default:
  758. WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
  759. }
  760. }
  761. static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  762. struct dwc3_ep *dep, struct dwc3_request *req)
  763. {
  764. int ret;
  765. req->direction = !!dep->number;
  766. if (req->request.length == 0) {
  767. ret = dwc3_ep0_start_trans(dwc, dep->number,
  768. dwc->ctrl_req_addr, 0,
  769. DWC3_TRBCTL_CONTROL_DATA, 0);
  770. } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
  771. (dep->number == 0)) {
  772. u32 transfer_size = 0;
  773. u32 maxpacket;
  774. ret = usb_gadget_map_request(&dwc->gadget, &req->request,
  775. dep->number);
  776. if (ret) {
  777. dev_dbg(dwc->dev, "failed to map request\n");
  778. return;
  779. }
  780. maxpacket = dep->endpoint.maxpacket;
  781. if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
  782. transfer_size = (req->request.length / maxpacket) *
  783. maxpacket;
  784. ret = dwc3_ep0_start_trans(dwc, dep->number,
  785. req->request.dma,
  786. transfer_size,
  787. DWC3_TRBCTL_CONTROL_DATA, 1);
  788. }
  789. transfer_size = roundup((req->request.length - transfer_size),
  790. maxpacket);
  791. dwc->ep0_bounced = true;
  792. /*
  793. * REVISIT in case request length is bigger than
  794. * DWC3_EP0_BOUNCE_SIZE we will need two chained
  795. * TRBs to handle the transfer.
  796. */
  797. ret = dwc3_ep0_start_trans(dwc, dep->number,
  798. dwc->ep0_bounce_addr, transfer_size,
  799. DWC3_TRBCTL_CONTROL_DATA, 0);
  800. } else {
  801. ret = usb_gadget_map_request(&dwc->gadget, &req->request,
  802. dep->number);
  803. if (ret) {
  804. dev_dbg(dwc->dev, "failed to map request\n");
  805. return;
  806. }
  807. ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
  808. req->request.length,
  809. DWC3_TRBCTL_CONTROL_DATA, 0);
  810. }
  811. WARN_ON(ret < 0);
  812. }
  813. static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
  814. {
  815. struct dwc3 *dwc = dep->dwc;
  816. u32 type;
  817. type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
  818. : DWC3_TRBCTL_CONTROL_STATUS2;
  819. return dwc3_ep0_start_trans(dwc, dep->number,
  820. dwc->ctrl_req_addr, 0, type, 0);
  821. }
  822. static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
  823. {
  824. if (dwc->resize_fifos) {
  825. dev_dbg(dwc->dev, "Resizing FIFOs");
  826. dwc3_gadget_resize_tx_fifos(dwc);
  827. dwc->resize_fifos = 0;
  828. }
  829. WARN_ON(dwc3_ep0_start_control_status(dep));
  830. }
  831. static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
  832. const struct dwc3_event_depevt *event)
  833. {
  834. struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
  835. __dwc3_ep0_do_control_status(dwc, dep);
  836. }
  837. static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
  838. {
  839. struct dwc3_gadget_ep_cmd_params params;
  840. u32 cmd;
  841. int ret;
  842. if (!dep->resource_index)
  843. return;
  844. cmd = DWC3_DEPCMD_ENDTRANSFER;
  845. cmd |= DWC3_DEPCMD_CMDIOC;
  846. cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
  847. memset(&params, 0, sizeof(params));
  848. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
  849. WARN_ON_ONCE(ret);
  850. dep->resource_index = 0;
  851. }
  852. static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
  853. const struct dwc3_event_depevt *event)
  854. {
  855. dwc->setup_packet_pending = true;
  856. switch (event->status) {
  857. case DEPEVT_STATUS_CONTROL_DATA:
  858. dev_vdbg(dwc->dev, "Control Data");
  859. /*
  860. * We already have a DATA transfer in the controller's cache,
  861. * if we receive a XferNotReady(DATA) we will ignore it, unless
  862. * it's for the wrong direction.
  863. *
  864. * In that case, we must issue END_TRANSFER command to the Data
  865. * Phase we already have started and issue SetStall on the
  866. * control endpoint.
  867. */
  868. if (dwc->ep0_expect_in != event->endpoint_number) {
  869. struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
  870. dev_vdbg(dwc->dev, "Wrong direction for Data phase");
  871. dwc3_ep0_end_control_data(dwc, dep);
  872. dwc3_ep0_stall_and_restart(dwc);
  873. return;
  874. }
  875. break;
  876. case DEPEVT_STATUS_CONTROL_STATUS:
  877. if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
  878. return;
  879. dev_vdbg(dwc->dev, "Control Status");
  880. dwc->ep0state = EP0_STATUS_PHASE;
  881. if (dwc->delayed_status) {
  882. WARN_ON_ONCE(event->endpoint_number != 1);
  883. dev_vdbg(dwc->dev, "Delayed Status");
  884. return;
  885. }
  886. dwc3_ep0_do_control_status(dwc, event);
  887. }
  888. }
  889. void dwc3_ep0_interrupt(struct dwc3 *dwc,
  890. const struct dwc3_event_depevt *event)
  891. {
  892. u8 epnum = event->endpoint_number;
  893. dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
  894. dwc3_ep_event_string(event->endpoint_event),
  895. epnum >> 1, (epnum & 1) ? "in" : "out",
  896. dwc3_ep0_state_string(dwc->ep0state));
  897. switch (event->endpoint_event) {
  898. case DWC3_DEPEVT_XFERCOMPLETE:
  899. dwc3_ep0_xfer_complete(dwc, event);
  900. break;
  901. case DWC3_DEPEVT_XFERNOTREADY:
  902. dwc3_ep0_xfernotready(dwc, event);
  903. break;
  904. case DWC3_DEPEVT_XFERINPROGRESS:
  905. case DWC3_DEPEVT_RXTXFIFOEVT:
  906. case DWC3_DEPEVT_STREAMEVT:
  907. case DWC3_DEPEVT_EPCMDCMPLT:
  908. break;
  909. }
  910. }