pinctrl-uniphier.h 4.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015-2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #ifndef __PINCTRL_UNIPHIER_H__
  7. #define __PINCTRL_UNIPHIER_H__
  8. #include <linux/bitops.h>
  9. #include <linux/bug.h>
  10. #include <linux/build_bug.h>
  11. #include <linux/kernel.h>
  12. #include <linux/types.h>
  13. /* drive strength control register number */
  14. #define UNIPHIER_PIN_DRVCTRL_SHIFT 0
  15. #define UNIPHIER_PIN_DRVCTRL_BITS 9
  16. #define UNIPHIER_PIN_DRVCTRL_MASK ((1U << (UNIPHIER_PIN_DRVCTRL_BITS)) \
  17. - 1)
  18. /* drive control type */
  19. #define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
  20. (UNIPHIER_PIN_DRVCTRL_BITS))
  21. #define UNIPHIER_PIN_DRV_TYPE_BITS 2
  22. #define UNIPHIER_PIN_DRV_TYPE_MASK ((1U << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
  23. - 1)
  24. /* drive control type */
  25. enum uniphier_pin_drv_type {
  26. UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
  27. UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
  28. UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
  29. };
  30. #define UNIPHIER_PIN_DRVCTRL(x) \
  31. (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
  32. #define UNIPHIER_PIN_DRV_TYPE(x) \
  33. (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
  34. #define UNIPHIER_PIN_ATTR_PACKED(drvctrl, drv_type) \
  35. UNIPHIER_PIN_DRVCTRL(drvctrl) | \
  36. UNIPHIER_PIN_DRV_TYPE(drv_type)
  37. static inline unsigned int uniphier_pin_get_drvctrl(unsigned int data)
  38. {
  39. return (data >> UNIPHIER_PIN_DRVCTRL_SHIFT) & UNIPHIER_PIN_DRVCTRL_MASK;
  40. }
  41. static inline unsigned int uniphier_pin_get_drv_type(unsigned int data)
  42. {
  43. return (data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
  44. UNIPHIER_PIN_DRV_TYPE_MASK;
  45. }
  46. /**
  47. * struct uniphier_pinctrl_pin - pin data for UniPhier SoC
  48. *
  49. * @number: pin number
  50. * @data: additional per-pin data
  51. */
  52. struct uniphier_pinctrl_pin {
  53. unsigned number;
  54. const char *name;
  55. unsigned int data;
  56. };
  57. /**
  58. * struct uniphier_pinctrl_group - pin group data for UniPhier SoC
  59. *
  60. * @name: pin group name
  61. * @pins: array of pins that belong to the group
  62. * @num_pins: number of pins in the group
  63. * @muxvals: array of values to be set to pinmux registers
  64. */
  65. struct uniphier_pinctrl_group {
  66. const char *name;
  67. const unsigned *pins;
  68. unsigned num_pins;
  69. const int *muxvals;
  70. };
  71. /**
  72. * struct uniphier_pinctrl_socdata - SoC data for UniPhier pin controller
  73. *
  74. * @pins: array of pin data
  75. * @pins_count: number of pin data
  76. * @groups: array of pin group data
  77. * @groups_count: number of pin group data
  78. * @functions: array of pinmux function names
  79. * @functions_count: number of pinmux functions
  80. * @mux_bits: bit width of each pinmux register
  81. * @reg_stride: stride of pinmux register address
  82. * @caps: SoC-specific capability flag
  83. */
  84. struct uniphier_pinctrl_socdata {
  85. const struct uniphier_pinctrl_pin *pins;
  86. int pins_count;
  87. const struct uniphier_pinctrl_group *groups;
  88. int groups_count;
  89. const char * const *functions;
  90. int functions_count;
  91. unsigned caps;
  92. #define UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE BIT(3)
  93. #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(2)
  94. #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(1)
  95. #define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0)
  96. };
  97. #define UNIPHIER_PINCTRL_PIN(a, b, c, d) \
  98. { \
  99. .number = a, \
  100. .name = b, \
  101. .data = UNIPHIER_PIN_ATTR_PACKED(c, d), \
  102. }
  103. #define __UNIPHIER_PINCTRL_GROUP(grp) \
  104. { \
  105. .name = #grp, \
  106. .pins = grp##_pins, \
  107. .num_pins = ARRAY_SIZE(grp##_pins), \
  108. .muxvals = grp##_muxvals + \
  109. BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
  110. ARRAY_SIZE(grp##_muxvals)), \
  111. }
  112. #define __UNIPHIER_PINMUX_FUNCTION(func) #func
  113. #ifdef CONFIG_SPL_BUILD
  114. /*
  115. * a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL,
  116. * suppressing "defined but not used" warnings.
  117. */
  118. #define UNIPHIER_PINCTRL_GROUP(grp) \
  119. { .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) }
  120. #define UNIPHIER_PINMUX_FUNCTION(func) NULL
  121. #else
  122. #define UNIPHIER_PINCTRL_GROUP(grp) __UNIPHIER_PINCTRL_GROUP(grp)
  123. #define UNIPHIER_PINMUX_FUNCTION(func) __UNIPHIER_PINMUX_FUNCTION(func)
  124. #endif
  125. #define UNIPHIER_PINCTRL_GROUP_SPL(grp) __UNIPHIER_PINCTRL_GROUP(grp)
  126. #define UNIPHIER_PINMUX_FUNCTION_SPL(func) __UNIPHIER_PINMUX_FUNCTION(func)
  127. /**
  128. * struct uniphier_pinctrl_priv - private data for UniPhier pinctrl driver
  129. *
  130. * @base: base address of the pinctrl device
  131. * @socdata: SoC specific data
  132. */
  133. struct uniphier_pinctrl_priv {
  134. void __iomem *base;
  135. struct uniphier_pinctrl_socdata *socdata;
  136. };
  137. extern const struct pinctrl_ops uniphier_pinctrl_ops;
  138. int uniphier_pinctrl_probe(struct udevice *dev,
  139. struct uniphier_pinctrl_socdata *socdata);
  140. #endif /* __PINCTRL_UNIPHIER_H__ */