nand_base.c 135 KB

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  1. /*
  2. * Overview:
  3. * This is the generic MTD driver for NAND flash devices. It should be
  4. * capable of working with almost all NAND chips currently available.
  5. *
  6. * Additional technical information is available on
  7. * http://www.linux-mtd.infradead.org/doc/nand.html
  8. *
  9. * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  10. * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
  11. *
  12. * Credits:
  13. * David Woodhouse for adding multichip support
  14. *
  15. * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  16. * rework for 2K page size chips
  17. *
  18. * TODO:
  19. * Enable cached programming for 2k page size chips
  20. * Check, if mtd->ecctype should be set to MTD_ECC_HW
  21. * if we have HW ECC support.
  22. * BBT table is not serialized, has to be fixed
  23. *
  24. * This program is free software; you can redistribute it and/or modify
  25. * it under the terms of the GNU General Public License version 2 as
  26. * published by the Free Software Foundation.
  27. *
  28. */
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <common.h>
  31. #if CONFIG_IS_ENABLED(OF_CONTROL)
  32. #include <fdtdec.h>
  33. #endif
  34. #include <log.h>
  35. #include <malloc.h>
  36. #include <watchdog.h>
  37. #include <dm/devres.h>
  38. #include <linux/bug.h>
  39. #include <linux/err.h>
  40. #include <linux/compat.h>
  41. #include <linux/mtd/mtd.h>
  42. #include <linux/mtd/rawnand.h>
  43. #include <linux/mtd/nand_ecc.h>
  44. #include <linux/mtd/nand_bch.h>
  45. #ifdef CONFIG_MTD_PARTITIONS
  46. #include <linux/mtd/partitions.h>
  47. #endif
  48. #include <asm/io.h>
  49. #include <linux/errno.h>
  50. /* Define default oob placement schemes for large and small page devices */
  51. #ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
  52. static struct nand_ecclayout nand_oob_8 = {
  53. .eccbytes = 3,
  54. .eccpos = {0, 1, 2},
  55. .oobfree = {
  56. {.offset = 3,
  57. .length = 2},
  58. {.offset = 6,
  59. .length = 2} }
  60. };
  61. static struct nand_ecclayout nand_oob_16 = {
  62. .eccbytes = 6,
  63. .eccpos = {0, 1, 2, 3, 6, 7},
  64. .oobfree = {
  65. {.offset = 8,
  66. . length = 8} }
  67. };
  68. static struct nand_ecclayout nand_oob_64 = {
  69. .eccbytes = 24,
  70. .eccpos = {
  71. 40, 41, 42, 43, 44, 45, 46, 47,
  72. 48, 49, 50, 51, 52, 53, 54, 55,
  73. 56, 57, 58, 59, 60, 61, 62, 63},
  74. .oobfree = {
  75. {.offset = 2,
  76. .length = 38} }
  77. };
  78. static struct nand_ecclayout nand_oob_128 = {
  79. .eccbytes = 48,
  80. .eccpos = {
  81. 80, 81, 82, 83, 84, 85, 86, 87,
  82. 88, 89, 90, 91, 92, 93, 94, 95,
  83. 96, 97, 98, 99, 100, 101, 102, 103,
  84. 104, 105, 106, 107, 108, 109, 110, 111,
  85. 112, 113, 114, 115, 116, 117, 118, 119,
  86. 120, 121, 122, 123, 124, 125, 126, 127},
  87. .oobfree = {
  88. {.offset = 2,
  89. .length = 78} }
  90. };
  91. #endif
  92. static int nand_get_device(struct mtd_info *mtd, int new_state);
  93. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  94. struct mtd_oob_ops *ops);
  95. /*
  96. * For devices which display every fart in the system on a separate LED. Is
  97. * compiled away when LED support is disabled.
  98. */
  99. DEFINE_LED_TRIGGER(nand_led_trigger);
  100. static int check_offs_len(struct mtd_info *mtd,
  101. loff_t ofs, uint64_t len)
  102. {
  103. struct nand_chip *chip = mtd_to_nand(mtd);
  104. int ret = 0;
  105. /* Start address must align on block boundary */
  106. if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
  107. pr_debug("%s: unaligned address\n", __func__);
  108. ret = -EINVAL;
  109. }
  110. /* Length must align on block boundary */
  111. if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
  112. pr_debug("%s: length not block aligned\n", __func__);
  113. ret = -EINVAL;
  114. }
  115. return ret;
  116. }
  117. /**
  118. * nand_release_device - [GENERIC] release chip
  119. * @mtd: MTD device structure
  120. *
  121. * Release chip lock and wake up anyone waiting on the device.
  122. */
  123. static void nand_release_device(struct mtd_info *mtd)
  124. {
  125. struct nand_chip *chip = mtd_to_nand(mtd);
  126. /* De-select the NAND device */
  127. chip->select_chip(mtd, -1);
  128. }
  129. /**
  130. * nand_read_byte - [DEFAULT] read one byte from the chip
  131. * @mtd: MTD device structure
  132. *
  133. * Default read function for 8bit buswidth
  134. */
  135. uint8_t nand_read_byte(struct mtd_info *mtd)
  136. {
  137. struct nand_chip *chip = mtd_to_nand(mtd);
  138. return readb(chip->IO_ADDR_R);
  139. }
  140. /**
  141. * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
  142. * @mtd: MTD device structure
  143. *
  144. * Default read function for 16bit buswidth with endianness conversion.
  145. *
  146. */
  147. static uint8_t nand_read_byte16(struct mtd_info *mtd)
  148. {
  149. struct nand_chip *chip = mtd_to_nand(mtd);
  150. return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
  151. }
  152. /**
  153. * nand_read_word - [DEFAULT] read one word from the chip
  154. * @mtd: MTD device structure
  155. *
  156. * Default read function for 16bit buswidth without endianness conversion.
  157. */
  158. static u16 nand_read_word(struct mtd_info *mtd)
  159. {
  160. struct nand_chip *chip = mtd_to_nand(mtd);
  161. return readw(chip->IO_ADDR_R);
  162. }
  163. /**
  164. * nand_select_chip - [DEFAULT] control CE line
  165. * @mtd: MTD device structure
  166. * @chipnr: chipnumber to select, -1 for deselect
  167. *
  168. * Default select function for 1 chip devices.
  169. */
  170. static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  171. {
  172. struct nand_chip *chip = mtd_to_nand(mtd);
  173. switch (chipnr) {
  174. case -1:
  175. chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  176. break;
  177. case 0:
  178. break;
  179. default:
  180. BUG();
  181. }
  182. }
  183. /**
  184. * nand_write_byte - [DEFAULT] write single byte to chip
  185. * @mtd: MTD device structure
  186. * @byte: value to write
  187. *
  188. * Default function to write a byte to I/O[7:0]
  189. */
  190. static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
  191. {
  192. struct nand_chip *chip = mtd_to_nand(mtd);
  193. chip->write_buf(mtd, &byte, 1);
  194. }
  195. /**
  196. * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
  197. * @mtd: MTD device structure
  198. * @byte: value to write
  199. *
  200. * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
  201. */
  202. static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
  203. {
  204. struct nand_chip *chip = mtd_to_nand(mtd);
  205. uint16_t word = byte;
  206. /*
  207. * It's not entirely clear what should happen to I/O[15:8] when writing
  208. * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
  209. *
  210. * When the host supports a 16-bit bus width, only data is
  211. * transferred at the 16-bit width. All address and command line
  212. * transfers shall use only the lower 8-bits of the data bus. During
  213. * command transfers, the host may place any value on the upper
  214. * 8-bits of the data bus. During address transfers, the host shall
  215. * set the upper 8-bits of the data bus to 00h.
  216. *
  217. * One user of the write_byte callback is nand_onfi_set_features. The
  218. * four parameters are specified to be written to I/O[7:0], but this is
  219. * neither an address nor a command transfer. Let's assume a 0 on the
  220. * upper I/O lines is OK.
  221. */
  222. chip->write_buf(mtd, (uint8_t *)&word, 2);
  223. }
  224. static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
  225. {
  226. int i;
  227. for (i = 0; i < len; i++)
  228. writeb(buf[i], addr);
  229. }
  230. static void ioread8_rep(void *addr, uint8_t *buf, int len)
  231. {
  232. int i;
  233. for (i = 0; i < len; i++)
  234. buf[i] = readb(addr);
  235. }
  236. static void ioread16_rep(void *addr, void *buf, int len)
  237. {
  238. int i;
  239. u16 *p = (u16 *) buf;
  240. for (i = 0; i < len; i++)
  241. p[i] = readw(addr);
  242. }
  243. static void iowrite16_rep(void *addr, void *buf, int len)
  244. {
  245. int i;
  246. u16 *p = (u16 *) buf;
  247. for (i = 0; i < len; i++)
  248. writew(p[i], addr);
  249. }
  250. /**
  251. * nand_write_buf - [DEFAULT] write buffer to chip
  252. * @mtd: MTD device structure
  253. * @buf: data buffer
  254. * @len: number of bytes to write
  255. *
  256. * Default write function for 8bit buswidth.
  257. */
  258. void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  259. {
  260. struct nand_chip *chip = mtd_to_nand(mtd);
  261. iowrite8_rep(chip->IO_ADDR_W, buf, len);
  262. }
  263. /**
  264. * nand_read_buf - [DEFAULT] read chip data into buffer
  265. * @mtd: MTD device structure
  266. * @buf: buffer to store date
  267. * @len: number of bytes to read
  268. *
  269. * Default read function for 8bit buswidth.
  270. */
  271. void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  272. {
  273. struct nand_chip *chip = mtd_to_nand(mtd);
  274. ioread8_rep(chip->IO_ADDR_R, buf, len);
  275. }
  276. /**
  277. * nand_write_buf16 - [DEFAULT] write buffer to chip
  278. * @mtd: MTD device structure
  279. * @buf: data buffer
  280. * @len: number of bytes to write
  281. *
  282. * Default write function for 16bit buswidth.
  283. */
  284. void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
  285. {
  286. struct nand_chip *chip = mtd_to_nand(mtd);
  287. u16 *p = (u16 *) buf;
  288. iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
  289. }
  290. /**
  291. * nand_read_buf16 - [DEFAULT] read chip data into buffer
  292. * @mtd: MTD device structure
  293. * @buf: buffer to store date
  294. * @len: number of bytes to read
  295. *
  296. * Default read function for 16bit buswidth.
  297. */
  298. void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  299. {
  300. struct nand_chip *chip = mtd_to_nand(mtd);
  301. u16 *p = (u16 *) buf;
  302. ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
  303. }
  304. /**
  305. * nand_block_bad - [DEFAULT] Read bad block marker from the chip
  306. * @mtd: MTD device structure
  307. * @ofs: offset from device start
  308. *
  309. * Check, if the block is bad.
  310. */
  311. static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
  312. {
  313. int page, res = 0, i = 0;
  314. struct nand_chip *chip = mtd_to_nand(mtd);
  315. u16 bad;
  316. if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
  317. ofs += mtd->erasesize - mtd->writesize;
  318. page = (int)(ofs >> chip->page_shift) & chip->pagemask;
  319. do {
  320. if (chip->options & NAND_BUSWIDTH_16) {
  321. chip->cmdfunc(mtd, NAND_CMD_READOOB,
  322. chip->badblockpos & 0xFE, page);
  323. bad = cpu_to_le16(chip->read_word(mtd));
  324. if (chip->badblockpos & 0x1)
  325. bad >>= 8;
  326. else
  327. bad &= 0xFF;
  328. } else {
  329. chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
  330. page);
  331. bad = chip->read_byte(mtd);
  332. }
  333. if (likely(chip->badblockbits == 8))
  334. res = bad != 0xFF;
  335. else
  336. res = hweight8(bad) < chip->badblockbits;
  337. ofs += mtd->writesize;
  338. page = (int)(ofs >> chip->page_shift) & chip->pagemask;
  339. i++;
  340. } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
  341. return res;
  342. }
  343. /**
  344. * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
  345. * @mtd: MTD device structure
  346. * @ofs: offset from device start
  347. *
  348. * This is the default implementation, which can be overridden by a hardware
  349. * specific driver. It provides the details for writing a bad block marker to a
  350. * block.
  351. */
  352. static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
  353. {
  354. struct nand_chip *chip = mtd_to_nand(mtd);
  355. struct mtd_oob_ops ops;
  356. uint8_t buf[2] = { 0, 0 };
  357. int ret = 0, res, i = 0;
  358. memset(&ops, 0, sizeof(ops));
  359. ops.oobbuf = buf;
  360. ops.ooboffs = chip->badblockpos;
  361. if (chip->options & NAND_BUSWIDTH_16) {
  362. ops.ooboffs &= ~0x01;
  363. ops.len = ops.ooblen = 2;
  364. } else {
  365. ops.len = ops.ooblen = 1;
  366. }
  367. ops.mode = MTD_OPS_PLACE_OOB;
  368. /* Write to first/last page(s) if necessary */
  369. if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
  370. ofs += mtd->erasesize - mtd->writesize;
  371. do {
  372. res = nand_do_write_oob(mtd, ofs, &ops);
  373. if (!ret)
  374. ret = res;
  375. i++;
  376. ofs += mtd->writesize;
  377. } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
  378. return ret;
  379. }
  380. /**
  381. * nand_block_markbad_lowlevel - mark a block bad
  382. * @mtd: MTD device structure
  383. * @ofs: offset from device start
  384. *
  385. * This function performs the generic NAND bad block marking steps (i.e., bad
  386. * block table(s) and/or marker(s)). We only allow the hardware driver to
  387. * specify how to write bad block markers to OOB (chip->block_markbad).
  388. *
  389. * We try operations in the following order:
  390. * (1) erase the affected block, to allow OOB marker to be written cleanly
  391. * (2) write bad block marker to OOB area of affected block (unless flag
  392. * NAND_BBT_NO_OOB_BBM is present)
  393. * (3) update the BBT
  394. * Note that we retain the first error encountered in (2) or (3), finish the
  395. * procedures, and dump the error in the end.
  396. */
  397. static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
  398. {
  399. struct nand_chip *chip = mtd_to_nand(mtd);
  400. int res, ret = 0;
  401. if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
  402. struct erase_info einfo;
  403. /* Attempt erase before marking OOB */
  404. memset(&einfo, 0, sizeof(einfo));
  405. einfo.mtd = mtd;
  406. einfo.addr = ofs;
  407. einfo.len = 1ULL << chip->phys_erase_shift;
  408. nand_erase_nand(mtd, &einfo, 0);
  409. /* Write bad block marker to OOB */
  410. nand_get_device(mtd, FL_WRITING);
  411. ret = chip->block_markbad(mtd, ofs);
  412. nand_release_device(mtd);
  413. }
  414. /* Mark block bad in BBT */
  415. if (chip->bbt) {
  416. res = nand_markbad_bbt(mtd, ofs);
  417. if (!ret)
  418. ret = res;
  419. }
  420. if (!ret)
  421. mtd->ecc_stats.badblocks++;
  422. return ret;
  423. }
  424. /**
  425. * nand_check_wp - [GENERIC] check if the chip is write protected
  426. * @mtd: MTD device structure
  427. *
  428. * Check, if the device is write protected. The function expects, that the
  429. * device is already selected.
  430. */
  431. static int nand_check_wp(struct mtd_info *mtd)
  432. {
  433. struct nand_chip *chip = mtd_to_nand(mtd);
  434. u8 status;
  435. int ret;
  436. /* Broken xD cards report WP despite being writable */
  437. if (chip->options & NAND_BROKEN_XD)
  438. return 0;
  439. /* Check the WP bit */
  440. ret = nand_status_op(chip, &status);
  441. if (ret)
  442. return ret;
  443. return status & NAND_STATUS_WP ? 0 : 1;
  444. }
  445. /**
  446. * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
  447. * @mtd: MTD device structure
  448. * @ofs: offset from device start
  449. *
  450. * Check if the block is marked as reserved.
  451. */
  452. static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
  453. {
  454. struct nand_chip *chip = mtd_to_nand(mtd);
  455. if (!chip->bbt)
  456. return 0;
  457. /* Return info from the table */
  458. return nand_isreserved_bbt(mtd, ofs);
  459. }
  460. /**
  461. * nand_block_checkbad - [GENERIC] Check if a block is marked bad
  462. * @mtd: MTD device structure
  463. * @ofs: offset from device start
  464. * @allowbbt: 1, if its allowed to access the bbt area
  465. *
  466. * Check, if the block is bad. Either by reading the bad block table or
  467. * calling of the scan function.
  468. */
  469. static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
  470. {
  471. struct nand_chip *chip = mtd_to_nand(mtd);
  472. if (!(chip->options & NAND_SKIP_BBTSCAN) &&
  473. !(chip->options & NAND_BBT_SCANNED)) {
  474. chip->options |= NAND_BBT_SCANNED;
  475. chip->scan_bbt(mtd);
  476. }
  477. if (!chip->bbt)
  478. return chip->block_bad(mtd, ofs);
  479. /* Return info from the table */
  480. return nand_isbad_bbt(mtd, ofs, allowbbt);
  481. }
  482. /**
  483. * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
  484. * @mtd: MTD device structure
  485. *
  486. * Wait for the ready pin after a command, and warn if a timeout occurs.
  487. */
  488. void nand_wait_ready(struct mtd_info *mtd)
  489. {
  490. struct nand_chip *chip = mtd_to_nand(mtd);
  491. u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
  492. u32 time_start;
  493. time_start = get_timer(0);
  494. /* Wait until command is processed or timeout occurs */
  495. while (get_timer(time_start) < timeo) {
  496. if (chip->dev_ready)
  497. if (chip->dev_ready(mtd))
  498. break;
  499. }
  500. if (!chip->dev_ready(mtd))
  501. pr_warn("timeout while waiting for chip to become ready\n");
  502. }
  503. EXPORT_SYMBOL_GPL(nand_wait_ready);
  504. /**
  505. * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
  506. * @mtd: MTD device structure
  507. * @timeo: Timeout in ms
  508. *
  509. * Wait for status ready (i.e. command done) or timeout.
  510. */
  511. static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
  512. {
  513. register struct nand_chip *chip = mtd_to_nand(mtd);
  514. u32 time_start;
  515. int ret;
  516. timeo = (CONFIG_SYS_HZ * timeo) / 1000;
  517. time_start = get_timer(0);
  518. while (get_timer(time_start) < timeo) {
  519. u8 status;
  520. ret = nand_read_data_op(chip, &status, sizeof(status), true);
  521. if (ret)
  522. return;
  523. if (status & NAND_STATUS_READY)
  524. break;
  525. WATCHDOG_RESET();
  526. }
  527. };
  528. /**
  529. * nand_command - [DEFAULT] Send command to NAND device
  530. * @mtd: MTD device structure
  531. * @command: the command to be sent
  532. * @column: the column address for this command, -1 if none
  533. * @page_addr: the page address for this command, -1 if none
  534. *
  535. * Send command to NAND device. This function is used for small page devices
  536. * (512 Bytes per page).
  537. */
  538. static void nand_command(struct mtd_info *mtd, unsigned int command,
  539. int column, int page_addr)
  540. {
  541. register struct nand_chip *chip = mtd_to_nand(mtd);
  542. int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
  543. /* Write out the command to the device */
  544. if (command == NAND_CMD_SEQIN) {
  545. int readcmd;
  546. if (column >= mtd->writesize) {
  547. /* OOB area */
  548. column -= mtd->writesize;
  549. readcmd = NAND_CMD_READOOB;
  550. } else if (column < 256) {
  551. /* First 256 bytes --> READ0 */
  552. readcmd = NAND_CMD_READ0;
  553. } else {
  554. column -= 256;
  555. readcmd = NAND_CMD_READ1;
  556. }
  557. chip->cmd_ctrl(mtd, readcmd, ctrl);
  558. ctrl &= ~NAND_CTRL_CHANGE;
  559. }
  560. chip->cmd_ctrl(mtd, command, ctrl);
  561. /* Address cycle, when necessary */
  562. ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
  563. /* Serially input address */
  564. if (column != -1) {
  565. /* Adjust columns for 16 bit buswidth */
  566. if (chip->options & NAND_BUSWIDTH_16 &&
  567. !nand_opcode_8bits(command))
  568. column >>= 1;
  569. chip->cmd_ctrl(mtd, column, ctrl);
  570. ctrl &= ~NAND_CTRL_CHANGE;
  571. }
  572. if (page_addr != -1) {
  573. chip->cmd_ctrl(mtd, page_addr, ctrl);
  574. ctrl &= ~NAND_CTRL_CHANGE;
  575. chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
  576. if (chip->options & NAND_ROW_ADDR_3)
  577. chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
  578. }
  579. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  580. /*
  581. * Program and erase have their own busy handlers status and sequential
  582. * in needs no delay
  583. */
  584. switch (command) {
  585. case NAND_CMD_PAGEPROG:
  586. case NAND_CMD_ERASE1:
  587. case NAND_CMD_ERASE2:
  588. case NAND_CMD_SEQIN:
  589. case NAND_CMD_STATUS:
  590. case NAND_CMD_READID:
  591. case NAND_CMD_SET_FEATURES:
  592. return;
  593. case NAND_CMD_RESET:
  594. if (chip->dev_ready)
  595. break;
  596. udelay(chip->chip_delay);
  597. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  598. NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  599. chip->cmd_ctrl(mtd,
  600. NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  601. /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
  602. nand_wait_status_ready(mtd, 250);
  603. return;
  604. /* This applies to read commands */
  605. default:
  606. /*
  607. * If we don't have access to the busy pin, we apply the given
  608. * command delay
  609. */
  610. if (!chip->dev_ready) {
  611. udelay(chip->chip_delay);
  612. return;
  613. }
  614. }
  615. /*
  616. * Apply this short delay always to ensure that we do wait tWB in
  617. * any case on any machine.
  618. */
  619. ndelay(100);
  620. nand_wait_ready(mtd);
  621. }
  622. /**
  623. * nand_command_lp - [DEFAULT] Send command to NAND large page device
  624. * @mtd: MTD device structure
  625. * @command: the command to be sent
  626. * @column: the column address for this command, -1 if none
  627. * @page_addr: the page address for this command, -1 if none
  628. *
  629. * Send command to NAND device. This is the version for the new large page
  630. * devices. We don't have the separate regions as we have in the small page
  631. * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
  632. */
  633. static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
  634. int column, int page_addr)
  635. {
  636. register struct nand_chip *chip = mtd_to_nand(mtd);
  637. /* Emulate NAND_CMD_READOOB */
  638. if (command == NAND_CMD_READOOB) {
  639. column += mtd->writesize;
  640. command = NAND_CMD_READ0;
  641. }
  642. /* Command latch cycle */
  643. chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  644. if (column != -1 || page_addr != -1) {
  645. int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
  646. /* Serially input address */
  647. if (column != -1) {
  648. /* Adjust columns for 16 bit buswidth */
  649. if (chip->options & NAND_BUSWIDTH_16 &&
  650. !nand_opcode_8bits(command))
  651. column >>= 1;
  652. chip->cmd_ctrl(mtd, column, ctrl);
  653. ctrl &= ~NAND_CTRL_CHANGE;
  654. chip->cmd_ctrl(mtd, column >> 8, ctrl);
  655. }
  656. if (page_addr != -1) {
  657. chip->cmd_ctrl(mtd, page_addr, ctrl);
  658. chip->cmd_ctrl(mtd, page_addr >> 8,
  659. NAND_NCE | NAND_ALE);
  660. if (chip->options & NAND_ROW_ADDR_3)
  661. chip->cmd_ctrl(mtd, page_addr >> 16,
  662. NAND_NCE | NAND_ALE);
  663. }
  664. }
  665. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  666. /*
  667. * Program and erase have their own busy handlers status, sequential
  668. * in and status need no delay.
  669. */
  670. switch (command) {
  671. case NAND_CMD_CACHEDPROG:
  672. case NAND_CMD_PAGEPROG:
  673. case NAND_CMD_ERASE1:
  674. case NAND_CMD_ERASE2:
  675. case NAND_CMD_SEQIN:
  676. case NAND_CMD_RNDIN:
  677. case NAND_CMD_STATUS:
  678. case NAND_CMD_READID:
  679. case NAND_CMD_SET_FEATURES:
  680. return;
  681. case NAND_CMD_RESET:
  682. if (chip->dev_ready)
  683. break;
  684. udelay(chip->chip_delay);
  685. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  686. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  687. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  688. NAND_NCE | NAND_CTRL_CHANGE);
  689. /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
  690. nand_wait_status_ready(mtd, 250);
  691. return;
  692. case NAND_CMD_RNDOUT:
  693. /* No ready / busy check necessary */
  694. chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
  695. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  696. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  697. NAND_NCE | NAND_CTRL_CHANGE);
  698. return;
  699. case NAND_CMD_READ0:
  700. chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
  701. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  702. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  703. NAND_NCE | NAND_CTRL_CHANGE);
  704. /* This applies to read commands */
  705. default:
  706. /*
  707. * If we don't have access to the busy pin, we apply the given
  708. * command delay.
  709. */
  710. if (!chip->dev_ready) {
  711. udelay(chip->chip_delay);
  712. return;
  713. }
  714. }
  715. /*
  716. * Apply this short delay always to ensure that we do wait tWB in
  717. * any case on any machine.
  718. */
  719. ndelay(100);
  720. nand_wait_ready(mtd);
  721. }
  722. /**
  723. * panic_nand_get_device - [GENERIC] Get chip for selected access
  724. * @chip: the nand chip descriptor
  725. * @mtd: MTD device structure
  726. * @new_state: the state which is requested
  727. *
  728. * Used when in panic, no locks are taken.
  729. */
  730. static void panic_nand_get_device(struct nand_chip *chip,
  731. struct mtd_info *mtd, int new_state)
  732. {
  733. /* Hardware controller shared among independent devices */
  734. chip->controller->active = chip;
  735. chip->state = new_state;
  736. }
  737. /**
  738. * nand_get_device - [GENERIC] Get chip for selected access
  739. * @mtd: MTD device structure
  740. * @new_state: the state which is requested
  741. *
  742. * Get the device and lock it for exclusive access
  743. */
  744. static int
  745. nand_get_device(struct mtd_info *mtd, int new_state)
  746. {
  747. struct nand_chip *chip = mtd_to_nand(mtd);
  748. chip->state = new_state;
  749. return 0;
  750. }
  751. /**
  752. * panic_nand_wait - [GENERIC] wait until the command is done
  753. * @mtd: MTD device structure
  754. * @chip: NAND chip structure
  755. * @timeo: timeout
  756. *
  757. * Wait for command done. This is a helper function for nand_wait used when
  758. * we are in interrupt context. May happen when in panic and trying to write
  759. * an oops through mtdoops.
  760. */
  761. static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
  762. unsigned long timeo)
  763. {
  764. int i;
  765. for (i = 0; i < timeo; i++) {
  766. if (chip->dev_ready) {
  767. if (chip->dev_ready(mtd))
  768. break;
  769. } else {
  770. int ret;
  771. u8 status;
  772. ret = nand_read_data_op(chip, &status, sizeof(status),
  773. true);
  774. if (ret)
  775. return;
  776. if (status & NAND_STATUS_READY)
  777. break;
  778. }
  779. mdelay(1);
  780. }
  781. }
  782. /**
  783. * nand_wait - [DEFAULT] wait until the command is done
  784. * @mtd: MTD device structure
  785. * @chip: NAND chip structure
  786. *
  787. * Wait for command done. This applies to erase and program only.
  788. */
  789. static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
  790. {
  791. unsigned long timeo = 400;
  792. u8 status;
  793. int ret;
  794. led_trigger_event(nand_led_trigger, LED_FULL);
  795. /*
  796. * Apply this short delay always to ensure that we do wait tWB in any
  797. * case on any machine.
  798. */
  799. ndelay(100);
  800. ret = nand_status_op(chip, NULL);
  801. if (ret)
  802. return ret;
  803. u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
  804. u32 time_start;
  805. time_start = get_timer(0);
  806. while (get_timer(time_start) < timer) {
  807. if (chip->dev_ready) {
  808. if (chip->dev_ready(mtd))
  809. break;
  810. } else {
  811. ret = nand_read_data_op(chip, &status,
  812. sizeof(status), true);
  813. if (ret)
  814. return ret;
  815. if (status & NAND_STATUS_READY)
  816. break;
  817. }
  818. }
  819. led_trigger_event(nand_led_trigger, LED_OFF);
  820. ret = nand_read_data_op(chip, &status, sizeof(status), true);
  821. if (ret)
  822. return ret;
  823. /* This can happen if in case of timeout or buggy dev_ready */
  824. WARN_ON(!(status & NAND_STATUS_READY));
  825. return status;
  826. }
  827. /**
  828. * nand_reset_data_interface - Reset data interface and timings
  829. * @chip: The NAND chip
  830. * @chipnr: Internal die id
  831. *
  832. * Reset the Data interface and timings to ONFI mode 0.
  833. *
  834. * Returns 0 for success or negative error code otherwise.
  835. */
  836. static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
  837. {
  838. struct mtd_info *mtd = nand_to_mtd(chip);
  839. const struct nand_data_interface *conf;
  840. int ret;
  841. if (!chip->setup_data_interface)
  842. return 0;
  843. /*
  844. * The ONFI specification says:
  845. * "
  846. * To transition from NV-DDR or NV-DDR2 to the SDR data
  847. * interface, the host shall use the Reset (FFh) command
  848. * using SDR timing mode 0. A device in any timing mode is
  849. * required to recognize Reset (FFh) command issued in SDR
  850. * timing mode 0.
  851. * "
  852. *
  853. * Configure the data interface in SDR mode and set the
  854. * timings to timing mode 0.
  855. */
  856. conf = nand_get_default_data_interface();
  857. ret = chip->setup_data_interface(mtd, chipnr, conf);
  858. if (ret)
  859. pr_err("Failed to configure data interface to SDR timing mode 0\n");
  860. return ret;
  861. }
  862. /**
  863. * nand_setup_data_interface - Setup the best data interface and timings
  864. * @chip: The NAND chip
  865. * @chipnr: Internal die id
  866. *
  867. * Find and configure the best data interface and NAND timings supported by
  868. * the chip and the driver.
  869. * First tries to retrieve supported timing modes from ONFI information,
  870. * and if the NAND chip does not support ONFI, relies on the
  871. * ->onfi_timing_mode_default specified in the nand_ids table.
  872. *
  873. * Returns 0 for success or negative error code otherwise.
  874. */
  875. static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
  876. {
  877. struct mtd_info *mtd = nand_to_mtd(chip);
  878. int ret;
  879. if (!chip->setup_data_interface || !chip->data_interface)
  880. return 0;
  881. /*
  882. * Ensure the timing mode has been changed on the chip side
  883. * before changing timings on the controller side.
  884. */
  885. if (chip->onfi_version) {
  886. u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
  887. chip->onfi_timing_mode_default,
  888. };
  889. ret = chip->onfi_set_features(mtd, chip,
  890. ONFI_FEATURE_ADDR_TIMING_MODE,
  891. tmode_param);
  892. if (ret)
  893. goto err;
  894. }
  895. ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
  896. err:
  897. return ret;
  898. }
  899. /**
  900. * nand_init_data_interface - find the best data interface and timings
  901. * @chip: The NAND chip
  902. *
  903. * Find the best data interface and NAND timings supported by the chip
  904. * and the driver.
  905. * First tries to retrieve supported timing modes from ONFI information,
  906. * and if the NAND chip does not support ONFI, relies on the
  907. * ->onfi_timing_mode_default specified in the nand_ids table. After this
  908. * function nand_chip->data_interface is initialized with the best timing mode
  909. * available.
  910. *
  911. * Returns 0 for success or negative error code otherwise.
  912. */
  913. static int nand_init_data_interface(struct nand_chip *chip)
  914. {
  915. struct mtd_info *mtd = nand_to_mtd(chip);
  916. int modes, mode, ret;
  917. if (!chip->setup_data_interface)
  918. return 0;
  919. /*
  920. * First try to identify the best timings from ONFI parameters and
  921. * if the NAND does not support ONFI, fallback to the default ONFI
  922. * timing mode.
  923. */
  924. modes = onfi_get_async_timing_mode(chip);
  925. if (modes == ONFI_TIMING_MODE_UNKNOWN) {
  926. if (!chip->onfi_timing_mode_default)
  927. return 0;
  928. modes = GENMASK(chip->onfi_timing_mode_default, 0);
  929. }
  930. chip->data_interface = kzalloc(sizeof(*chip->data_interface),
  931. GFP_KERNEL);
  932. if (!chip->data_interface)
  933. return -ENOMEM;
  934. for (mode = fls(modes) - 1; mode >= 0; mode--) {
  935. ret = onfi_init_data_interface(chip, chip->data_interface,
  936. NAND_SDR_IFACE, mode);
  937. if (ret)
  938. continue;
  939. /* Pass -1 to only */
  940. ret = chip->setup_data_interface(mtd,
  941. NAND_DATA_IFACE_CHECK_ONLY,
  942. chip->data_interface);
  943. if (!ret) {
  944. chip->onfi_timing_mode_default = mode;
  945. break;
  946. }
  947. }
  948. return 0;
  949. }
  950. static void __maybe_unused nand_release_data_interface(struct nand_chip *chip)
  951. {
  952. kfree(chip->data_interface);
  953. }
  954. /**
  955. * nand_read_page_op - Do a READ PAGE operation
  956. * @chip: The NAND chip
  957. * @page: page to read
  958. * @offset_in_page: offset within the page
  959. * @buf: buffer used to store the data
  960. * @len: length of the buffer
  961. *
  962. * This function issues a READ PAGE operation.
  963. * This function does not select/unselect the CS line.
  964. *
  965. * Returns 0 on success, a negative error code otherwise.
  966. */
  967. int nand_read_page_op(struct nand_chip *chip, unsigned int page,
  968. unsigned int offset_in_page, void *buf, unsigned int len)
  969. {
  970. struct mtd_info *mtd = nand_to_mtd(chip);
  971. if (len && !buf)
  972. return -EINVAL;
  973. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  974. return -EINVAL;
  975. chip->cmdfunc(mtd, NAND_CMD_READ0, offset_in_page, page);
  976. if (len)
  977. chip->read_buf(mtd, buf, len);
  978. return 0;
  979. }
  980. EXPORT_SYMBOL_GPL(nand_read_page_op);
  981. /**
  982. * nand_read_param_page_op - Do a READ PARAMETER PAGE operation
  983. * @chip: The NAND chip
  984. * @page: parameter page to read
  985. * @buf: buffer used to store the data
  986. * @len: length of the buffer
  987. *
  988. * This function issues a READ PARAMETER PAGE operation.
  989. * This function does not select/unselect the CS line.
  990. *
  991. * Returns 0 on success, a negative error code otherwise.
  992. */
  993. static int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
  994. unsigned int len)
  995. {
  996. struct mtd_info *mtd = nand_to_mtd(chip);
  997. unsigned int i;
  998. u8 *p = buf;
  999. if (len && !buf)
  1000. return -EINVAL;
  1001. chip->cmdfunc(mtd, NAND_CMD_PARAM, page, -1);
  1002. for (i = 0; i < len; i++)
  1003. p[i] = chip->read_byte(mtd);
  1004. return 0;
  1005. }
  1006. /**
  1007. * nand_change_read_column_op - Do a CHANGE READ COLUMN operation
  1008. * @chip: The NAND chip
  1009. * @offset_in_page: offset within the page
  1010. * @buf: buffer used to store the data
  1011. * @len: length of the buffer
  1012. * @force_8bit: force 8-bit bus access
  1013. *
  1014. * This function issues a CHANGE READ COLUMN operation.
  1015. * This function does not select/unselect the CS line.
  1016. *
  1017. * Returns 0 on success, a negative error code otherwise.
  1018. */
  1019. int nand_change_read_column_op(struct nand_chip *chip,
  1020. unsigned int offset_in_page, void *buf,
  1021. unsigned int len, bool force_8bit)
  1022. {
  1023. struct mtd_info *mtd = nand_to_mtd(chip);
  1024. if (len && !buf)
  1025. return -EINVAL;
  1026. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1027. return -EINVAL;
  1028. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset_in_page, -1);
  1029. if (len)
  1030. chip->read_buf(mtd, buf, len);
  1031. return 0;
  1032. }
  1033. EXPORT_SYMBOL_GPL(nand_change_read_column_op);
  1034. /**
  1035. * nand_read_oob_op - Do a READ OOB operation
  1036. * @chip: The NAND chip
  1037. * @page: page to read
  1038. * @offset_in_oob: offset within the OOB area
  1039. * @buf: buffer used to store the data
  1040. * @len: length of the buffer
  1041. *
  1042. * This function issues a READ OOB operation.
  1043. * This function does not select/unselect the CS line.
  1044. *
  1045. * Returns 0 on success, a negative error code otherwise.
  1046. */
  1047. int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
  1048. unsigned int offset_in_oob, void *buf, unsigned int len)
  1049. {
  1050. struct mtd_info *mtd = nand_to_mtd(chip);
  1051. if (len && !buf)
  1052. return -EINVAL;
  1053. if (offset_in_oob + len > mtd->oobsize)
  1054. return -EINVAL;
  1055. chip->cmdfunc(mtd, NAND_CMD_READOOB, offset_in_oob, page);
  1056. if (len)
  1057. chip->read_buf(mtd, buf, len);
  1058. return 0;
  1059. }
  1060. EXPORT_SYMBOL_GPL(nand_read_oob_op);
  1061. /**
  1062. * nand_prog_page_begin_op - starts a PROG PAGE operation
  1063. * @chip: The NAND chip
  1064. * @page: page to write
  1065. * @offset_in_page: offset within the page
  1066. * @buf: buffer containing the data to write to the page
  1067. * @len: length of the buffer
  1068. *
  1069. * This function issues the first half of a PROG PAGE operation.
  1070. * This function does not select/unselect the CS line.
  1071. *
  1072. * Returns 0 on success, a negative error code otherwise.
  1073. */
  1074. int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
  1075. unsigned int offset_in_page, const void *buf,
  1076. unsigned int len)
  1077. {
  1078. struct mtd_info *mtd = nand_to_mtd(chip);
  1079. if (len && !buf)
  1080. return -EINVAL;
  1081. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1082. return -EINVAL;
  1083. chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
  1084. if (buf)
  1085. chip->write_buf(mtd, buf, len);
  1086. return 0;
  1087. }
  1088. EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
  1089. /**
  1090. * nand_prog_page_end_op - ends a PROG PAGE operation
  1091. * @chip: The NAND chip
  1092. *
  1093. * This function issues the second half of a PROG PAGE operation.
  1094. * This function does not select/unselect the CS line.
  1095. *
  1096. * Returns 0 on success, a negative error code otherwise.
  1097. */
  1098. int nand_prog_page_end_op(struct nand_chip *chip)
  1099. {
  1100. struct mtd_info *mtd = nand_to_mtd(chip);
  1101. int status;
  1102. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1103. status = chip->waitfunc(mtd, chip);
  1104. if (status & NAND_STATUS_FAIL)
  1105. return -EIO;
  1106. return 0;
  1107. }
  1108. EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
  1109. /**
  1110. * nand_prog_page_op - Do a full PROG PAGE operation
  1111. * @chip: The NAND chip
  1112. * @page: page to write
  1113. * @offset_in_page: offset within the page
  1114. * @buf: buffer containing the data to write to the page
  1115. * @len: length of the buffer
  1116. *
  1117. * This function issues a full PROG PAGE operation.
  1118. * This function does not select/unselect the CS line.
  1119. *
  1120. * Returns 0 on success, a negative error code otherwise.
  1121. */
  1122. int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
  1123. unsigned int offset_in_page, const void *buf,
  1124. unsigned int len)
  1125. {
  1126. struct mtd_info *mtd = nand_to_mtd(chip);
  1127. int status;
  1128. if (!len || !buf)
  1129. return -EINVAL;
  1130. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1131. return -EINVAL;
  1132. chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page);
  1133. chip->write_buf(mtd, buf, len);
  1134. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1135. status = chip->waitfunc(mtd, chip);
  1136. if (status & NAND_STATUS_FAIL)
  1137. return -EIO;
  1138. return 0;
  1139. }
  1140. EXPORT_SYMBOL_GPL(nand_prog_page_op);
  1141. /**
  1142. * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
  1143. * @chip: The NAND chip
  1144. * @offset_in_page: offset within the page
  1145. * @buf: buffer containing the data to send to the NAND
  1146. * @len: length of the buffer
  1147. * @force_8bit: force 8-bit bus access
  1148. *
  1149. * This function issues a CHANGE WRITE COLUMN operation.
  1150. * This function does not select/unselect the CS line.
  1151. *
  1152. * Returns 0 on success, a negative error code otherwise.
  1153. */
  1154. int nand_change_write_column_op(struct nand_chip *chip,
  1155. unsigned int offset_in_page,
  1156. const void *buf, unsigned int len,
  1157. bool force_8bit)
  1158. {
  1159. struct mtd_info *mtd = nand_to_mtd(chip);
  1160. if (len && !buf)
  1161. return -EINVAL;
  1162. if (offset_in_page + len > mtd->writesize + mtd->oobsize)
  1163. return -EINVAL;
  1164. chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset_in_page, -1);
  1165. if (len)
  1166. chip->write_buf(mtd, buf, len);
  1167. return 0;
  1168. }
  1169. EXPORT_SYMBOL_GPL(nand_change_write_column_op);
  1170. /**
  1171. * nand_readid_op - Do a READID operation
  1172. * @chip: The NAND chip
  1173. * @addr: address cycle to pass after the READID command
  1174. * @buf: buffer used to store the ID
  1175. * @len: length of the buffer
  1176. *
  1177. * This function sends a READID command and reads back the ID returned by the
  1178. * NAND.
  1179. * This function does not select/unselect the CS line.
  1180. *
  1181. * Returns 0 on success, a negative error code otherwise.
  1182. */
  1183. int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
  1184. unsigned int len)
  1185. {
  1186. struct mtd_info *mtd = nand_to_mtd(chip);
  1187. unsigned int i;
  1188. u8 *id = buf;
  1189. if (len && !buf)
  1190. return -EINVAL;
  1191. chip->cmdfunc(mtd, NAND_CMD_READID, addr, -1);
  1192. for (i = 0; i < len; i++)
  1193. id[i] = chip->read_byte(mtd);
  1194. return 0;
  1195. }
  1196. EXPORT_SYMBOL_GPL(nand_readid_op);
  1197. /**
  1198. * nand_status_op - Do a STATUS operation
  1199. * @chip: The NAND chip
  1200. * @status: out variable to store the NAND status
  1201. *
  1202. * This function sends a STATUS command and reads back the status returned by
  1203. * the NAND.
  1204. * This function does not select/unselect the CS line.
  1205. *
  1206. * Returns 0 on success, a negative error code otherwise.
  1207. */
  1208. int nand_status_op(struct nand_chip *chip, u8 *status)
  1209. {
  1210. struct mtd_info *mtd = nand_to_mtd(chip);
  1211. chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
  1212. if (status)
  1213. *status = chip->read_byte(mtd);
  1214. return 0;
  1215. }
  1216. EXPORT_SYMBOL_GPL(nand_status_op);
  1217. /**
  1218. * nand_exit_status_op - Exit a STATUS operation
  1219. * @chip: The NAND chip
  1220. *
  1221. * This function sends a READ0 command to cancel the effect of the STATUS
  1222. * command to avoid reading only the status until a new read command is sent.
  1223. *
  1224. * This function does not select/unselect the CS line.
  1225. *
  1226. * Returns 0 on success, a negative error code otherwise.
  1227. */
  1228. int nand_exit_status_op(struct nand_chip *chip)
  1229. {
  1230. struct mtd_info *mtd = nand_to_mtd(chip);
  1231. chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1);
  1232. return 0;
  1233. }
  1234. EXPORT_SYMBOL_GPL(nand_exit_status_op);
  1235. /**
  1236. * nand_erase_op - Do an erase operation
  1237. * @chip: The NAND chip
  1238. * @eraseblock: block to erase
  1239. *
  1240. * This function sends an ERASE command and waits for the NAND to be ready
  1241. * before returning.
  1242. * This function does not select/unselect the CS line.
  1243. *
  1244. * Returns 0 on success, a negative error code otherwise.
  1245. */
  1246. int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
  1247. {
  1248. struct mtd_info *mtd = nand_to_mtd(chip);
  1249. unsigned int page = eraseblock <<
  1250. (chip->phys_erase_shift - chip->page_shift);
  1251. int status;
  1252. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
  1253. chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
  1254. status = chip->waitfunc(mtd, chip);
  1255. if (status < 0)
  1256. return status;
  1257. if (status & NAND_STATUS_FAIL)
  1258. return -EIO;
  1259. return 0;
  1260. }
  1261. EXPORT_SYMBOL_GPL(nand_erase_op);
  1262. /**
  1263. * nand_set_features_op - Do a SET FEATURES operation
  1264. * @chip: The NAND chip
  1265. * @feature: feature id
  1266. * @data: 4 bytes of data
  1267. *
  1268. * This function sends a SET FEATURES command and waits for the NAND to be
  1269. * ready before returning.
  1270. * This function does not select/unselect the CS line.
  1271. *
  1272. * Returns 0 on success, a negative error code otherwise.
  1273. */
  1274. static int nand_set_features_op(struct nand_chip *chip, u8 feature,
  1275. const void *data)
  1276. {
  1277. struct mtd_info *mtd = nand_to_mtd(chip);
  1278. const u8 *params = data;
  1279. int i, status;
  1280. chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature, -1);
  1281. for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
  1282. chip->write_byte(mtd, params[i]);
  1283. status = chip->waitfunc(mtd, chip);
  1284. if (status & NAND_STATUS_FAIL)
  1285. return -EIO;
  1286. return 0;
  1287. }
  1288. /**
  1289. * nand_get_features_op - Do a GET FEATURES operation
  1290. * @chip: The NAND chip
  1291. * @feature: feature id
  1292. * @data: 4 bytes of data
  1293. *
  1294. * This function sends a GET FEATURES command and waits for the NAND to be
  1295. * ready before returning.
  1296. * This function does not select/unselect the CS line.
  1297. *
  1298. * Returns 0 on success, a negative error code otherwise.
  1299. */
  1300. static int nand_get_features_op(struct nand_chip *chip, u8 feature,
  1301. void *data)
  1302. {
  1303. struct mtd_info *mtd = nand_to_mtd(chip);
  1304. u8 *params = data;
  1305. int i;
  1306. chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature, -1);
  1307. for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
  1308. params[i] = chip->read_byte(mtd);
  1309. return 0;
  1310. }
  1311. /**
  1312. * nand_reset_op - Do a reset operation
  1313. * @chip: The NAND chip
  1314. *
  1315. * This function sends a RESET command and waits for the NAND to be ready
  1316. * before returning.
  1317. * This function does not select/unselect the CS line.
  1318. *
  1319. * Returns 0 on success, a negative error code otherwise.
  1320. */
  1321. int nand_reset_op(struct nand_chip *chip)
  1322. {
  1323. struct mtd_info *mtd = nand_to_mtd(chip);
  1324. chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  1325. return 0;
  1326. }
  1327. EXPORT_SYMBOL_GPL(nand_reset_op);
  1328. /**
  1329. * nand_read_data_op - Read data from the NAND
  1330. * @chip: The NAND chip
  1331. * @buf: buffer used to store the data
  1332. * @len: length of the buffer
  1333. * @force_8bit: force 8-bit bus access
  1334. *
  1335. * This function does a raw data read on the bus. Usually used after launching
  1336. * another NAND operation like nand_read_page_op().
  1337. * This function does not select/unselect the CS line.
  1338. *
  1339. * Returns 0 on success, a negative error code otherwise.
  1340. */
  1341. int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
  1342. bool force_8bit)
  1343. {
  1344. struct mtd_info *mtd = nand_to_mtd(chip);
  1345. if (!len || !buf)
  1346. return -EINVAL;
  1347. if (force_8bit) {
  1348. u8 *p = buf;
  1349. unsigned int i;
  1350. for (i = 0; i < len; i++)
  1351. p[i] = chip->read_byte(mtd);
  1352. } else {
  1353. chip->read_buf(mtd, buf, len);
  1354. }
  1355. return 0;
  1356. }
  1357. EXPORT_SYMBOL_GPL(nand_read_data_op);
  1358. /**
  1359. * nand_write_data_op - Write data from the NAND
  1360. * @chip: The NAND chip
  1361. * @buf: buffer containing the data to send on the bus
  1362. * @len: length of the buffer
  1363. * @force_8bit: force 8-bit bus access
  1364. *
  1365. * This function does a raw data write on the bus. Usually used after launching
  1366. * another NAND operation like nand_write_page_begin_op().
  1367. * This function does not select/unselect the CS line.
  1368. *
  1369. * Returns 0 on success, a negative error code otherwise.
  1370. */
  1371. int nand_write_data_op(struct nand_chip *chip, const void *buf,
  1372. unsigned int len, bool force_8bit)
  1373. {
  1374. struct mtd_info *mtd = nand_to_mtd(chip);
  1375. if (!len || !buf)
  1376. return -EINVAL;
  1377. if (force_8bit) {
  1378. const u8 *p = buf;
  1379. unsigned int i;
  1380. for (i = 0; i < len; i++)
  1381. chip->write_byte(mtd, p[i]);
  1382. } else {
  1383. chip->write_buf(mtd, buf, len);
  1384. }
  1385. return 0;
  1386. }
  1387. EXPORT_SYMBOL_GPL(nand_write_data_op);
  1388. /**
  1389. * nand_reset - Reset and initialize a NAND device
  1390. * @chip: The NAND chip
  1391. * @chipnr: Internal die id
  1392. *
  1393. * Returns 0 for success or negative error code otherwise
  1394. */
  1395. int nand_reset(struct nand_chip *chip, int chipnr)
  1396. {
  1397. struct mtd_info *mtd = nand_to_mtd(chip);
  1398. int ret;
  1399. ret = nand_reset_data_interface(chip, chipnr);
  1400. if (ret)
  1401. return ret;
  1402. /*
  1403. * The CS line has to be released before we can apply the new NAND
  1404. * interface settings, hence this weird ->select_chip() dance.
  1405. */
  1406. chip->select_chip(mtd, chipnr);
  1407. ret = nand_reset_op(chip);
  1408. chip->select_chip(mtd, -1);
  1409. if (ret)
  1410. return ret;
  1411. chip->select_chip(mtd, chipnr);
  1412. ret = nand_setup_data_interface(chip, chipnr);
  1413. chip->select_chip(mtd, -1);
  1414. if (ret)
  1415. return ret;
  1416. return 0;
  1417. }
  1418. /**
  1419. * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
  1420. * @buf: buffer to test
  1421. * @len: buffer length
  1422. * @bitflips_threshold: maximum number of bitflips
  1423. *
  1424. * Check if a buffer contains only 0xff, which means the underlying region
  1425. * has been erased and is ready to be programmed.
  1426. * The bitflips_threshold specify the maximum number of bitflips before
  1427. * considering the region is not erased.
  1428. * Note: The logic of this function has been extracted from the memweight
  1429. * implementation, except that nand_check_erased_buf function exit before
  1430. * testing the whole buffer if the number of bitflips exceed the
  1431. * bitflips_threshold value.
  1432. *
  1433. * Returns a positive number of bitflips less than or equal to
  1434. * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
  1435. * threshold.
  1436. */
  1437. static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
  1438. {
  1439. const unsigned char *bitmap = buf;
  1440. int bitflips = 0;
  1441. int weight;
  1442. for (; len && ((uintptr_t)bitmap) % sizeof(long);
  1443. len--, bitmap++) {
  1444. weight = hweight8(*bitmap);
  1445. bitflips += BITS_PER_BYTE - weight;
  1446. if (unlikely(bitflips > bitflips_threshold))
  1447. return -EBADMSG;
  1448. }
  1449. for (; len >= 4; len -= 4, bitmap += 4) {
  1450. weight = hweight32(*((u32 *)bitmap));
  1451. bitflips += 32 - weight;
  1452. if (unlikely(bitflips > bitflips_threshold))
  1453. return -EBADMSG;
  1454. }
  1455. for (; len > 0; len--, bitmap++) {
  1456. weight = hweight8(*bitmap);
  1457. bitflips += BITS_PER_BYTE - weight;
  1458. if (unlikely(bitflips > bitflips_threshold))
  1459. return -EBADMSG;
  1460. }
  1461. return bitflips;
  1462. }
  1463. /**
  1464. * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
  1465. * 0xff data
  1466. * @data: data buffer to test
  1467. * @datalen: data length
  1468. * @ecc: ECC buffer
  1469. * @ecclen: ECC length
  1470. * @extraoob: extra OOB buffer
  1471. * @extraooblen: extra OOB length
  1472. * @bitflips_threshold: maximum number of bitflips
  1473. *
  1474. * Check if a data buffer and its associated ECC and OOB data contains only
  1475. * 0xff pattern, which means the underlying region has been erased and is
  1476. * ready to be programmed.
  1477. * The bitflips_threshold specify the maximum number of bitflips before
  1478. * considering the region as not erased.
  1479. *
  1480. * Note:
  1481. * 1/ ECC algorithms are working on pre-defined block sizes which are usually
  1482. * different from the NAND page size. When fixing bitflips, ECC engines will
  1483. * report the number of errors per chunk, and the NAND core infrastructure
  1484. * expect you to return the maximum number of bitflips for the whole page.
  1485. * This is why you should always use this function on a single chunk and
  1486. * not on the whole page. After checking each chunk you should update your
  1487. * max_bitflips value accordingly.
  1488. * 2/ When checking for bitflips in erased pages you should not only check
  1489. * the payload data but also their associated ECC data, because a user might
  1490. * have programmed almost all bits to 1 but a few. In this case, we
  1491. * shouldn't consider the chunk as erased, and checking ECC bytes prevent
  1492. * this case.
  1493. * 3/ The extraoob argument is optional, and should be used if some of your OOB
  1494. * data are protected by the ECC engine.
  1495. * It could also be used if you support subpages and want to attach some
  1496. * extra OOB data to an ECC chunk.
  1497. *
  1498. * Returns a positive number of bitflips less than or equal to
  1499. * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
  1500. * threshold. In case of success, the passed buffers are filled with 0xff.
  1501. */
  1502. int nand_check_erased_ecc_chunk(void *data, int datalen,
  1503. void *ecc, int ecclen,
  1504. void *extraoob, int extraooblen,
  1505. int bitflips_threshold)
  1506. {
  1507. int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
  1508. data_bitflips = nand_check_erased_buf(data, datalen,
  1509. bitflips_threshold);
  1510. if (data_bitflips < 0)
  1511. return data_bitflips;
  1512. bitflips_threshold -= data_bitflips;
  1513. ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
  1514. if (ecc_bitflips < 0)
  1515. return ecc_bitflips;
  1516. bitflips_threshold -= ecc_bitflips;
  1517. extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
  1518. bitflips_threshold);
  1519. if (extraoob_bitflips < 0)
  1520. return extraoob_bitflips;
  1521. if (data_bitflips)
  1522. memset(data, 0xff, datalen);
  1523. if (ecc_bitflips)
  1524. memset(ecc, 0xff, ecclen);
  1525. if (extraoob_bitflips)
  1526. memset(extraoob, 0xff, extraooblen);
  1527. return data_bitflips + ecc_bitflips + extraoob_bitflips;
  1528. }
  1529. EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
  1530. /**
  1531. * nand_read_page_raw - [INTERN] read raw page data without ecc
  1532. * @mtd: mtd info structure
  1533. * @chip: nand chip info structure
  1534. * @buf: buffer to store read data
  1535. * @oob_required: caller requires OOB data read to chip->oob_poi
  1536. * @page: page number to read
  1537. *
  1538. * Not for syndrome calculating ECC controllers, which use a special oob layout.
  1539. */
  1540. static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  1541. uint8_t *buf, int oob_required, int page)
  1542. {
  1543. int ret;
  1544. ret = nand_read_data_op(chip, buf, mtd->writesize, false);
  1545. if (ret)
  1546. return ret;
  1547. if (oob_required) {
  1548. ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
  1549. false);
  1550. if (ret)
  1551. return ret;
  1552. }
  1553. return 0;
  1554. }
  1555. /**
  1556. * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
  1557. * @mtd: mtd info structure
  1558. * @chip: nand chip info structure
  1559. * @buf: buffer to store read data
  1560. * @oob_required: caller requires OOB data read to chip->oob_poi
  1561. * @page: page number to read
  1562. *
  1563. * We need a special oob layout and handling even when OOB isn't used.
  1564. */
  1565. static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
  1566. struct nand_chip *chip, uint8_t *buf,
  1567. int oob_required, int page)
  1568. {
  1569. int eccsize = chip->ecc.size;
  1570. int eccbytes = chip->ecc.bytes;
  1571. uint8_t *oob = chip->oob_poi;
  1572. int steps, size, ret;
  1573. for (steps = chip->ecc.steps; steps > 0; steps--) {
  1574. ret = nand_read_data_op(chip, buf, eccsize, false);
  1575. if (ret)
  1576. return ret;
  1577. buf += eccsize;
  1578. if (chip->ecc.prepad) {
  1579. ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
  1580. false);
  1581. if (ret)
  1582. return ret;
  1583. oob += chip->ecc.prepad;
  1584. }
  1585. ret = nand_read_data_op(chip, oob, eccbytes, false);
  1586. if (ret)
  1587. return ret;
  1588. oob += eccbytes;
  1589. if (chip->ecc.postpad) {
  1590. ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
  1591. false);
  1592. if (ret)
  1593. return ret;
  1594. oob += chip->ecc.postpad;
  1595. }
  1596. }
  1597. size = mtd->oobsize - (oob - chip->oob_poi);
  1598. if (size) {
  1599. ret = nand_read_data_op(chip, oob, size, false);
  1600. if (ret)
  1601. return ret;
  1602. }
  1603. return 0;
  1604. }
  1605. /**
  1606. * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
  1607. * @mtd: mtd info structure
  1608. * @chip: nand chip info structure
  1609. * @buf: buffer to store read data
  1610. * @oob_required: caller requires OOB data read to chip->oob_poi
  1611. * @page: page number to read
  1612. */
  1613. static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  1614. uint8_t *buf, int oob_required, int page)
  1615. {
  1616. int i, eccsize = chip->ecc.size;
  1617. int eccbytes = chip->ecc.bytes;
  1618. int eccsteps = chip->ecc.steps;
  1619. uint8_t *p = buf;
  1620. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1621. uint8_t *ecc_code = chip->buffers->ecccode;
  1622. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1623. unsigned int max_bitflips = 0;
  1624. chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
  1625. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  1626. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1627. for (i = 0; i < chip->ecc.total; i++)
  1628. ecc_code[i] = chip->oob_poi[eccpos[i]];
  1629. eccsteps = chip->ecc.steps;
  1630. p = buf;
  1631. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1632. int stat;
  1633. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  1634. if (stat < 0) {
  1635. mtd->ecc_stats.failed++;
  1636. } else {
  1637. mtd->ecc_stats.corrected += stat;
  1638. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1639. }
  1640. }
  1641. return max_bitflips;
  1642. }
  1643. /**
  1644. * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
  1645. * @mtd: mtd info structure
  1646. * @chip: nand chip info structure
  1647. * @data_offs: offset of requested data within the page
  1648. * @readlen: data length
  1649. * @bufpoi: buffer to store read data
  1650. * @page: page number to read
  1651. */
  1652. static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
  1653. uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
  1654. int page)
  1655. {
  1656. int start_step, end_step, num_steps;
  1657. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1658. uint8_t *p;
  1659. int data_col_addr, i, gaps = 0;
  1660. int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
  1661. int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
  1662. int index;
  1663. unsigned int max_bitflips = 0;
  1664. int ret;
  1665. /* Column address within the page aligned to ECC size (256bytes) */
  1666. start_step = data_offs / chip->ecc.size;
  1667. end_step = (data_offs + readlen - 1) / chip->ecc.size;
  1668. num_steps = end_step - start_step + 1;
  1669. index = start_step * chip->ecc.bytes;
  1670. /* Data size aligned to ECC ecc.size */
  1671. datafrag_len = num_steps * chip->ecc.size;
  1672. eccfrag_len = num_steps * chip->ecc.bytes;
  1673. data_col_addr = start_step * chip->ecc.size;
  1674. /* If we read not a page aligned data */
  1675. if (data_col_addr != 0)
  1676. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
  1677. p = bufpoi + data_col_addr;
  1678. ret = nand_read_data_op(chip, p, datafrag_len, false);
  1679. if (ret)
  1680. return ret;
  1681. /* Calculate ECC */
  1682. for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
  1683. chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
  1684. /*
  1685. * The performance is faster if we position offsets according to
  1686. * ecc.pos. Let's make sure that there are no gaps in ECC positions.
  1687. */
  1688. for (i = 0; i < eccfrag_len - 1; i++) {
  1689. if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
  1690. gaps = 1;
  1691. break;
  1692. }
  1693. }
  1694. if (gaps) {
  1695. ret = nand_change_read_column_op(chip, mtd->writesize,
  1696. chip->oob_poi, mtd->oobsize,
  1697. false);
  1698. if (ret)
  1699. return ret;
  1700. } else {
  1701. /*
  1702. * Send the command to read the particular ECC bytes take care
  1703. * about buswidth alignment in read_buf.
  1704. */
  1705. aligned_pos = eccpos[index] & ~(busw - 1);
  1706. aligned_len = eccfrag_len;
  1707. if (eccpos[index] & (busw - 1))
  1708. aligned_len++;
  1709. if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
  1710. aligned_len++;
  1711. ret = nand_change_read_column_op(chip,
  1712. mtd->writesize + aligned_pos,
  1713. &chip->oob_poi[aligned_pos],
  1714. aligned_len, false);
  1715. if (ret)
  1716. return ret;
  1717. }
  1718. for (i = 0; i < eccfrag_len; i++)
  1719. chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
  1720. p = bufpoi + data_col_addr;
  1721. for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
  1722. int stat;
  1723. stat = chip->ecc.correct(mtd, p,
  1724. &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
  1725. if (stat == -EBADMSG &&
  1726. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1727. /* check for empty pages with bitflips */
  1728. stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
  1729. &chip->buffers->ecccode[i],
  1730. chip->ecc.bytes,
  1731. NULL, 0,
  1732. chip->ecc.strength);
  1733. }
  1734. if (stat < 0) {
  1735. mtd->ecc_stats.failed++;
  1736. } else {
  1737. mtd->ecc_stats.corrected += stat;
  1738. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1739. }
  1740. }
  1741. return max_bitflips;
  1742. }
  1743. /**
  1744. * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
  1745. * @mtd: mtd info structure
  1746. * @chip: nand chip info structure
  1747. * @buf: buffer to store read data
  1748. * @oob_required: caller requires OOB data read to chip->oob_poi
  1749. * @page: page number to read
  1750. *
  1751. * Not for syndrome calculating ECC controllers which need a special oob layout.
  1752. */
  1753. static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  1754. uint8_t *buf, int oob_required, int page)
  1755. {
  1756. int i, eccsize = chip->ecc.size;
  1757. int eccbytes = chip->ecc.bytes;
  1758. int eccsteps = chip->ecc.steps;
  1759. uint8_t *p = buf;
  1760. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1761. uint8_t *ecc_code = chip->buffers->ecccode;
  1762. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1763. unsigned int max_bitflips = 0;
  1764. int ret;
  1765. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1766. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  1767. ret = nand_read_data_op(chip, p, eccsize, false);
  1768. if (ret)
  1769. return ret;
  1770. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1771. }
  1772. ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false);
  1773. if (ret)
  1774. return ret;
  1775. for (i = 0; i < chip->ecc.total; i++)
  1776. ecc_code[i] = chip->oob_poi[eccpos[i]];
  1777. eccsteps = chip->ecc.steps;
  1778. p = buf;
  1779. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1780. int stat;
  1781. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  1782. if (stat == -EBADMSG &&
  1783. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1784. /* check for empty pages with bitflips */
  1785. stat = nand_check_erased_ecc_chunk(p, eccsize,
  1786. &ecc_code[i], eccbytes,
  1787. NULL, 0,
  1788. chip->ecc.strength);
  1789. }
  1790. if (stat < 0) {
  1791. mtd->ecc_stats.failed++;
  1792. } else {
  1793. mtd->ecc_stats.corrected += stat;
  1794. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1795. }
  1796. }
  1797. return max_bitflips;
  1798. }
  1799. /**
  1800. * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
  1801. * @mtd: mtd info structure
  1802. * @chip: nand chip info structure
  1803. * @buf: buffer to store read data
  1804. * @oob_required: caller requires OOB data read to chip->oob_poi
  1805. * @page: page number to read
  1806. *
  1807. * Hardware ECC for large page chips, require OOB to be read first. For this
  1808. * ECC mode, the write_page method is re-used from ECC_HW. These methods
  1809. * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
  1810. * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
  1811. * the data area, by overwriting the NAND manufacturer bad block markings.
  1812. */
  1813. static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
  1814. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  1815. {
  1816. int i, eccsize = chip->ecc.size;
  1817. int eccbytes = chip->ecc.bytes;
  1818. int eccsteps = chip->ecc.steps;
  1819. uint8_t *p = buf;
  1820. uint8_t *ecc_code = chip->buffers->ecccode;
  1821. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1822. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1823. unsigned int max_bitflips = 0;
  1824. int ret;
  1825. /* Read the OOB area first */
  1826. ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
  1827. if (ret)
  1828. return ret;
  1829. ret = nand_read_page_op(chip, page, 0, NULL, 0);
  1830. if (ret)
  1831. return ret;
  1832. for (i = 0; i < chip->ecc.total; i++)
  1833. ecc_code[i] = chip->oob_poi[eccpos[i]];
  1834. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1835. int stat;
  1836. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  1837. ret = nand_read_data_op(chip, p, eccsize, false);
  1838. if (ret)
  1839. return ret;
  1840. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1841. stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
  1842. if (stat == -EBADMSG &&
  1843. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1844. /* check for empty pages with bitflips */
  1845. stat = nand_check_erased_ecc_chunk(p, eccsize,
  1846. &ecc_code[i], eccbytes,
  1847. NULL, 0,
  1848. chip->ecc.strength);
  1849. }
  1850. if (stat < 0) {
  1851. mtd->ecc_stats.failed++;
  1852. } else {
  1853. mtd->ecc_stats.corrected += stat;
  1854. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1855. }
  1856. }
  1857. return max_bitflips;
  1858. }
  1859. /**
  1860. * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
  1861. * @mtd: mtd info structure
  1862. * @chip: nand chip info structure
  1863. * @buf: buffer to store read data
  1864. * @oob_required: caller requires OOB data read to chip->oob_poi
  1865. * @page: page number to read
  1866. *
  1867. * The hw generator calculates the error syndrome automatically. Therefore we
  1868. * need a special oob layout and handling.
  1869. */
  1870. static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  1871. uint8_t *buf, int oob_required, int page)
  1872. {
  1873. int ret, i, eccsize = chip->ecc.size;
  1874. int eccbytes = chip->ecc.bytes;
  1875. int eccsteps = chip->ecc.steps;
  1876. int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  1877. uint8_t *p = buf;
  1878. uint8_t *oob = chip->oob_poi;
  1879. unsigned int max_bitflips = 0;
  1880. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1881. int stat;
  1882. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  1883. ret = nand_read_data_op(chip, p, eccsize, false);
  1884. if (ret)
  1885. return ret;
  1886. if (chip->ecc.prepad) {
  1887. ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
  1888. false);
  1889. if (ret)
  1890. return ret;
  1891. oob += chip->ecc.prepad;
  1892. }
  1893. chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
  1894. ret = nand_read_data_op(chip, oob, eccbytes, false);
  1895. if (ret)
  1896. return ret;
  1897. stat = chip->ecc.correct(mtd, p, oob, NULL);
  1898. oob += eccbytes;
  1899. if (chip->ecc.postpad) {
  1900. ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
  1901. false);
  1902. if (ret)
  1903. return ret;
  1904. oob += chip->ecc.postpad;
  1905. }
  1906. if (stat == -EBADMSG &&
  1907. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1908. /* check for empty pages with bitflips */
  1909. stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
  1910. oob - eccpadbytes,
  1911. eccpadbytes,
  1912. NULL, 0,
  1913. chip->ecc.strength);
  1914. }
  1915. if (stat < 0) {
  1916. mtd->ecc_stats.failed++;
  1917. } else {
  1918. mtd->ecc_stats.corrected += stat;
  1919. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1920. }
  1921. }
  1922. /* Calculate remaining oob bytes */
  1923. i = mtd->oobsize - (oob - chip->oob_poi);
  1924. if (i) {
  1925. ret = nand_read_data_op(chip, oob, i, false);
  1926. if (ret)
  1927. return ret;
  1928. }
  1929. return max_bitflips;
  1930. }
  1931. /**
  1932. * nand_transfer_oob - [INTERN] Transfer oob to client buffer
  1933. * @chip: nand chip structure
  1934. * @oob: oob destination address
  1935. * @ops: oob ops structure
  1936. * @len: size of oob to transfer
  1937. */
  1938. static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
  1939. struct mtd_oob_ops *ops, size_t len)
  1940. {
  1941. switch (ops->mode) {
  1942. case MTD_OPS_PLACE_OOB:
  1943. case MTD_OPS_RAW:
  1944. memcpy(oob, chip->oob_poi + ops->ooboffs, len);
  1945. return oob + len;
  1946. case MTD_OPS_AUTO_OOB: {
  1947. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  1948. uint32_t boffs = 0, roffs = ops->ooboffs;
  1949. size_t bytes = 0;
  1950. for (; free->length && len; free++, len -= bytes) {
  1951. /* Read request not from offset 0? */
  1952. if (unlikely(roffs)) {
  1953. if (roffs >= free->length) {
  1954. roffs -= free->length;
  1955. continue;
  1956. }
  1957. boffs = free->offset + roffs;
  1958. bytes = min_t(size_t, len,
  1959. (free->length - roffs));
  1960. roffs = 0;
  1961. } else {
  1962. bytes = min_t(size_t, len, free->length);
  1963. boffs = free->offset;
  1964. }
  1965. memcpy(oob, chip->oob_poi + boffs, bytes);
  1966. oob += bytes;
  1967. }
  1968. return oob;
  1969. }
  1970. default:
  1971. BUG();
  1972. }
  1973. return NULL;
  1974. }
  1975. /**
  1976. * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
  1977. * @mtd: MTD device structure
  1978. * @retry_mode: the retry mode to use
  1979. *
  1980. * Some vendors supply a special command to shift the Vt threshold, to be used
  1981. * when there are too many bitflips in a page (i.e., ECC error). After setting
  1982. * a new threshold, the host should retry reading the page.
  1983. */
  1984. static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
  1985. {
  1986. struct nand_chip *chip = mtd_to_nand(mtd);
  1987. pr_debug("setting READ RETRY mode %d\n", retry_mode);
  1988. if (retry_mode >= chip->read_retries)
  1989. return -EINVAL;
  1990. if (!chip->setup_read_retry)
  1991. return -EOPNOTSUPP;
  1992. return chip->setup_read_retry(mtd, retry_mode);
  1993. }
  1994. /**
  1995. * nand_do_read_ops - [INTERN] Read data with ECC
  1996. * @mtd: MTD device structure
  1997. * @from: offset to read from
  1998. * @ops: oob ops structure
  1999. *
  2000. * Internal function. Called with chip held.
  2001. */
  2002. static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
  2003. struct mtd_oob_ops *ops)
  2004. {
  2005. int chipnr, page, realpage, col, bytes, aligned, oob_required;
  2006. struct nand_chip *chip = mtd_to_nand(mtd);
  2007. int ret = 0;
  2008. uint32_t readlen = ops->len;
  2009. uint32_t oobreadlen = ops->ooblen;
  2010. uint32_t max_oobsize = mtd_oobavail(mtd, ops);
  2011. uint8_t *bufpoi, *oob, *buf;
  2012. int use_bufpoi;
  2013. unsigned int max_bitflips = 0;
  2014. int retry_mode = 0;
  2015. bool ecc_fail = false;
  2016. chipnr = (int)(from >> chip->chip_shift);
  2017. chip->select_chip(mtd, chipnr);
  2018. realpage = (int)(from >> chip->page_shift);
  2019. page = realpage & chip->pagemask;
  2020. col = (int)(from & (mtd->writesize - 1));
  2021. buf = ops->datbuf;
  2022. oob = ops->oobbuf;
  2023. oob_required = oob ? 1 : 0;
  2024. while (1) {
  2025. unsigned int ecc_failures = mtd->ecc_stats.failed;
  2026. WATCHDOG_RESET();
  2027. bytes = min(mtd->writesize - col, readlen);
  2028. aligned = (bytes == mtd->writesize);
  2029. if (!aligned)
  2030. use_bufpoi = 1;
  2031. else if (chip->options & NAND_USE_BOUNCE_BUFFER)
  2032. use_bufpoi = !IS_ALIGNED((unsigned long)buf,
  2033. chip->buf_align);
  2034. else
  2035. use_bufpoi = 0;
  2036. /* Is the current page in the buffer? */
  2037. if (realpage != chip->pagebuf || oob) {
  2038. bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
  2039. if (use_bufpoi && aligned)
  2040. pr_debug("%s: using read bounce buffer for buf@%p\n",
  2041. __func__, buf);
  2042. read_retry:
  2043. if (nand_standard_page_accessors(&chip->ecc)) {
  2044. ret = nand_read_page_op(chip, page, 0, NULL, 0);
  2045. if (ret)
  2046. break;
  2047. }
  2048. /*
  2049. * Now read the page into the buffer. Absent an error,
  2050. * the read methods return max bitflips per ecc step.
  2051. */
  2052. if (unlikely(ops->mode == MTD_OPS_RAW))
  2053. ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
  2054. oob_required,
  2055. page);
  2056. else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
  2057. !oob)
  2058. ret = chip->ecc.read_subpage(mtd, chip,
  2059. col, bytes, bufpoi,
  2060. page);
  2061. else
  2062. ret = chip->ecc.read_page(mtd, chip, bufpoi,
  2063. oob_required, page);
  2064. if (ret < 0) {
  2065. if (use_bufpoi)
  2066. /* Invalidate page cache */
  2067. chip->pagebuf = -1;
  2068. break;
  2069. }
  2070. max_bitflips = max_t(unsigned int, max_bitflips, ret);
  2071. /* Transfer not aligned data */
  2072. if (use_bufpoi) {
  2073. if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
  2074. !(mtd->ecc_stats.failed - ecc_failures) &&
  2075. (ops->mode != MTD_OPS_RAW)) {
  2076. chip->pagebuf = realpage;
  2077. chip->pagebuf_bitflips = ret;
  2078. } else {
  2079. /* Invalidate page cache */
  2080. chip->pagebuf = -1;
  2081. }
  2082. memcpy(buf, chip->buffers->databuf + col, bytes);
  2083. }
  2084. if (unlikely(oob)) {
  2085. int toread = min(oobreadlen, max_oobsize);
  2086. if (toread) {
  2087. oob = nand_transfer_oob(chip,
  2088. oob, ops, toread);
  2089. oobreadlen -= toread;
  2090. }
  2091. }
  2092. if (chip->options & NAND_NEED_READRDY) {
  2093. /* Apply delay or wait for ready/busy pin */
  2094. if (!chip->dev_ready)
  2095. udelay(chip->chip_delay);
  2096. else
  2097. nand_wait_ready(mtd);
  2098. }
  2099. if (mtd->ecc_stats.failed - ecc_failures) {
  2100. if (retry_mode + 1 < chip->read_retries) {
  2101. retry_mode++;
  2102. ret = nand_setup_read_retry(mtd,
  2103. retry_mode);
  2104. if (ret < 0)
  2105. break;
  2106. /* Reset failures; retry */
  2107. mtd->ecc_stats.failed = ecc_failures;
  2108. goto read_retry;
  2109. } else {
  2110. /* No more retry modes; real failure */
  2111. ecc_fail = true;
  2112. }
  2113. }
  2114. buf += bytes;
  2115. } else {
  2116. memcpy(buf, chip->buffers->databuf + col, bytes);
  2117. buf += bytes;
  2118. max_bitflips = max_t(unsigned int, max_bitflips,
  2119. chip->pagebuf_bitflips);
  2120. }
  2121. readlen -= bytes;
  2122. /* Reset to retry mode 0 */
  2123. if (retry_mode) {
  2124. ret = nand_setup_read_retry(mtd, 0);
  2125. if (ret < 0)
  2126. break;
  2127. retry_mode = 0;
  2128. }
  2129. if (!readlen)
  2130. break;
  2131. /* For subsequent reads align to page boundary */
  2132. col = 0;
  2133. /* Increment page address */
  2134. realpage++;
  2135. page = realpage & chip->pagemask;
  2136. /* Check, if we cross a chip boundary */
  2137. if (!page) {
  2138. chipnr++;
  2139. chip->select_chip(mtd, -1);
  2140. chip->select_chip(mtd, chipnr);
  2141. }
  2142. }
  2143. chip->select_chip(mtd, -1);
  2144. ops->retlen = ops->len - (size_t) readlen;
  2145. if (oob)
  2146. ops->oobretlen = ops->ooblen - oobreadlen;
  2147. if (ret < 0)
  2148. return ret;
  2149. if (ecc_fail)
  2150. return -EBADMSG;
  2151. return max_bitflips;
  2152. }
  2153. /**
  2154. * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
  2155. * @mtd: mtd info structure
  2156. * @chip: nand chip info structure
  2157. * @page: page number to read
  2158. */
  2159. static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  2160. int page)
  2161. {
  2162. return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
  2163. }
  2164. /**
  2165. * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
  2166. * with syndromes
  2167. * @mtd: mtd info structure
  2168. * @chip: nand chip info structure
  2169. * @page: page number to read
  2170. */
  2171. static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  2172. int page)
  2173. {
  2174. int length = mtd->oobsize;
  2175. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  2176. int eccsize = chip->ecc.size;
  2177. uint8_t *bufpoi = chip->oob_poi;
  2178. int i, toread, sndrnd = 0, pos, ret;
  2179. ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
  2180. if (ret)
  2181. return ret;
  2182. for (i = 0; i < chip->ecc.steps; i++) {
  2183. if (sndrnd) {
  2184. int ret;
  2185. pos = eccsize + i * (eccsize + chunk);
  2186. if (mtd->writesize > 512)
  2187. ret = nand_change_read_column_op(chip, pos,
  2188. NULL, 0,
  2189. false);
  2190. else
  2191. ret = nand_read_page_op(chip, page, pos, NULL,
  2192. 0);
  2193. if (ret)
  2194. return ret;
  2195. } else
  2196. sndrnd = 1;
  2197. toread = min_t(int, length, chunk);
  2198. ret = nand_read_data_op(chip, bufpoi, toread, false);
  2199. if (ret)
  2200. return ret;
  2201. bufpoi += toread;
  2202. length -= toread;
  2203. }
  2204. if (length > 0) {
  2205. ret = nand_read_data_op(chip, bufpoi, length, false);
  2206. if (ret)
  2207. return ret;
  2208. }
  2209. return 0;
  2210. }
  2211. /**
  2212. * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
  2213. * @mtd: mtd info structure
  2214. * @chip: nand chip info structure
  2215. * @page: page number to write
  2216. */
  2217. static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  2218. int page)
  2219. {
  2220. return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
  2221. mtd->oobsize);
  2222. }
  2223. /**
  2224. * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
  2225. * with syndrome - only for large page flash
  2226. * @mtd: mtd info structure
  2227. * @chip: nand chip info structure
  2228. * @page: page number to write
  2229. */
  2230. static int nand_write_oob_syndrome(struct mtd_info *mtd,
  2231. struct nand_chip *chip, int page)
  2232. {
  2233. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  2234. int eccsize = chip->ecc.size, length = mtd->oobsize;
  2235. int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
  2236. const uint8_t *bufpoi = chip->oob_poi;
  2237. /*
  2238. * data-ecc-data-ecc ... ecc-oob
  2239. * or
  2240. * data-pad-ecc-pad-data-pad .... ecc-pad-oob
  2241. */
  2242. if (!chip->ecc.prepad && !chip->ecc.postpad) {
  2243. pos = steps * (eccsize + chunk);
  2244. steps = 0;
  2245. } else
  2246. pos = eccsize;
  2247. ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
  2248. if (ret)
  2249. return ret;
  2250. for (i = 0; i < steps; i++) {
  2251. if (sndcmd) {
  2252. if (mtd->writesize <= 512) {
  2253. uint32_t fill = 0xFFFFFFFF;
  2254. len = eccsize;
  2255. while (len > 0) {
  2256. int num = min_t(int, len, 4);
  2257. ret = nand_write_data_op(chip, &fill,
  2258. num, false);
  2259. if (ret)
  2260. return ret;
  2261. len -= num;
  2262. }
  2263. } else {
  2264. pos = eccsize + i * (eccsize + chunk);
  2265. ret = nand_change_write_column_op(chip, pos,
  2266. NULL, 0,
  2267. false);
  2268. if (ret)
  2269. return ret;
  2270. }
  2271. } else
  2272. sndcmd = 1;
  2273. len = min_t(int, length, chunk);
  2274. ret = nand_write_data_op(chip, bufpoi, len, false);
  2275. if (ret)
  2276. return ret;
  2277. bufpoi += len;
  2278. length -= len;
  2279. }
  2280. if (length > 0) {
  2281. ret = nand_write_data_op(chip, bufpoi, length, false);
  2282. if (ret)
  2283. return ret;
  2284. }
  2285. return nand_prog_page_end_op(chip);
  2286. }
  2287. /**
  2288. * nand_do_read_oob - [INTERN] NAND read out-of-band
  2289. * @mtd: MTD device structure
  2290. * @from: offset to read from
  2291. * @ops: oob operations description structure
  2292. *
  2293. * NAND read out-of-band data from the spare area.
  2294. */
  2295. static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
  2296. struct mtd_oob_ops *ops)
  2297. {
  2298. int page, realpage, chipnr;
  2299. struct nand_chip *chip = mtd_to_nand(mtd);
  2300. struct mtd_ecc_stats stats;
  2301. int readlen = ops->ooblen;
  2302. int len;
  2303. uint8_t *buf = ops->oobbuf;
  2304. int ret = 0;
  2305. pr_debug("%s: from = 0x%08Lx, len = %i\n",
  2306. __func__, (unsigned long long)from, readlen);
  2307. stats = mtd->ecc_stats;
  2308. len = mtd_oobavail(mtd, ops);
  2309. if (unlikely(ops->ooboffs >= len)) {
  2310. pr_debug("%s: attempt to start read outside oob\n",
  2311. __func__);
  2312. return -EINVAL;
  2313. }
  2314. /* Do not allow reads past end of device */
  2315. if (unlikely(from >= mtd->size ||
  2316. ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
  2317. (from >> chip->page_shift)) * len)) {
  2318. pr_debug("%s: attempt to read beyond end of device\n",
  2319. __func__);
  2320. return -EINVAL;
  2321. }
  2322. chipnr = (int)(from >> chip->chip_shift);
  2323. chip->select_chip(mtd, chipnr);
  2324. /* Shift to get page */
  2325. realpage = (int)(from >> chip->page_shift);
  2326. page = realpage & chip->pagemask;
  2327. while (1) {
  2328. WATCHDOG_RESET();
  2329. if (ops->mode == MTD_OPS_RAW)
  2330. ret = chip->ecc.read_oob_raw(mtd, chip, page);
  2331. else
  2332. ret = chip->ecc.read_oob(mtd, chip, page);
  2333. if (ret < 0)
  2334. break;
  2335. len = min(len, readlen);
  2336. buf = nand_transfer_oob(chip, buf, ops, len);
  2337. if (chip->options & NAND_NEED_READRDY) {
  2338. /* Apply delay or wait for ready/busy pin */
  2339. if (!chip->dev_ready)
  2340. udelay(chip->chip_delay);
  2341. else
  2342. nand_wait_ready(mtd);
  2343. }
  2344. readlen -= len;
  2345. if (!readlen)
  2346. break;
  2347. /* Increment page address */
  2348. realpage++;
  2349. page = realpage & chip->pagemask;
  2350. /* Check, if we cross a chip boundary */
  2351. if (!page) {
  2352. chipnr++;
  2353. chip->select_chip(mtd, -1);
  2354. chip->select_chip(mtd, chipnr);
  2355. }
  2356. }
  2357. chip->select_chip(mtd, -1);
  2358. ops->oobretlen = ops->ooblen - readlen;
  2359. if (ret < 0)
  2360. return ret;
  2361. if (mtd->ecc_stats.failed - stats.failed)
  2362. return -EBADMSG;
  2363. return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
  2364. }
  2365. /**
  2366. * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
  2367. * @mtd: MTD device structure
  2368. * @from: offset to read from
  2369. * @ops: oob operation description structure
  2370. *
  2371. * NAND read data and/or out-of-band data.
  2372. */
  2373. static int nand_read_oob(struct mtd_info *mtd, loff_t from,
  2374. struct mtd_oob_ops *ops)
  2375. {
  2376. int ret = -ENOTSUPP;
  2377. ops->retlen = 0;
  2378. /* Do not allow reads past end of device */
  2379. if (ops->datbuf && (from + ops->len) > mtd->size) {
  2380. pr_debug("%s: attempt to read beyond end of device\n",
  2381. __func__);
  2382. return -EINVAL;
  2383. }
  2384. nand_get_device(mtd, FL_READING);
  2385. switch (ops->mode) {
  2386. case MTD_OPS_PLACE_OOB:
  2387. case MTD_OPS_AUTO_OOB:
  2388. case MTD_OPS_RAW:
  2389. break;
  2390. default:
  2391. goto out;
  2392. }
  2393. if (!ops->datbuf)
  2394. ret = nand_do_read_oob(mtd, from, ops);
  2395. else
  2396. ret = nand_do_read_ops(mtd, from, ops);
  2397. out:
  2398. nand_release_device(mtd);
  2399. return ret;
  2400. }
  2401. /**
  2402. * nand_write_page_raw - [INTERN] raw page write function
  2403. * @mtd: mtd info structure
  2404. * @chip: nand chip info structure
  2405. * @buf: data buffer
  2406. * @oob_required: must write chip->oob_poi to OOB
  2407. * @page: page number to write
  2408. *
  2409. * Not for syndrome calculating ECC controllers, which use a special oob layout.
  2410. */
  2411. static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  2412. const uint8_t *buf, int oob_required, int page)
  2413. {
  2414. int ret;
  2415. ret = nand_write_data_op(chip, buf, mtd->writesize, false);
  2416. if (ret)
  2417. return ret;
  2418. if (oob_required) {
  2419. ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
  2420. false);
  2421. if (ret)
  2422. return ret;
  2423. }
  2424. return 0;
  2425. }
  2426. /**
  2427. * nand_write_page_raw_syndrome - [INTERN] raw page write function
  2428. * @mtd: mtd info structure
  2429. * @chip: nand chip info structure
  2430. * @buf: data buffer
  2431. * @oob_required: must write chip->oob_poi to OOB
  2432. * @page: page number to write
  2433. *
  2434. * We need a special oob layout and handling even when ECC isn't checked.
  2435. */
  2436. static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
  2437. struct nand_chip *chip,
  2438. const uint8_t *buf, int oob_required,
  2439. int page)
  2440. {
  2441. int eccsize = chip->ecc.size;
  2442. int eccbytes = chip->ecc.bytes;
  2443. uint8_t *oob = chip->oob_poi;
  2444. int steps, size, ret;
  2445. for (steps = chip->ecc.steps; steps > 0; steps--) {
  2446. ret = nand_write_data_op(chip, buf, eccsize, false);
  2447. if (ret)
  2448. return ret;
  2449. buf += eccsize;
  2450. if (chip->ecc.prepad) {
  2451. ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
  2452. false);
  2453. if (ret)
  2454. return ret;
  2455. oob += chip->ecc.prepad;
  2456. }
  2457. ret = nand_write_data_op(chip, oob, eccbytes, false);
  2458. if (ret)
  2459. return ret;
  2460. oob += eccbytes;
  2461. if (chip->ecc.postpad) {
  2462. ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
  2463. false);
  2464. if (ret)
  2465. return ret;
  2466. oob += chip->ecc.postpad;
  2467. }
  2468. }
  2469. size = mtd->oobsize - (oob - chip->oob_poi);
  2470. if (size) {
  2471. ret = nand_write_data_op(chip, oob, size, false);
  2472. if (ret)
  2473. return ret;
  2474. }
  2475. return 0;
  2476. }
  2477. /**
  2478. * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
  2479. * @mtd: mtd info structure
  2480. * @chip: nand chip info structure
  2481. * @buf: data buffer
  2482. * @oob_required: must write chip->oob_poi to OOB
  2483. * @page: page number to write
  2484. */
  2485. static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  2486. const uint8_t *buf, int oob_required,
  2487. int page)
  2488. {
  2489. int i, eccsize = chip->ecc.size;
  2490. int eccbytes = chip->ecc.bytes;
  2491. int eccsteps = chip->ecc.steps;
  2492. uint8_t *ecc_calc = chip->buffers->ecccalc;
  2493. const uint8_t *p = buf;
  2494. uint32_t *eccpos = chip->ecc.layout->eccpos;
  2495. /* Software ECC calculation */
  2496. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  2497. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  2498. for (i = 0; i < chip->ecc.total; i++)
  2499. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  2500. return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
  2501. }
  2502. /**
  2503. * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
  2504. * @mtd: mtd info structure
  2505. * @chip: nand chip info structure
  2506. * @buf: data buffer
  2507. * @oob_required: must write chip->oob_poi to OOB
  2508. * @page: page number to write
  2509. */
  2510. static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  2511. const uint8_t *buf, int oob_required,
  2512. int page)
  2513. {
  2514. int i, eccsize = chip->ecc.size;
  2515. int eccbytes = chip->ecc.bytes;
  2516. int eccsteps = chip->ecc.steps;
  2517. uint8_t *ecc_calc = chip->buffers->ecccalc;
  2518. const uint8_t *p = buf;
  2519. uint32_t *eccpos = chip->ecc.layout->eccpos;
  2520. int ret;
  2521. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  2522. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  2523. ret = nand_write_data_op(chip, p, eccsize, false);
  2524. if (ret)
  2525. return ret;
  2526. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  2527. }
  2528. for (i = 0; i < chip->ecc.total; i++)
  2529. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  2530. ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
  2531. if (ret)
  2532. return ret;
  2533. return 0;
  2534. }
  2535. /**
  2536. * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
  2537. * @mtd: mtd info structure
  2538. * @chip: nand chip info structure
  2539. * @offset: column address of subpage within the page
  2540. * @data_len: data length
  2541. * @buf: data buffer
  2542. * @oob_required: must write chip->oob_poi to OOB
  2543. * @page: page number to write
  2544. */
  2545. static int nand_write_subpage_hwecc(struct mtd_info *mtd,
  2546. struct nand_chip *chip, uint32_t offset,
  2547. uint32_t data_len, const uint8_t *buf,
  2548. int oob_required, int page)
  2549. {
  2550. uint8_t *oob_buf = chip->oob_poi;
  2551. uint8_t *ecc_calc = chip->buffers->ecccalc;
  2552. int ecc_size = chip->ecc.size;
  2553. int ecc_bytes = chip->ecc.bytes;
  2554. int ecc_steps = chip->ecc.steps;
  2555. uint32_t *eccpos = chip->ecc.layout->eccpos;
  2556. uint32_t start_step = offset / ecc_size;
  2557. uint32_t end_step = (offset + data_len - 1) / ecc_size;
  2558. int oob_bytes = mtd->oobsize / ecc_steps;
  2559. int step, i;
  2560. int ret;
  2561. for (step = 0; step < ecc_steps; step++) {
  2562. /* configure controller for WRITE access */
  2563. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  2564. /* write data (untouched subpages already masked by 0xFF) */
  2565. ret = nand_write_data_op(chip, buf, ecc_size, false);
  2566. if (ret)
  2567. return ret;
  2568. /* mask ECC of un-touched subpages by padding 0xFF */
  2569. if ((step < start_step) || (step > end_step))
  2570. memset(ecc_calc, 0xff, ecc_bytes);
  2571. else
  2572. chip->ecc.calculate(mtd, buf, ecc_calc);
  2573. /* mask OOB of un-touched subpages by padding 0xFF */
  2574. /* if oob_required, preserve OOB metadata of written subpage */
  2575. if (!oob_required || (step < start_step) || (step > end_step))
  2576. memset(oob_buf, 0xff, oob_bytes);
  2577. buf += ecc_size;
  2578. ecc_calc += ecc_bytes;
  2579. oob_buf += oob_bytes;
  2580. }
  2581. /* copy calculated ECC for whole page to chip->buffer->oob */
  2582. /* this include masked-value(0xFF) for unwritten subpages */
  2583. ecc_calc = chip->buffers->ecccalc;
  2584. for (i = 0; i < chip->ecc.total; i++)
  2585. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  2586. /* write OOB buffer to NAND device */
  2587. ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
  2588. if (ret)
  2589. return ret;
  2590. return 0;
  2591. }
  2592. /**
  2593. * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
  2594. * @mtd: mtd info structure
  2595. * @chip: nand chip info structure
  2596. * @buf: data buffer
  2597. * @oob_required: must write chip->oob_poi to OOB
  2598. * @page: page number to write
  2599. *
  2600. * The hw generator calculates the error syndrome automatically. Therefore we
  2601. * need a special oob layout and handling.
  2602. */
  2603. static int nand_write_page_syndrome(struct mtd_info *mtd,
  2604. struct nand_chip *chip,
  2605. const uint8_t *buf, int oob_required,
  2606. int page)
  2607. {
  2608. int i, eccsize = chip->ecc.size;
  2609. int eccbytes = chip->ecc.bytes;
  2610. int eccsteps = chip->ecc.steps;
  2611. const uint8_t *p = buf;
  2612. uint8_t *oob = chip->oob_poi;
  2613. int ret;
  2614. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  2615. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  2616. ret = nand_write_data_op(chip, p, eccsize, false);
  2617. if (ret)
  2618. return ret;
  2619. if (chip->ecc.prepad) {
  2620. ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
  2621. false);
  2622. if (ret)
  2623. return ret;
  2624. oob += chip->ecc.prepad;
  2625. }
  2626. chip->ecc.calculate(mtd, p, oob);
  2627. ret = nand_write_data_op(chip, oob, eccbytes, false);
  2628. if (ret)
  2629. return ret;
  2630. oob += eccbytes;
  2631. if (chip->ecc.postpad) {
  2632. ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
  2633. false);
  2634. if (ret)
  2635. return ret;
  2636. oob += chip->ecc.postpad;
  2637. }
  2638. }
  2639. /* Calculate remaining oob bytes */
  2640. i = mtd->oobsize - (oob - chip->oob_poi);
  2641. if (i) {
  2642. ret = nand_write_data_op(chip, oob, i, false);
  2643. if (ret)
  2644. return ret;
  2645. }
  2646. return 0;
  2647. }
  2648. /**
  2649. * nand_write_page - [REPLACEABLE] write one page
  2650. * @mtd: MTD device structure
  2651. * @chip: NAND chip descriptor
  2652. * @offset: address offset within the page
  2653. * @data_len: length of actual data to be written
  2654. * @buf: the data to write
  2655. * @oob_required: must write chip->oob_poi to OOB
  2656. * @page: page number to write
  2657. * @raw: use _raw version of write_page
  2658. */
  2659. static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  2660. uint32_t offset, int data_len, const uint8_t *buf,
  2661. int oob_required, int page, int raw)
  2662. {
  2663. int status, subpage;
  2664. if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
  2665. chip->ecc.write_subpage)
  2666. subpage = offset || (data_len < mtd->writesize);
  2667. else
  2668. subpage = 0;
  2669. if (nand_standard_page_accessors(&chip->ecc)) {
  2670. status = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
  2671. if (status)
  2672. return status;
  2673. }
  2674. if (unlikely(raw))
  2675. status = chip->ecc.write_page_raw(mtd, chip, buf,
  2676. oob_required, page);
  2677. else if (subpage)
  2678. status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
  2679. buf, oob_required, page);
  2680. else
  2681. status = chip->ecc.write_page(mtd, chip, buf, oob_required,
  2682. page);
  2683. if (status < 0)
  2684. return status;
  2685. if (nand_standard_page_accessors(&chip->ecc))
  2686. return nand_prog_page_end_op(chip);
  2687. return 0;
  2688. }
  2689. /**
  2690. * nand_fill_oob - [INTERN] Transfer client buffer to oob
  2691. * @mtd: MTD device structure
  2692. * @oob: oob data buffer
  2693. * @len: oob data write length
  2694. * @ops: oob ops structure
  2695. */
  2696. static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
  2697. struct mtd_oob_ops *ops)
  2698. {
  2699. struct nand_chip *chip = mtd_to_nand(mtd);
  2700. /*
  2701. * Initialise to all 0xFF, to avoid the possibility of left over OOB
  2702. * data from a previous OOB read.
  2703. */
  2704. memset(chip->oob_poi, 0xff, mtd->oobsize);
  2705. switch (ops->mode) {
  2706. case MTD_OPS_PLACE_OOB:
  2707. case MTD_OPS_RAW:
  2708. memcpy(chip->oob_poi + ops->ooboffs, oob, len);
  2709. return oob + len;
  2710. case MTD_OPS_AUTO_OOB: {
  2711. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  2712. uint32_t boffs = 0, woffs = ops->ooboffs;
  2713. size_t bytes = 0;
  2714. for (; free->length && len; free++, len -= bytes) {
  2715. /* Write request not from offset 0? */
  2716. if (unlikely(woffs)) {
  2717. if (woffs >= free->length) {
  2718. woffs -= free->length;
  2719. continue;
  2720. }
  2721. boffs = free->offset + woffs;
  2722. bytes = min_t(size_t, len,
  2723. (free->length - woffs));
  2724. woffs = 0;
  2725. } else {
  2726. bytes = min_t(size_t, len, free->length);
  2727. boffs = free->offset;
  2728. }
  2729. memcpy(chip->oob_poi + boffs, oob, bytes);
  2730. oob += bytes;
  2731. }
  2732. return oob;
  2733. }
  2734. default:
  2735. BUG();
  2736. }
  2737. return NULL;
  2738. }
  2739. #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
  2740. /**
  2741. * nand_do_write_ops - [INTERN] NAND write with ECC
  2742. * @mtd: MTD device structure
  2743. * @to: offset to write to
  2744. * @ops: oob operations description structure
  2745. *
  2746. * NAND write with ECC.
  2747. */
  2748. static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
  2749. struct mtd_oob_ops *ops)
  2750. {
  2751. int chipnr, realpage, page, column;
  2752. struct nand_chip *chip = mtd_to_nand(mtd);
  2753. uint32_t writelen = ops->len;
  2754. uint32_t oobwritelen = ops->ooblen;
  2755. uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
  2756. uint8_t *oob = ops->oobbuf;
  2757. uint8_t *buf = ops->datbuf;
  2758. int ret;
  2759. int oob_required = oob ? 1 : 0;
  2760. ops->retlen = 0;
  2761. if (!writelen)
  2762. return 0;
  2763. /* Reject writes, which are not page aligned */
  2764. if (NOTALIGNED(to)) {
  2765. pr_notice("%s: attempt to write non page aligned data\n",
  2766. __func__);
  2767. return -EINVAL;
  2768. }
  2769. column = to & (mtd->writesize - 1);
  2770. chipnr = (int)(to >> chip->chip_shift);
  2771. chip->select_chip(mtd, chipnr);
  2772. /* Check, if it is write protected */
  2773. if (nand_check_wp(mtd)) {
  2774. ret = -EIO;
  2775. goto err_out;
  2776. }
  2777. realpage = (int)(to >> chip->page_shift);
  2778. page = realpage & chip->pagemask;
  2779. /* Invalidate the page cache, when we write to the cached page */
  2780. if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
  2781. ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
  2782. chip->pagebuf = -1;
  2783. /* Don't allow multipage oob writes with offset */
  2784. if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
  2785. ret = -EINVAL;
  2786. goto err_out;
  2787. }
  2788. while (1) {
  2789. int bytes = mtd->writesize;
  2790. uint8_t *wbuf = buf;
  2791. int use_bufpoi;
  2792. int part_pagewr = (column || writelen < mtd->writesize);
  2793. if (part_pagewr)
  2794. use_bufpoi = 1;
  2795. else if (chip->options & NAND_USE_BOUNCE_BUFFER)
  2796. use_bufpoi = !IS_ALIGNED((unsigned long)buf,
  2797. chip->buf_align);
  2798. else
  2799. use_bufpoi = 0;
  2800. WATCHDOG_RESET();
  2801. /* Partial page write?, or need to use bounce buffer */
  2802. if (use_bufpoi) {
  2803. pr_debug("%s: using write bounce buffer for buf@%p\n",
  2804. __func__, buf);
  2805. if (part_pagewr)
  2806. bytes = min_t(int, bytes - column, writelen);
  2807. chip->pagebuf = -1;
  2808. memset(chip->buffers->databuf, 0xff, mtd->writesize);
  2809. memcpy(&chip->buffers->databuf[column], buf, bytes);
  2810. wbuf = chip->buffers->databuf;
  2811. }
  2812. if (unlikely(oob)) {
  2813. size_t len = min(oobwritelen, oobmaxlen);
  2814. oob = nand_fill_oob(mtd, oob, len, ops);
  2815. oobwritelen -= len;
  2816. } else {
  2817. /* We still need to erase leftover OOB data */
  2818. memset(chip->oob_poi, 0xff, mtd->oobsize);
  2819. }
  2820. ret = chip->write_page(mtd, chip, column, bytes, wbuf,
  2821. oob_required, page,
  2822. (ops->mode == MTD_OPS_RAW));
  2823. if (ret)
  2824. break;
  2825. writelen -= bytes;
  2826. if (!writelen)
  2827. break;
  2828. column = 0;
  2829. buf += bytes;
  2830. realpage++;
  2831. page = realpage & chip->pagemask;
  2832. /* Check, if we cross a chip boundary */
  2833. if (!page) {
  2834. chipnr++;
  2835. chip->select_chip(mtd, -1);
  2836. chip->select_chip(mtd, chipnr);
  2837. }
  2838. }
  2839. ops->retlen = ops->len - writelen;
  2840. if (unlikely(oob))
  2841. ops->oobretlen = ops->ooblen;
  2842. err_out:
  2843. chip->select_chip(mtd, -1);
  2844. return ret;
  2845. }
  2846. /**
  2847. * panic_nand_write - [MTD Interface] NAND write with ECC
  2848. * @mtd: MTD device structure
  2849. * @to: offset to write to
  2850. * @len: number of bytes to write
  2851. * @retlen: pointer to variable to store the number of written bytes
  2852. * @buf: the data to write
  2853. *
  2854. * NAND write with ECC. Used when performing writes in interrupt context, this
  2855. * may for example be called by mtdoops when writing an oops while in panic.
  2856. */
  2857. static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
  2858. size_t *retlen, const uint8_t *buf)
  2859. {
  2860. struct nand_chip *chip = mtd_to_nand(mtd);
  2861. struct mtd_oob_ops ops;
  2862. int ret;
  2863. /* Wait for the device to get ready */
  2864. panic_nand_wait(mtd, chip, 400);
  2865. /* Grab the device */
  2866. panic_nand_get_device(chip, mtd, FL_WRITING);
  2867. memset(&ops, 0, sizeof(ops));
  2868. ops.len = len;
  2869. ops.datbuf = (uint8_t *)buf;
  2870. ops.mode = MTD_OPS_PLACE_OOB;
  2871. ret = nand_do_write_ops(mtd, to, &ops);
  2872. *retlen = ops.retlen;
  2873. return ret;
  2874. }
  2875. /**
  2876. * nand_do_write_oob - [MTD Interface] NAND write out-of-band
  2877. * @mtd: MTD device structure
  2878. * @to: offset to write to
  2879. * @ops: oob operation description structure
  2880. *
  2881. * NAND write out-of-band.
  2882. */
  2883. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  2884. struct mtd_oob_ops *ops)
  2885. {
  2886. int chipnr, page, status, len;
  2887. struct nand_chip *chip = mtd_to_nand(mtd);
  2888. pr_debug("%s: to = 0x%08x, len = %i\n",
  2889. __func__, (unsigned int)to, (int)ops->ooblen);
  2890. len = mtd_oobavail(mtd, ops);
  2891. /* Do not allow write past end of page */
  2892. if ((ops->ooboffs + ops->ooblen) > len) {
  2893. pr_debug("%s: attempt to write past end of page\n",
  2894. __func__);
  2895. return -EINVAL;
  2896. }
  2897. if (unlikely(ops->ooboffs >= len)) {
  2898. pr_debug("%s: attempt to start write outside oob\n",
  2899. __func__);
  2900. return -EINVAL;
  2901. }
  2902. /* Do not allow write past end of device */
  2903. if (unlikely(to >= mtd->size ||
  2904. ops->ooboffs + ops->ooblen >
  2905. ((mtd->size >> chip->page_shift) -
  2906. (to >> chip->page_shift)) * len)) {
  2907. pr_debug("%s: attempt to write beyond end of device\n",
  2908. __func__);
  2909. return -EINVAL;
  2910. }
  2911. chipnr = (int)(to >> chip->chip_shift);
  2912. /*
  2913. * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
  2914. * of my DiskOnChip 2000 test units) will clear the whole data page too
  2915. * if we don't do this. I have no clue why, but I seem to have 'fixed'
  2916. * it in the doc2000 driver in August 1999. dwmw2.
  2917. */
  2918. nand_reset(chip, chipnr);
  2919. chip->select_chip(mtd, chipnr);
  2920. /* Shift to get page */
  2921. page = (int)(to >> chip->page_shift);
  2922. /* Check, if it is write protected */
  2923. if (nand_check_wp(mtd)) {
  2924. chip->select_chip(mtd, -1);
  2925. return -EROFS;
  2926. }
  2927. /* Invalidate the page cache, if we write to the cached page */
  2928. if (page == chip->pagebuf)
  2929. chip->pagebuf = -1;
  2930. nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
  2931. if (ops->mode == MTD_OPS_RAW)
  2932. status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
  2933. else
  2934. status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
  2935. chip->select_chip(mtd, -1);
  2936. if (status)
  2937. return status;
  2938. ops->oobretlen = ops->ooblen;
  2939. return 0;
  2940. }
  2941. /**
  2942. * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
  2943. * @mtd: MTD device structure
  2944. * @to: offset to write to
  2945. * @ops: oob operation description structure
  2946. */
  2947. static int nand_write_oob(struct mtd_info *mtd, loff_t to,
  2948. struct mtd_oob_ops *ops)
  2949. {
  2950. int ret = -ENOTSUPP;
  2951. ops->retlen = 0;
  2952. /* Do not allow writes past end of device */
  2953. if (ops->datbuf && (to + ops->len) > mtd->size) {
  2954. pr_debug("%s: attempt to write beyond end of device\n",
  2955. __func__);
  2956. return -EINVAL;
  2957. }
  2958. nand_get_device(mtd, FL_WRITING);
  2959. switch (ops->mode) {
  2960. case MTD_OPS_PLACE_OOB:
  2961. case MTD_OPS_AUTO_OOB:
  2962. case MTD_OPS_RAW:
  2963. break;
  2964. default:
  2965. goto out;
  2966. }
  2967. if (!ops->datbuf)
  2968. ret = nand_do_write_oob(mtd, to, ops);
  2969. else
  2970. ret = nand_do_write_ops(mtd, to, ops);
  2971. out:
  2972. nand_release_device(mtd);
  2973. return ret;
  2974. }
  2975. /**
  2976. * single_erase - [GENERIC] NAND standard block erase command function
  2977. * @mtd: MTD device structure
  2978. * @page: the page address of the block which will be erased
  2979. *
  2980. * Standard erase command for NAND chips. Returns NAND status.
  2981. */
  2982. static int single_erase(struct mtd_info *mtd, int page)
  2983. {
  2984. struct nand_chip *chip = mtd_to_nand(mtd);
  2985. unsigned int eraseblock;
  2986. /* Send commands to erase a block */
  2987. eraseblock = page >> (chip->phys_erase_shift - chip->page_shift);
  2988. return nand_erase_op(chip, eraseblock);
  2989. }
  2990. /**
  2991. * nand_erase - [MTD Interface] erase block(s)
  2992. * @mtd: MTD device structure
  2993. * @instr: erase instruction
  2994. *
  2995. * Erase one ore more blocks.
  2996. */
  2997. static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
  2998. {
  2999. return nand_erase_nand(mtd, instr, 0);
  3000. }
  3001. /**
  3002. * nand_erase_nand - [INTERN] erase block(s)
  3003. * @mtd: MTD device structure
  3004. * @instr: erase instruction
  3005. * @allowbbt: allow erasing the bbt area
  3006. *
  3007. * Erase one ore more blocks.
  3008. */
  3009. int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  3010. int allowbbt)
  3011. {
  3012. int page, status, pages_per_block, ret, chipnr;
  3013. struct nand_chip *chip = mtd_to_nand(mtd);
  3014. loff_t len;
  3015. pr_debug("%s: start = 0x%012llx, len = %llu\n",
  3016. __func__, (unsigned long long)instr->addr,
  3017. (unsigned long long)instr->len);
  3018. if (check_offs_len(mtd, instr->addr, instr->len))
  3019. return -EINVAL;
  3020. /* Grab the lock and see if the device is available */
  3021. nand_get_device(mtd, FL_ERASING);
  3022. /* Shift to get first page */
  3023. page = (int)(instr->addr >> chip->page_shift);
  3024. chipnr = (int)(instr->addr >> chip->chip_shift);
  3025. /* Calculate pages in each block */
  3026. pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
  3027. /* Select the NAND device */
  3028. chip->select_chip(mtd, chipnr);
  3029. /* Check, if it is write protected */
  3030. if (nand_check_wp(mtd)) {
  3031. pr_debug("%s: device is write protected!\n",
  3032. __func__);
  3033. instr->state = MTD_ERASE_FAILED;
  3034. goto erase_exit;
  3035. }
  3036. /* Loop through the pages */
  3037. len = instr->len;
  3038. instr->state = MTD_ERASING;
  3039. while (len) {
  3040. WATCHDOG_RESET();
  3041. /* Check if we have a bad block, we do not erase bad blocks! */
  3042. if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
  3043. chip->page_shift, allowbbt)) {
  3044. pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
  3045. __func__, page);
  3046. instr->state = MTD_ERASE_FAILED;
  3047. goto erase_exit;
  3048. }
  3049. /*
  3050. * Invalidate the page cache, if we erase the block which
  3051. * contains the current cached page.
  3052. */
  3053. if (page <= chip->pagebuf && chip->pagebuf <
  3054. (page + pages_per_block))
  3055. chip->pagebuf = -1;
  3056. status = chip->erase(mtd, page & chip->pagemask);
  3057. /* See if block erase succeeded */
  3058. if (status & NAND_STATUS_FAIL) {
  3059. pr_debug("%s: failed erase, page 0x%08x\n",
  3060. __func__, page);
  3061. instr->state = MTD_ERASE_FAILED;
  3062. instr->fail_addr =
  3063. ((loff_t)page << chip->page_shift);
  3064. goto erase_exit;
  3065. }
  3066. /* Increment page address and decrement length */
  3067. len -= (1ULL << chip->phys_erase_shift);
  3068. page += pages_per_block;
  3069. /* Check, if we cross a chip boundary */
  3070. if (len && !(page & chip->pagemask)) {
  3071. chipnr++;
  3072. chip->select_chip(mtd, -1);
  3073. chip->select_chip(mtd, chipnr);
  3074. }
  3075. }
  3076. instr->state = MTD_ERASE_DONE;
  3077. erase_exit:
  3078. ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
  3079. /* Deselect and wake up anyone waiting on the device */
  3080. chip->select_chip(mtd, -1);
  3081. nand_release_device(mtd);
  3082. /* Do call back function */
  3083. if (!ret)
  3084. mtd_erase_callback(instr);
  3085. /* Return more or less happy */
  3086. return ret;
  3087. }
  3088. /**
  3089. * nand_sync - [MTD Interface] sync
  3090. * @mtd: MTD device structure
  3091. *
  3092. * Sync is actually a wait for chip ready function.
  3093. */
  3094. static void nand_sync(struct mtd_info *mtd)
  3095. {
  3096. pr_debug("%s: called\n", __func__);
  3097. /* Grab the lock and see if the device is available */
  3098. nand_get_device(mtd, FL_SYNCING);
  3099. /* Release it and go back */
  3100. nand_release_device(mtd);
  3101. }
  3102. /**
  3103. * nand_block_isbad - [MTD Interface] Check if block at offset is bad
  3104. * @mtd: MTD device structure
  3105. * @offs: offset relative to mtd start
  3106. */
  3107. static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
  3108. {
  3109. struct nand_chip *chip = mtd_to_nand(mtd);
  3110. int chipnr = (int)(offs >> chip->chip_shift);
  3111. int ret;
  3112. /* Select the NAND device */
  3113. nand_get_device(mtd, FL_READING);
  3114. chip->select_chip(mtd, chipnr);
  3115. ret = nand_block_checkbad(mtd, offs, 0);
  3116. chip->select_chip(mtd, -1);
  3117. nand_release_device(mtd);
  3118. return ret;
  3119. }
  3120. /**
  3121. * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
  3122. * @mtd: MTD device structure
  3123. * @ofs: offset relative to mtd start
  3124. */
  3125. static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
  3126. {
  3127. int ret;
  3128. ret = nand_block_isbad(mtd, ofs);
  3129. if (ret) {
  3130. /* If it was bad already, return success and do nothing */
  3131. if (ret > 0)
  3132. return 0;
  3133. return ret;
  3134. }
  3135. return nand_block_markbad_lowlevel(mtd, ofs);
  3136. }
  3137. /**
  3138. * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
  3139. * @mtd: MTD device structure
  3140. * @chip: nand chip info structure
  3141. * @addr: feature address.
  3142. * @subfeature_param: the subfeature parameters, a four bytes array.
  3143. */
  3144. static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
  3145. int addr, uint8_t *subfeature_param)
  3146. {
  3147. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  3148. if (!chip->onfi_version ||
  3149. !(le16_to_cpu(chip->onfi_params.opt_cmd)
  3150. & ONFI_OPT_CMD_SET_GET_FEATURES))
  3151. return -ENOTSUPP;
  3152. #endif
  3153. return nand_set_features_op(chip, addr, subfeature_param);
  3154. }
  3155. /**
  3156. * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
  3157. * @mtd: MTD device structure
  3158. * @chip: nand chip info structure
  3159. * @addr: feature address.
  3160. * @subfeature_param: the subfeature parameters, a four bytes array.
  3161. */
  3162. static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
  3163. int addr, uint8_t *subfeature_param)
  3164. {
  3165. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  3166. if (!chip->onfi_version ||
  3167. !(le16_to_cpu(chip->onfi_params.opt_cmd)
  3168. & ONFI_OPT_CMD_SET_GET_FEATURES))
  3169. return -ENOTSUPP;
  3170. #endif
  3171. return nand_get_features_op(chip, addr, subfeature_param);
  3172. }
  3173. /* Set default functions */
  3174. static void nand_set_defaults(struct nand_chip *chip, int busw)
  3175. {
  3176. /* check for proper chip_delay setup, set 20us if not */
  3177. if (!chip->chip_delay)
  3178. chip->chip_delay = 20;
  3179. /* check, if a user supplied command function given */
  3180. if (chip->cmdfunc == NULL)
  3181. chip->cmdfunc = nand_command;
  3182. /* check, if a user supplied wait function given */
  3183. if (chip->waitfunc == NULL)
  3184. chip->waitfunc = nand_wait;
  3185. if (!chip->select_chip)
  3186. chip->select_chip = nand_select_chip;
  3187. /* set for ONFI nand */
  3188. if (!chip->onfi_set_features)
  3189. chip->onfi_set_features = nand_onfi_set_features;
  3190. if (!chip->onfi_get_features)
  3191. chip->onfi_get_features = nand_onfi_get_features;
  3192. /* If called twice, pointers that depend on busw may need to be reset */
  3193. if (!chip->read_byte || chip->read_byte == nand_read_byte)
  3194. chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
  3195. if (!chip->read_word)
  3196. chip->read_word = nand_read_word;
  3197. if (!chip->block_bad)
  3198. chip->block_bad = nand_block_bad;
  3199. if (!chip->block_markbad)
  3200. chip->block_markbad = nand_default_block_markbad;
  3201. if (!chip->write_buf || chip->write_buf == nand_write_buf)
  3202. chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
  3203. if (!chip->write_byte || chip->write_byte == nand_write_byte)
  3204. chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
  3205. if (!chip->read_buf || chip->read_buf == nand_read_buf)
  3206. chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
  3207. if (!chip->scan_bbt)
  3208. chip->scan_bbt = nand_default_bbt;
  3209. if (!chip->controller) {
  3210. chip->controller = &chip->hwcontrol;
  3211. spin_lock_init(&chip->controller->lock);
  3212. init_waitqueue_head(&chip->controller->wq);
  3213. }
  3214. if (!chip->buf_align)
  3215. chip->buf_align = 1;
  3216. }
  3217. /* Sanitize ONFI strings so we can safely print them */
  3218. static void sanitize_string(char *s, size_t len)
  3219. {
  3220. ssize_t i;
  3221. /* Null terminate */
  3222. s[len - 1] = 0;
  3223. /* Remove non printable chars */
  3224. for (i = 0; i < len - 1; i++) {
  3225. if (s[i] < ' ' || s[i] > 127)
  3226. s[i] = '?';
  3227. }
  3228. /* Remove trailing spaces */
  3229. strim(s);
  3230. }
  3231. static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
  3232. {
  3233. int i;
  3234. while (len--) {
  3235. crc ^= *p++ << 8;
  3236. for (i = 0; i < 8; i++)
  3237. crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
  3238. }
  3239. return crc;
  3240. }
  3241. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  3242. /* Parse the Extended Parameter Page. */
  3243. static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
  3244. struct nand_chip *chip, struct nand_onfi_params *p)
  3245. {
  3246. struct onfi_ext_param_page *ep;
  3247. struct onfi_ext_section *s;
  3248. struct onfi_ext_ecc_info *ecc;
  3249. uint8_t *cursor;
  3250. int ret;
  3251. int len;
  3252. int i;
  3253. len = le16_to_cpu(p->ext_param_page_length) * 16;
  3254. ep = kmalloc(len, GFP_KERNEL);
  3255. if (!ep)
  3256. return -ENOMEM;
  3257. /* Send our own NAND_CMD_PARAM. */
  3258. ret = nand_read_param_page_op(chip, 0, NULL, 0);
  3259. if (ret)
  3260. goto ext_out;
  3261. /* Use the Change Read Column command to skip the ONFI param pages. */
  3262. ret = nand_change_read_column_op(chip,
  3263. sizeof(*p) * p->num_of_param_pages,
  3264. ep, len, true);
  3265. if (ret)
  3266. goto ext_out;
  3267. ret = -EINVAL;
  3268. if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
  3269. != le16_to_cpu(ep->crc))) {
  3270. pr_debug("fail in the CRC.\n");
  3271. goto ext_out;
  3272. }
  3273. /*
  3274. * Check the signature.
  3275. * Do not strictly follow the ONFI spec, maybe changed in future.
  3276. */
  3277. if (strncmp((char *)ep->sig, "EPPS", 4)) {
  3278. pr_debug("The signature is invalid.\n");
  3279. goto ext_out;
  3280. }
  3281. /* find the ECC section. */
  3282. cursor = (uint8_t *)(ep + 1);
  3283. for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
  3284. s = ep->sections + i;
  3285. if (s->type == ONFI_SECTION_TYPE_2)
  3286. break;
  3287. cursor += s->length * 16;
  3288. }
  3289. if (i == ONFI_EXT_SECTION_MAX) {
  3290. pr_debug("We can not find the ECC section.\n");
  3291. goto ext_out;
  3292. }
  3293. /* get the info we want. */
  3294. ecc = (struct onfi_ext_ecc_info *)cursor;
  3295. if (!ecc->codeword_size) {
  3296. pr_debug("Invalid codeword size\n");
  3297. goto ext_out;
  3298. }
  3299. chip->ecc_strength_ds = ecc->ecc_bits;
  3300. chip->ecc_step_ds = 1 << ecc->codeword_size;
  3301. ret = 0;
  3302. ext_out:
  3303. kfree(ep);
  3304. return ret;
  3305. }
  3306. static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
  3307. {
  3308. struct nand_chip *chip = mtd_to_nand(mtd);
  3309. uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
  3310. return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
  3311. feature);
  3312. }
  3313. /*
  3314. * Configure chip properties from Micron vendor-specific ONFI table
  3315. */
  3316. static void nand_onfi_detect_micron(struct nand_chip *chip,
  3317. struct nand_onfi_params *p)
  3318. {
  3319. struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
  3320. if (le16_to_cpu(p->vendor_revision) < 1)
  3321. return;
  3322. chip->read_retries = micron->read_retry_options;
  3323. chip->setup_read_retry = nand_setup_read_retry_micron;
  3324. }
  3325. /*
  3326. * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
  3327. */
  3328. static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
  3329. int *busw)
  3330. {
  3331. struct nand_onfi_params *p = &chip->onfi_params;
  3332. char id[4];
  3333. int i, ret, val;
  3334. /* Try ONFI for unknown chip or LP */
  3335. ret = nand_readid_op(chip, 0x20, id, sizeof(id));
  3336. if (ret || strncmp(id, "ONFI", 4))
  3337. return 0;
  3338. ret = nand_read_param_page_op(chip, 0, NULL, 0);
  3339. if (ret)
  3340. return 0;
  3341. for (i = 0; i < 3; i++) {
  3342. ret = nand_read_data_op(chip, p, sizeof(*p), true);
  3343. if (ret)
  3344. return 0;
  3345. if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
  3346. le16_to_cpu(p->crc)) {
  3347. break;
  3348. }
  3349. }
  3350. if (i == 3) {
  3351. pr_err("Could not find valid ONFI parameter page; aborting\n");
  3352. return 0;
  3353. }
  3354. /* Check version */
  3355. val = le16_to_cpu(p->revision);
  3356. if (val & (1 << 5))
  3357. chip->onfi_version = 23;
  3358. else if (val & (1 << 4))
  3359. chip->onfi_version = 22;
  3360. else if (val & (1 << 3))
  3361. chip->onfi_version = 21;
  3362. else if (val & (1 << 2))
  3363. chip->onfi_version = 20;
  3364. else if (val & (1 << 1))
  3365. chip->onfi_version = 10;
  3366. if (!chip->onfi_version) {
  3367. pr_info("unsupported ONFI version: %d\n", val);
  3368. return 0;
  3369. }
  3370. sanitize_string(p->manufacturer, sizeof(p->manufacturer));
  3371. sanitize_string(p->model, sizeof(p->model));
  3372. if (!mtd->name)
  3373. mtd->name = p->model;
  3374. mtd->writesize = le32_to_cpu(p->byte_per_page);
  3375. /*
  3376. * pages_per_block and blocks_per_lun may not be a power-of-2 size
  3377. * (don't ask me who thought of this...). MTD assumes that these
  3378. * dimensions will be power-of-2, so just truncate the remaining area.
  3379. */
  3380. mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
  3381. mtd->erasesize *= mtd->writesize;
  3382. mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
  3383. /* See erasesize comment */
  3384. chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
  3385. chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
  3386. chip->bits_per_cell = p->bits_per_cell;
  3387. if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
  3388. *busw = NAND_BUSWIDTH_16;
  3389. else
  3390. *busw = 0;
  3391. if (p->ecc_bits != 0xff) {
  3392. chip->ecc_strength_ds = p->ecc_bits;
  3393. chip->ecc_step_ds = 512;
  3394. } else if (chip->onfi_version >= 21 &&
  3395. (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
  3396. /*
  3397. * The nand_flash_detect_ext_param_page() uses the
  3398. * Change Read Column command which maybe not supported
  3399. * by the chip->cmdfunc. So try to update the chip->cmdfunc
  3400. * now. We do not replace user supplied command function.
  3401. */
  3402. if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
  3403. chip->cmdfunc = nand_command_lp;
  3404. /* The Extended Parameter Page is supported since ONFI 2.1. */
  3405. if (nand_flash_detect_ext_param_page(mtd, chip, p))
  3406. pr_warn("Failed to detect ONFI extended param page\n");
  3407. } else {
  3408. pr_warn("Could not retrieve ONFI ECC requirements\n");
  3409. }
  3410. if (p->jedec_id == NAND_MFR_MICRON)
  3411. nand_onfi_detect_micron(chip, p);
  3412. return 1;
  3413. }
  3414. #else
  3415. static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
  3416. int *busw)
  3417. {
  3418. return 0;
  3419. }
  3420. #endif
  3421. /*
  3422. * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
  3423. */
  3424. static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
  3425. int *busw)
  3426. {
  3427. struct nand_jedec_params *p = &chip->jedec_params;
  3428. struct jedec_ecc_info *ecc;
  3429. char id[5];
  3430. int i, val, ret;
  3431. /* Try JEDEC for unknown chip or LP */
  3432. ret = nand_readid_op(chip, 0x40, id, sizeof(id));
  3433. if (ret || strncmp(id, "JEDEC", sizeof(id)))
  3434. return 0;
  3435. ret = nand_read_param_page_op(chip, 0x40, NULL, 0);
  3436. if (ret)
  3437. return 0;
  3438. for (i = 0; i < 3; i++) {
  3439. ret = nand_read_data_op(chip, p, sizeof(*p), true);
  3440. if (ret)
  3441. return 0;
  3442. if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
  3443. le16_to_cpu(p->crc))
  3444. break;
  3445. }
  3446. if (i == 3) {
  3447. pr_err("Could not find valid JEDEC parameter page; aborting\n");
  3448. return 0;
  3449. }
  3450. /* Check version */
  3451. val = le16_to_cpu(p->revision);
  3452. if (val & (1 << 2))
  3453. chip->jedec_version = 10;
  3454. else if (val & (1 << 1))
  3455. chip->jedec_version = 1; /* vendor specific version */
  3456. if (!chip->jedec_version) {
  3457. pr_info("unsupported JEDEC version: %d\n", val);
  3458. return 0;
  3459. }
  3460. sanitize_string(p->manufacturer, sizeof(p->manufacturer));
  3461. sanitize_string(p->model, sizeof(p->model));
  3462. if (!mtd->name)
  3463. mtd->name = p->model;
  3464. mtd->writesize = le32_to_cpu(p->byte_per_page);
  3465. /* Please reference to the comment for nand_flash_detect_onfi. */
  3466. mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
  3467. mtd->erasesize *= mtd->writesize;
  3468. mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
  3469. /* Please reference to the comment for nand_flash_detect_onfi. */
  3470. chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
  3471. chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
  3472. chip->bits_per_cell = p->bits_per_cell;
  3473. if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
  3474. *busw = NAND_BUSWIDTH_16;
  3475. else
  3476. *busw = 0;
  3477. /* ECC info */
  3478. ecc = &p->ecc_info[0];
  3479. if (ecc->codeword_size >= 9) {
  3480. chip->ecc_strength_ds = ecc->ecc_bits;
  3481. chip->ecc_step_ds = 1 << ecc->codeword_size;
  3482. } else {
  3483. pr_warn("Invalid codeword size\n");
  3484. }
  3485. return 1;
  3486. }
  3487. /*
  3488. * nand_id_has_period - Check if an ID string has a given wraparound period
  3489. * @id_data: the ID string
  3490. * @arrlen: the length of the @id_data array
  3491. * @period: the period of repitition
  3492. *
  3493. * Check if an ID string is repeated within a given sequence of bytes at
  3494. * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
  3495. * period of 3). This is a helper function for nand_id_len(). Returns non-zero
  3496. * if the repetition has a period of @period; otherwise, returns zero.
  3497. */
  3498. static int nand_id_has_period(u8 *id_data, int arrlen, int period)
  3499. {
  3500. int i, j;
  3501. for (i = 0; i < period; i++)
  3502. for (j = i + period; j < arrlen; j += period)
  3503. if (id_data[i] != id_data[j])
  3504. return 0;
  3505. return 1;
  3506. }
  3507. /*
  3508. * nand_id_len - Get the length of an ID string returned by CMD_READID
  3509. * @id_data: the ID string
  3510. * @arrlen: the length of the @id_data array
  3511. * Returns the length of the ID string, according to known wraparound/trailing
  3512. * zero patterns. If no pattern exists, returns the length of the array.
  3513. */
  3514. static int nand_id_len(u8 *id_data, int arrlen)
  3515. {
  3516. int last_nonzero, period;
  3517. /* Find last non-zero byte */
  3518. for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
  3519. if (id_data[last_nonzero])
  3520. break;
  3521. /* All zeros */
  3522. if (last_nonzero < 0)
  3523. return 0;
  3524. /* Calculate wraparound period */
  3525. for (period = 1; period < arrlen; period++)
  3526. if (nand_id_has_period(id_data, arrlen, period))
  3527. break;
  3528. /* There's a repeated pattern */
  3529. if (period < arrlen)
  3530. return period;
  3531. /* There are trailing zeros */
  3532. if (last_nonzero < arrlen - 1)
  3533. return last_nonzero + 1;
  3534. /* No pattern detected */
  3535. return arrlen;
  3536. }
  3537. /* Extract the bits of per cell from the 3rd byte of the extended ID */
  3538. static int nand_get_bits_per_cell(u8 cellinfo)
  3539. {
  3540. int bits;
  3541. bits = cellinfo & NAND_CI_CELLTYPE_MSK;
  3542. bits >>= NAND_CI_CELLTYPE_SHIFT;
  3543. return bits + 1;
  3544. }
  3545. /*
  3546. * Many new NAND share similar device ID codes, which represent the size of the
  3547. * chip. The rest of the parameters must be decoded according to generic or
  3548. * manufacturer-specific "extended ID" decoding patterns.
  3549. */
  3550. static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
  3551. u8 id_data[8], int *busw)
  3552. {
  3553. int extid, id_len;
  3554. /* The 3rd id byte holds MLC / multichip data */
  3555. chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
  3556. /* The 4th id byte is the important one */
  3557. extid = id_data[3];
  3558. id_len = nand_id_len(id_data, 8);
  3559. /*
  3560. * Field definitions are in the following datasheets:
  3561. * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
  3562. * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
  3563. * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
  3564. *
  3565. * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
  3566. * ID to decide what to do.
  3567. */
  3568. if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
  3569. !nand_is_slc(chip) && id_data[5] != 0x00) {
  3570. /* Calc pagesize */
  3571. mtd->writesize = 2048 << (extid & 0x03);
  3572. extid >>= 2;
  3573. /* Calc oobsize */
  3574. switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
  3575. case 1:
  3576. mtd->oobsize = 128;
  3577. break;
  3578. case 2:
  3579. mtd->oobsize = 218;
  3580. break;
  3581. case 3:
  3582. mtd->oobsize = 400;
  3583. break;
  3584. case 4:
  3585. mtd->oobsize = 436;
  3586. break;
  3587. case 5:
  3588. mtd->oobsize = 512;
  3589. break;
  3590. case 6:
  3591. mtd->oobsize = 640;
  3592. break;
  3593. case 7:
  3594. default: /* Other cases are "reserved" (unknown) */
  3595. mtd->oobsize = 1024;
  3596. break;
  3597. }
  3598. extid >>= 2;
  3599. /* Calc blocksize */
  3600. mtd->erasesize = (128 * 1024) <<
  3601. (((extid >> 1) & 0x04) | (extid & 0x03));
  3602. *busw = 0;
  3603. } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
  3604. !nand_is_slc(chip)) {
  3605. unsigned int tmp;
  3606. /* Calc pagesize */
  3607. mtd->writesize = 2048 << (extid & 0x03);
  3608. extid >>= 2;
  3609. /* Calc oobsize */
  3610. switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
  3611. case 0:
  3612. mtd->oobsize = 128;
  3613. break;
  3614. case 1:
  3615. mtd->oobsize = 224;
  3616. break;
  3617. case 2:
  3618. mtd->oobsize = 448;
  3619. break;
  3620. case 3:
  3621. mtd->oobsize = 64;
  3622. break;
  3623. case 4:
  3624. mtd->oobsize = 32;
  3625. break;
  3626. case 5:
  3627. mtd->oobsize = 16;
  3628. break;
  3629. default:
  3630. mtd->oobsize = 640;
  3631. break;
  3632. }
  3633. extid >>= 2;
  3634. /* Calc blocksize */
  3635. tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
  3636. if (tmp < 0x03)
  3637. mtd->erasesize = (128 * 1024) << tmp;
  3638. else if (tmp == 0x03)
  3639. mtd->erasesize = 768 * 1024;
  3640. else
  3641. mtd->erasesize = (64 * 1024) << tmp;
  3642. *busw = 0;
  3643. } else {
  3644. /* Calc pagesize */
  3645. mtd->writesize = 1024 << (extid & 0x03);
  3646. extid >>= 2;
  3647. /* Calc oobsize */
  3648. mtd->oobsize = (8 << (extid & 0x01)) *
  3649. (mtd->writesize >> 9);
  3650. extid >>= 2;
  3651. /* Calc blocksize. Blocksize is multiples of 64KiB */
  3652. mtd->erasesize = (64 * 1024) << (extid & 0x03);
  3653. extid >>= 2;
  3654. /* Get buswidth information */
  3655. *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
  3656. /*
  3657. * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
  3658. * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
  3659. * follows:
  3660. * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
  3661. * 110b -> 24nm
  3662. * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
  3663. */
  3664. if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
  3665. nand_is_slc(chip) &&
  3666. (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
  3667. !(id_data[4] & 0x80) /* !BENAND */) {
  3668. mtd->oobsize = 32 * mtd->writesize >> 9;
  3669. }
  3670. }
  3671. }
  3672. /*
  3673. * Old devices have chip data hardcoded in the device ID table. nand_decode_id
  3674. * decodes a matching ID table entry and assigns the MTD size parameters for
  3675. * the chip.
  3676. */
  3677. static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
  3678. struct nand_flash_dev *type, u8 id_data[8],
  3679. int *busw)
  3680. {
  3681. int maf_id = id_data[0];
  3682. mtd->erasesize = type->erasesize;
  3683. mtd->writesize = type->pagesize;
  3684. mtd->oobsize = mtd->writesize / 32;
  3685. *busw = type->options & NAND_BUSWIDTH_16;
  3686. /* All legacy ID NAND are small-page, SLC */
  3687. chip->bits_per_cell = 1;
  3688. /*
  3689. * Check for Spansion/AMD ID + repeating 5th, 6th byte since
  3690. * some Spansion chips have erasesize that conflicts with size
  3691. * listed in nand_ids table.
  3692. * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
  3693. */
  3694. if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
  3695. && id_data[6] == 0x00 && id_data[7] == 0x00
  3696. && mtd->writesize == 512) {
  3697. mtd->erasesize = 128 * 1024;
  3698. mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
  3699. }
  3700. }
  3701. /*
  3702. * Set the bad block marker/indicator (BBM/BBI) patterns according to some
  3703. * heuristic patterns using various detected parameters (e.g., manufacturer,
  3704. * page size, cell-type information).
  3705. */
  3706. static void nand_decode_bbm_options(struct mtd_info *mtd,
  3707. struct nand_chip *chip, u8 id_data[8])
  3708. {
  3709. int maf_id = id_data[0];
  3710. /* Set the bad block position */
  3711. if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
  3712. chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
  3713. else
  3714. chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
  3715. /*
  3716. * Bad block marker is stored in the last page of each block on Samsung
  3717. * and Hynix MLC devices; stored in first two pages of each block on
  3718. * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
  3719. * AMD/Spansion, and Macronix. All others scan only the first page.
  3720. */
  3721. if (!nand_is_slc(chip) &&
  3722. (maf_id == NAND_MFR_SAMSUNG ||
  3723. maf_id == NAND_MFR_HYNIX))
  3724. chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
  3725. else if ((nand_is_slc(chip) &&
  3726. (maf_id == NAND_MFR_SAMSUNG ||
  3727. maf_id == NAND_MFR_HYNIX ||
  3728. maf_id == NAND_MFR_TOSHIBA ||
  3729. maf_id == NAND_MFR_AMD ||
  3730. maf_id == NAND_MFR_MACRONIX)) ||
  3731. (mtd->writesize == 2048 &&
  3732. maf_id == NAND_MFR_MICRON))
  3733. chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
  3734. }
  3735. static inline bool is_full_id_nand(struct nand_flash_dev *type)
  3736. {
  3737. return type->id_len;
  3738. }
  3739. static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
  3740. struct nand_flash_dev *type, u8 *id_data, int *busw)
  3741. {
  3742. if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
  3743. mtd->writesize = type->pagesize;
  3744. mtd->erasesize = type->erasesize;
  3745. mtd->oobsize = type->oobsize;
  3746. chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
  3747. chip->chipsize = (uint64_t)type->chipsize << 20;
  3748. chip->options |= type->options;
  3749. chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
  3750. chip->ecc_step_ds = NAND_ECC_STEP(type);
  3751. chip->onfi_timing_mode_default =
  3752. type->onfi_timing_mode_default;
  3753. *busw = type->options & NAND_BUSWIDTH_16;
  3754. if (!mtd->name)
  3755. mtd->name = type->name;
  3756. return true;
  3757. }
  3758. return false;
  3759. }
  3760. /*
  3761. * Get the flash and manufacturer id and lookup if the type is supported.
  3762. */
  3763. struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
  3764. struct nand_chip *chip,
  3765. int *maf_id, int *dev_id,
  3766. struct nand_flash_dev *type)
  3767. {
  3768. int busw, ret;
  3769. int maf_idx;
  3770. u8 id_data[8];
  3771. /*
  3772. * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
  3773. * after power-up.
  3774. */
  3775. ret = nand_reset(chip, 0);
  3776. if (ret)
  3777. return ERR_PTR(ret);
  3778. /* Select the device */
  3779. chip->select_chip(mtd, 0);
  3780. /* Send the command for reading device ID */
  3781. ret = nand_readid_op(chip, 0, id_data, 2);
  3782. if (ret)
  3783. return ERR_PTR(ret);
  3784. /* Read manufacturer and device IDs */
  3785. *maf_id = id_data[0];
  3786. *dev_id = id_data[1];
  3787. /*
  3788. * Try again to make sure, as some systems the bus-hold or other
  3789. * interface concerns can cause random data which looks like a
  3790. * possibly credible NAND flash to appear. If the two results do
  3791. * not match, ignore the device completely.
  3792. */
  3793. /* Read entire ID string */
  3794. ret = nand_readid_op(chip, 0, id_data, 8);
  3795. if (ret)
  3796. return ERR_PTR(ret);
  3797. if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
  3798. pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
  3799. *maf_id, *dev_id, id_data[0], id_data[1]);
  3800. return ERR_PTR(-ENODEV);
  3801. }
  3802. if (!type)
  3803. type = nand_flash_ids;
  3804. for (; type->name != NULL; type++) {
  3805. if (is_full_id_nand(type)) {
  3806. if (find_full_id_nand(mtd, chip, type, id_data, &busw))
  3807. goto ident_done;
  3808. } else if (*dev_id == type->dev_id) {
  3809. break;
  3810. }
  3811. }
  3812. chip->onfi_version = 0;
  3813. if (!type->name || !type->pagesize) {
  3814. /* Check if the chip is ONFI compliant */
  3815. if (nand_flash_detect_onfi(mtd, chip, &busw))
  3816. goto ident_done;
  3817. /* Check if the chip is JEDEC compliant */
  3818. if (nand_flash_detect_jedec(mtd, chip, &busw))
  3819. goto ident_done;
  3820. }
  3821. if (!type->name)
  3822. return ERR_PTR(-ENODEV);
  3823. if (!mtd->name)
  3824. mtd->name = type->name;
  3825. chip->chipsize = (uint64_t)type->chipsize << 20;
  3826. if (!type->pagesize) {
  3827. /* Decode parameters from extended ID */
  3828. nand_decode_ext_id(mtd, chip, id_data, &busw);
  3829. } else {
  3830. nand_decode_id(mtd, chip, type, id_data, &busw);
  3831. }
  3832. /* Get chip options */
  3833. chip->options |= type->options;
  3834. /*
  3835. * Check if chip is not a Samsung device. Do not clear the
  3836. * options for chips which do not have an extended id.
  3837. */
  3838. if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
  3839. chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
  3840. ident_done:
  3841. /* Try to identify manufacturer */
  3842. for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
  3843. if (nand_manuf_ids[maf_idx].id == *maf_id)
  3844. break;
  3845. }
  3846. if (chip->options & NAND_BUSWIDTH_AUTO) {
  3847. WARN_ON(chip->options & NAND_BUSWIDTH_16);
  3848. chip->options |= busw;
  3849. nand_set_defaults(chip, busw);
  3850. } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
  3851. /*
  3852. * Check, if buswidth is correct. Hardware drivers should set
  3853. * chip correct!
  3854. */
  3855. pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
  3856. *maf_id, *dev_id);
  3857. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
  3858. pr_warn("bus width %d instead %d bit\n",
  3859. (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
  3860. busw ? 16 : 8);
  3861. return ERR_PTR(-EINVAL);
  3862. }
  3863. nand_decode_bbm_options(mtd, chip, id_data);
  3864. /* Calculate the address shift from the page size */
  3865. chip->page_shift = ffs(mtd->writesize) - 1;
  3866. /* Convert chipsize to number of pages per chip -1 */
  3867. chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
  3868. chip->bbt_erase_shift = chip->phys_erase_shift =
  3869. ffs(mtd->erasesize) - 1;
  3870. if (chip->chipsize & 0xffffffff)
  3871. chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
  3872. else {
  3873. chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
  3874. chip->chip_shift += 32 - 1;
  3875. }
  3876. if (chip->chip_shift - chip->page_shift > 16)
  3877. chip->options |= NAND_ROW_ADDR_3;
  3878. chip->badblockbits = 8;
  3879. chip->erase = single_erase;
  3880. /* Do not replace user supplied command function! */
  3881. if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
  3882. chip->cmdfunc = nand_command_lp;
  3883. pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
  3884. *maf_id, *dev_id);
  3885. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  3886. if (chip->onfi_version)
  3887. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3888. chip->onfi_params.model);
  3889. else if (chip->jedec_version)
  3890. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3891. chip->jedec_params.model);
  3892. else
  3893. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3894. type->name);
  3895. #else
  3896. if (chip->jedec_version)
  3897. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3898. chip->jedec_params.model);
  3899. else
  3900. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3901. type->name);
  3902. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3903. type->name);
  3904. #endif
  3905. pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
  3906. (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
  3907. mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
  3908. return type;
  3909. }
  3910. EXPORT_SYMBOL(nand_get_flash_type);
  3911. #if CONFIG_IS_ENABLED(OF_CONTROL)
  3912. DECLARE_GLOBAL_DATA_PTR;
  3913. static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
  3914. {
  3915. int ret, ecc_mode = -1, ecc_strength, ecc_step;
  3916. const void *blob = gd->fdt_blob;
  3917. const char *str;
  3918. ret = fdtdec_get_int(blob, node, "nand-bus-width", -1);
  3919. if (ret == 16)
  3920. chip->options |= NAND_BUSWIDTH_16;
  3921. if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt"))
  3922. chip->bbt_options |= NAND_BBT_USE_FLASH;
  3923. str = fdt_getprop(blob, node, "nand-ecc-mode", NULL);
  3924. if (str) {
  3925. if (!strcmp(str, "none"))
  3926. ecc_mode = NAND_ECC_NONE;
  3927. else if (!strcmp(str, "soft"))
  3928. ecc_mode = NAND_ECC_SOFT;
  3929. else if (!strcmp(str, "hw"))
  3930. ecc_mode = NAND_ECC_HW;
  3931. else if (!strcmp(str, "hw_syndrome"))
  3932. ecc_mode = NAND_ECC_HW_SYNDROME;
  3933. else if (!strcmp(str, "hw_oob_first"))
  3934. ecc_mode = NAND_ECC_HW_OOB_FIRST;
  3935. else if (!strcmp(str, "soft_bch"))
  3936. ecc_mode = NAND_ECC_SOFT_BCH;
  3937. }
  3938. ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1);
  3939. ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1);
  3940. if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
  3941. (!(ecc_step >= 0) && ecc_strength >= 0)) {
  3942. pr_err("must set both strength and step size in DT\n");
  3943. return -EINVAL;
  3944. }
  3945. if (ecc_mode >= 0)
  3946. chip->ecc.mode = ecc_mode;
  3947. if (ecc_strength >= 0)
  3948. chip->ecc.strength = ecc_strength;
  3949. if (ecc_step > 0)
  3950. chip->ecc.size = ecc_step;
  3951. if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL))
  3952. chip->ecc.options |= NAND_ECC_MAXIMIZE;
  3953. return 0;
  3954. }
  3955. #else
  3956. static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
  3957. {
  3958. return 0;
  3959. }
  3960. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  3961. /**
  3962. * nand_scan_ident - [NAND Interface] Scan for the NAND device
  3963. * @mtd: MTD device structure
  3964. * @maxchips: number of chips to scan for
  3965. * @table: alternative NAND ID table
  3966. *
  3967. * This is the first phase of the normal nand_scan() function. It reads the
  3968. * flash ID and sets up MTD fields accordingly.
  3969. *
  3970. */
  3971. int nand_scan_ident(struct mtd_info *mtd, int maxchips,
  3972. struct nand_flash_dev *table)
  3973. {
  3974. int i, nand_maf_id, nand_dev_id;
  3975. struct nand_chip *chip = mtd_to_nand(mtd);
  3976. struct nand_flash_dev *type;
  3977. int ret;
  3978. if (chip->flash_node) {
  3979. ret = nand_dt_init(mtd, chip, chip->flash_node);
  3980. if (ret)
  3981. return ret;
  3982. }
  3983. /* Set the default functions */
  3984. nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
  3985. /* Read the flash type */
  3986. type = nand_get_flash_type(mtd, chip, &nand_maf_id,
  3987. &nand_dev_id, table);
  3988. if (IS_ERR(type)) {
  3989. if (!(chip->options & NAND_SCAN_SILENT_NODEV))
  3990. pr_warn("No NAND device found\n");
  3991. chip->select_chip(mtd, -1);
  3992. return PTR_ERR(type);
  3993. }
  3994. /* Initialize the ->data_interface field. */
  3995. ret = nand_init_data_interface(chip);
  3996. if (ret)
  3997. return ret;
  3998. /*
  3999. * Setup the data interface correctly on the chip and controller side.
  4000. * This explicit call to nand_setup_data_interface() is only required
  4001. * for the first die, because nand_reset() has been called before
  4002. * ->data_interface and ->default_onfi_timing_mode were set.
  4003. * For the other dies, nand_reset() will automatically switch to the
  4004. * best mode for us.
  4005. */
  4006. ret = nand_setup_data_interface(chip, 0);
  4007. if (ret)
  4008. return ret;
  4009. chip->select_chip(mtd, -1);
  4010. /* Check for a chip array */
  4011. for (i = 1; i < maxchips; i++) {
  4012. u8 id[2];
  4013. /* See comment in nand_get_flash_type for reset */
  4014. nand_reset(chip, i);
  4015. chip->select_chip(mtd, i);
  4016. /* Send the command for reading device ID */
  4017. nand_readid_op(chip, 0, id, sizeof(id));
  4018. /* Read manufacturer and device IDs */
  4019. if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
  4020. chip->select_chip(mtd, -1);
  4021. break;
  4022. }
  4023. chip->select_chip(mtd, -1);
  4024. }
  4025. #ifdef DEBUG
  4026. if (i > 1)
  4027. pr_info("%d chips detected\n", i);
  4028. #endif
  4029. /* Store the number of chips and calc total size for mtd */
  4030. chip->numchips = i;
  4031. mtd->size = i * chip->chipsize;
  4032. return 0;
  4033. }
  4034. EXPORT_SYMBOL(nand_scan_ident);
  4035. /**
  4036. * nand_check_ecc_caps - check the sanity of preset ECC settings
  4037. * @chip: nand chip info structure
  4038. * @caps: ECC caps info structure
  4039. * @oobavail: OOB size that the ECC engine can use
  4040. *
  4041. * When ECC step size and strength are already set, check if they are supported
  4042. * by the controller and the calculated ECC bytes fit within the chip's OOB.
  4043. * On success, the calculated ECC bytes is set.
  4044. */
  4045. int nand_check_ecc_caps(struct nand_chip *chip,
  4046. const struct nand_ecc_caps *caps, int oobavail)
  4047. {
  4048. struct mtd_info *mtd = nand_to_mtd(chip);
  4049. const struct nand_ecc_step_info *stepinfo;
  4050. int preset_step = chip->ecc.size;
  4051. int preset_strength = chip->ecc.strength;
  4052. int nsteps, ecc_bytes;
  4053. int i, j;
  4054. if (WARN_ON(oobavail < 0))
  4055. return -EINVAL;
  4056. if (!preset_step || !preset_strength)
  4057. return -ENODATA;
  4058. nsteps = mtd->writesize / preset_step;
  4059. for (i = 0; i < caps->nstepinfos; i++) {
  4060. stepinfo = &caps->stepinfos[i];
  4061. if (stepinfo->stepsize != preset_step)
  4062. continue;
  4063. for (j = 0; j < stepinfo->nstrengths; j++) {
  4064. if (stepinfo->strengths[j] != preset_strength)
  4065. continue;
  4066. ecc_bytes = caps->calc_ecc_bytes(preset_step,
  4067. preset_strength);
  4068. if (WARN_ON_ONCE(ecc_bytes < 0))
  4069. return ecc_bytes;
  4070. if (ecc_bytes * nsteps > oobavail) {
  4071. pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
  4072. preset_step, preset_strength);
  4073. return -ENOSPC;
  4074. }
  4075. chip->ecc.bytes = ecc_bytes;
  4076. return 0;
  4077. }
  4078. }
  4079. pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
  4080. preset_step, preset_strength);
  4081. return -ENOTSUPP;
  4082. }
  4083. EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
  4084. /**
  4085. * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
  4086. * @chip: nand chip info structure
  4087. * @caps: ECC engine caps info structure
  4088. * @oobavail: OOB size that the ECC engine can use
  4089. *
  4090. * If a chip's ECC requirement is provided, try to meet it with the least
  4091. * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
  4092. * On success, the chosen ECC settings are set.
  4093. */
  4094. int nand_match_ecc_req(struct nand_chip *chip,
  4095. const struct nand_ecc_caps *caps, int oobavail)
  4096. {
  4097. struct mtd_info *mtd = nand_to_mtd(chip);
  4098. const struct nand_ecc_step_info *stepinfo;
  4099. int req_step = chip->ecc_step_ds;
  4100. int req_strength = chip->ecc_strength_ds;
  4101. int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
  4102. int best_step, best_strength, best_ecc_bytes;
  4103. int best_ecc_bytes_total = INT_MAX;
  4104. int i, j;
  4105. if (WARN_ON(oobavail < 0))
  4106. return -EINVAL;
  4107. /* No information provided by the NAND chip */
  4108. if (!req_step || !req_strength)
  4109. return -ENOTSUPP;
  4110. /* number of correctable bits the chip requires in a page */
  4111. req_corr = mtd->writesize / req_step * req_strength;
  4112. for (i = 0; i < caps->nstepinfos; i++) {
  4113. stepinfo = &caps->stepinfos[i];
  4114. step_size = stepinfo->stepsize;
  4115. for (j = 0; j < stepinfo->nstrengths; j++) {
  4116. strength = stepinfo->strengths[j];
  4117. /*
  4118. * If both step size and strength are smaller than the
  4119. * chip's requirement, it is not easy to compare the
  4120. * resulted reliability.
  4121. */
  4122. if (step_size < req_step && strength < req_strength)
  4123. continue;
  4124. if (mtd->writesize % step_size)
  4125. continue;
  4126. nsteps = mtd->writesize / step_size;
  4127. ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
  4128. if (WARN_ON_ONCE(ecc_bytes < 0))
  4129. continue;
  4130. ecc_bytes_total = ecc_bytes * nsteps;
  4131. if (ecc_bytes_total > oobavail ||
  4132. strength * nsteps < req_corr)
  4133. continue;
  4134. /*
  4135. * We assume the best is to meet the chip's requrement
  4136. * with the least number of ECC bytes.
  4137. */
  4138. if (ecc_bytes_total < best_ecc_bytes_total) {
  4139. best_ecc_bytes_total = ecc_bytes_total;
  4140. best_step = step_size;
  4141. best_strength = strength;
  4142. best_ecc_bytes = ecc_bytes;
  4143. }
  4144. }
  4145. }
  4146. if (best_ecc_bytes_total == INT_MAX)
  4147. return -ENOTSUPP;
  4148. chip->ecc.size = best_step;
  4149. chip->ecc.strength = best_strength;
  4150. chip->ecc.bytes = best_ecc_bytes;
  4151. return 0;
  4152. }
  4153. EXPORT_SYMBOL_GPL(nand_match_ecc_req);
  4154. /**
  4155. * nand_maximize_ecc - choose the max ECC strength available
  4156. * @chip: nand chip info structure
  4157. * @caps: ECC engine caps info structure
  4158. * @oobavail: OOB size that the ECC engine can use
  4159. *
  4160. * Choose the max ECC strength that is supported on the controller, and can fit
  4161. * within the chip's OOB. On success, the chosen ECC settings are set.
  4162. */
  4163. int nand_maximize_ecc(struct nand_chip *chip,
  4164. const struct nand_ecc_caps *caps, int oobavail)
  4165. {
  4166. struct mtd_info *mtd = nand_to_mtd(chip);
  4167. const struct nand_ecc_step_info *stepinfo;
  4168. int step_size, strength, nsteps, ecc_bytes, corr;
  4169. int best_corr = 0;
  4170. int best_step = 0;
  4171. int best_strength, best_ecc_bytes;
  4172. int i, j;
  4173. if (WARN_ON(oobavail < 0))
  4174. return -EINVAL;
  4175. for (i = 0; i < caps->nstepinfos; i++) {
  4176. stepinfo = &caps->stepinfos[i];
  4177. step_size = stepinfo->stepsize;
  4178. /* If chip->ecc.size is already set, respect it */
  4179. if (chip->ecc.size && step_size != chip->ecc.size)
  4180. continue;
  4181. for (j = 0; j < stepinfo->nstrengths; j++) {
  4182. strength = stepinfo->strengths[j];
  4183. if (mtd->writesize % step_size)
  4184. continue;
  4185. nsteps = mtd->writesize / step_size;
  4186. ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
  4187. if (WARN_ON_ONCE(ecc_bytes < 0))
  4188. continue;
  4189. if (ecc_bytes * nsteps > oobavail)
  4190. continue;
  4191. corr = strength * nsteps;
  4192. /*
  4193. * If the number of correctable bits is the same,
  4194. * bigger step_size has more reliability.
  4195. */
  4196. if (corr > best_corr ||
  4197. (corr == best_corr && step_size > best_step)) {
  4198. best_corr = corr;
  4199. best_step = step_size;
  4200. best_strength = strength;
  4201. best_ecc_bytes = ecc_bytes;
  4202. }
  4203. }
  4204. }
  4205. if (!best_corr)
  4206. return -ENOTSUPP;
  4207. chip->ecc.size = best_step;
  4208. chip->ecc.strength = best_strength;
  4209. chip->ecc.bytes = best_ecc_bytes;
  4210. return 0;
  4211. }
  4212. EXPORT_SYMBOL_GPL(nand_maximize_ecc);
  4213. /*
  4214. * Check if the chip configuration meet the datasheet requirements.
  4215. * If our configuration corrects A bits per B bytes and the minimum
  4216. * required correction level is X bits per Y bytes, then we must ensure
  4217. * both of the following are true:
  4218. *
  4219. * (1) A / B >= X / Y
  4220. * (2) A >= X
  4221. *
  4222. * Requirement (1) ensures we can correct for the required bitflip density.
  4223. * Requirement (2) ensures we can correct even when all bitflips are clumped
  4224. * in the same sector.
  4225. */
  4226. static bool nand_ecc_strength_good(struct mtd_info *mtd)
  4227. {
  4228. struct nand_chip *chip = mtd_to_nand(mtd);
  4229. struct nand_ecc_ctrl *ecc = &chip->ecc;
  4230. int corr, ds_corr;
  4231. if (ecc->size == 0 || chip->ecc_step_ds == 0)
  4232. /* Not enough information */
  4233. return true;
  4234. /*
  4235. * We get the number of corrected bits per page to compare
  4236. * the correction density.
  4237. */
  4238. corr = (mtd->writesize * ecc->strength) / ecc->size;
  4239. ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
  4240. return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
  4241. }
  4242. static bool invalid_ecc_page_accessors(struct nand_chip *chip)
  4243. {
  4244. struct nand_ecc_ctrl *ecc = &chip->ecc;
  4245. if (nand_standard_page_accessors(ecc))
  4246. return false;
  4247. /*
  4248. * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
  4249. * controller driver implements all the page accessors because
  4250. * default helpers are not suitable when the core does not
  4251. * send the READ0/PAGEPROG commands.
  4252. */
  4253. return (!ecc->read_page || !ecc->write_page ||
  4254. !ecc->read_page_raw || !ecc->write_page_raw ||
  4255. (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
  4256. (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
  4257. ecc->hwctl && ecc->calculate));
  4258. }
  4259. /**
  4260. * nand_scan_tail - [NAND Interface] Scan for the NAND device
  4261. * @mtd: MTD device structure
  4262. *
  4263. * This is the second phase of the normal nand_scan() function. It fills out
  4264. * all the uninitialized function pointers with the defaults and scans for a
  4265. * bad block table if appropriate.
  4266. */
  4267. int nand_scan_tail(struct mtd_info *mtd)
  4268. {
  4269. int i;
  4270. struct nand_chip *chip = mtd_to_nand(mtd);
  4271. struct nand_ecc_ctrl *ecc = &chip->ecc;
  4272. struct nand_buffers *nbuf;
  4273. /* New bad blocks should be marked in OOB, flash-based BBT, or both */
  4274. BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
  4275. !(chip->bbt_options & NAND_BBT_USE_FLASH));
  4276. if (invalid_ecc_page_accessors(chip)) {
  4277. pr_err("Invalid ECC page accessors setup\n");
  4278. return -EINVAL;
  4279. }
  4280. if (!(chip->options & NAND_OWN_BUFFERS)) {
  4281. nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
  4282. chip->buffers = nbuf;
  4283. } else {
  4284. if (!chip->buffers)
  4285. return -ENOMEM;
  4286. }
  4287. /* Set the internal oob buffer location, just after the page data */
  4288. chip->oob_poi = chip->buffers->databuf + mtd->writesize;
  4289. /*
  4290. * If no default placement scheme is given, select an appropriate one.
  4291. */
  4292. if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
  4293. switch (mtd->oobsize) {
  4294. #ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
  4295. case 8:
  4296. ecc->layout = &nand_oob_8;
  4297. break;
  4298. case 16:
  4299. ecc->layout = &nand_oob_16;
  4300. break;
  4301. case 64:
  4302. ecc->layout = &nand_oob_64;
  4303. break;
  4304. case 128:
  4305. ecc->layout = &nand_oob_128;
  4306. break;
  4307. #endif
  4308. default:
  4309. pr_warn("No oob scheme defined for oobsize %d\n",
  4310. mtd->oobsize);
  4311. BUG();
  4312. }
  4313. }
  4314. if (!chip->write_page)
  4315. chip->write_page = nand_write_page;
  4316. /*
  4317. * Check ECC mode, default to software if 3byte/512byte hardware ECC is
  4318. * selected and we have 256 byte pagesize fallback to software ECC
  4319. */
  4320. switch (ecc->mode) {
  4321. case NAND_ECC_HW_OOB_FIRST:
  4322. /* Similar to NAND_ECC_HW, but a separate read_page handle */
  4323. if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
  4324. pr_warn("No ECC functions supplied; hardware ECC not possible\n");
  4325. BUG();
  4326. }
  4327. if (!ecc->read_page)
  4328. ecc->read_page = nand_read_page_hwecc_oob_first;
  4329. case NAND_ECC_HW:
  4330. /* Use standard hwecc read page function? */
  4331. if (!ecc->read_page)
  4332. ecc->read_page = nand_read_page_hwecc;
  4333. if (!ecc->write_page)
  4334. ecc->write_page = nand_write_page_hwecc;
  4335. if (!ecc->read_page_raw)
  4336. ecc->read_page_raw = nand_read_page_raw;
  4337. if (!ecc->write_page_raw)
  4338. ecc->write_page_raw = nand_write_page_raw;
  4339. if (!ecc->read_oob)
  4340. ecc->read_oob = nand_read_oob_std;
  4341. if (!ecc->write_oob)
  4342. ecc->write_oob = nand_write_oob_std;
  4343. if (!ecc->read_subpage)
  4344. ecc->read_subpage = nand_read_subpage;
  4345. if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
  4346. ecc->write_subpage = nand_write_subpage_hwecc;
  4347. case NAND_ECC_HW_SYNDROME:
  4348. if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
  4349. (!ecc->read_page ||
  4350. ecc->read_page == nand_read_page_hwecc ||
  4351. !ecc->write_page ||
  4352. ecc->write_page == nand_write_page_hwecc)) {
  4353. pr_warn("No ECC functions supplied; hardware ECC not possible\n");
  4354. BUG();
  4355. }
  4356. /* Use standard syndrome read/write page function? */
  4357. if (!ecc->read_page)
  4358. ecc->read_page = nand_read_page_syndrome;
  4359. if (!ecc->write_page)
  4360. ecc->write_page = nand_write_page_syndrome;
  4361. if (!ecc->read_page_raw)
  4362. ecc->read_page_raw = nand_read_page_raw_syndrome;
  4363. if (!ecc->write_page_raw)
  4364. ecc->write_page_raw = nand_write_page_raw_syndrome;
  4365. if (!ecc->read_oob)
  4366. ecc->read_oob = nand_read_oob_syndrome;
  4367. if (!ecc->write_oob)
  4368. ecc->write_oob = nand_write_oob_syndrome;
  4369. if (mtd->writesize >= ecc->size) {
  4370. if (!ecc->strength) {
  4371. pr_warn("Driver must set ecc.strength when using hardware ECC\n");
  4372. BUG();
  4373. }
  4374. break;
  4375. }
  4376. pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
  4377. ecc->size, mtd->writesize);
  4378. ecc->mode = NAND_ECC_SOFT;
  4379. case NAND_ECC_SOFT:
  4380. ecc->calculate = nand_calculate_ecc;
  4381. ecc->correct = nand_correct_data;
  4382. ecc->read_page = nand_read_page_swecc;
  4383. ecc->read_subpage = nand_read_subpage;
  4384. ecc->write_page = nand_write_page_swecc;
  4385. ecc->read_page_raw = nand_read_page_raw;
  4386. ecc->write_page_raw = nand_write_page_raw;
  4387. ecc->read_oob = nand_read_oob_std;
  4388. ecc->write_oob = nand_write_oob_std;
  4389. if (!ecc->size)
  4390. ecc->size = 256;
  4391. ecc->bytes = 3;
  4392. ecc->strength = 1;
  4393. break;
  4394. case NAND_ECC_SOFT_BCH:
  4395. if (!mtd_nand_has_bch()) {
  4396. pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
  4397. BUG();
  4398. }
  4399. ecc->calculate = nand_bch_calculate_ecc;
  4400. ecc->correct = nand_bch_correct_data;
  4401. ecc->read_page = nand_read_page_swecc;
  4402. ecc->read_subpage = nand_read_subpage;
  4403. ecc->write_page = nand_write_page_swecc;
  4404. ecc->read_page_raw = nand_read_page_raw;
  4405. ecc->write_page_raw = nand_write_page_raw;
  4406. ecc->read_oob = nand_read_oob_std;
  4407. ecc->write_oob = nand_write_oob_std;
  4408. /*
  4409. * Board driver should supply ecc.size and ecc.strength values
  4410. * to select how many bits are correctable. Otherwise, default
  4411. * to 4 bits for large page devices.
  4412. */
  4413. if (!ecc->size && (mtd->oobsize >= 64)) {
  4414. ecc->size = 512;
  4415. ecc->strength = 4;
  4416. }
  4417. /* See nand_bch_init() for details. */
  4418. ecc->bytes = 0;
  4419. ecc->priv = nand_bch_init(mtd);
  4420. if (!ecc->priv) {
  4421. pr_warn("BCH ECC initialization failed!\n");
  4422. BUG();
  4423. }
  4424. break;
  4425. case NAND_ECC_NONE:
  4426. pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
  4427. ecc->read_page = nand_read_page_raw;
  4428. ecc->write_page = nand_write_page_raw;
  4429. ecc->read_oob = nand_read_oob_std;
  4430. ecc->read_page_raw = nand_read_page_raw;
  4431. ecc->write_page_raw = nand_write_page_raw;
  4432. ecc->write_oob = nand_write_oob_std;
  4433. ecc->size = mtd->writesize;
  4434. ecc->bytes = 0;
  4435. ecc->strength = 0;
  4436. break;
  4437. default:
  4438. pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
  4439. BUG();
  4440. }
  4441. /* For many systems, the standard OOB write also works for raw */
  4442. if (!ecc->read_oob_raw)
  4443. ecc->read_oob_raw = ecc->read_oob;
  4444. if (!ecc->write_oob_raw)
  4445. ecc->write_oob_raw = ecc->write_oob;
  4446. /*
  4447. * The number of bytes available for a client to place data into
  4448. * the out of band area.
  4449. */
  4450. mtd->oobavail = 0;
  4451. if (ecc->layout) {
  4452. for (i = 0; ecc->layout->oobfree[i].length; i++)
  4453. mtd->oobavail += ecc->layout->oobfree[i].length;
  4454. }
  4455. /* ECC sanity check: warn if it's too weak */
  4456. if (!nand_ecc_strength_good(mtd))
  4457. pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
  4458. mtd->name);
  4459. /*
  4460. * Set the number of read / write steps for one page depending on ECC
  4461. * mode.
  4462. */
  4463. ecc->steps = mtd->writesize / ecc->size;
  4464. if (ecc->steps * ecc->size != mtd->writesize) {
  4465. pr_warn("Invalid ECC parameters\n");
  4466. BUG();
  4467. }
  4468. ecc->total = ecc->steps * ecc->bytes;
  4469. /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
  4470. if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
  4471. switch (ecc->steps) {
  4472. case 2:
  4473. mtd->subpage_sft = 1;
  4474. break;
  4475. case 4:
  4476. case 8:
  4477. case 16:
  4478. mtd->subpage_sft = 2;
  4479. break;
  4480. }
  4481. }
  4482. chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
  4483. /* Initialize state */
  4484. chip->state = FL_READY;
  4485. /* Invalidate the pagebuffer reference */
  4486. chip->pagebuf = -1;
  4487. /* Large page NAND with SOFT_ECC should support subpage reads */
  4488. switch (ecc->mode) {
  4489. case NAND_ECC_SOFT:
  4490. case NAND_ECC_SOFT_BCH:
  4491. if (chip->page_shift > 9)
  4492. chip->options |= NAND_SUBPAGE_READ;
  4493. break;
  4494. default:
  4495. break;
  4496. }
  4497. /* Fill in remaining MTD driver data */
  4498. mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
  4499. mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
  4500. MTD_CAP_NANDFLASH;
  4501. mtd->_erase = nand_erase;
  4502. mtd->_panic_write = panic_nand_write;
  4503. mtd->_read_oob = nand_read_oob;
  4504. mtd->_write_oob = nand_write_oob;
  4505. mtd->_sync = nand_sync;
  4506. mtd->_lock = NULL;
  4507. mtd->_unlock = NULL;
  4508. mtd->_block_isreserved = nand_block_isreserved;
  4509. mtd->_block_isbad = nand_block_isbad;
  4510. mtd->_block_markbad = nand_block_markbad;
  4511. mtd->writebufsize = mtd->writesize;
  4512. /* propagate ecc info to mtd_info */
  4513. mtd->ecclayout = ecc->layout;
  4514. mtd->ecc_strength = ecc->strength;
  4515. mtd->ecc_step_size = ecc->size;
  4516. /*
  4517. * Initialize bitflip_threshold to its default prior scan_bbt() call.
  4518. * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
  4519. * properly set.
  4520. */
  4521. if (!mtd->bitflip_threshold)
  4522. mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
  4523. return 0;
  4524. }
  4525. EXPORT_SYMBOL(nand_scan_tail);
  4526. /**
  4527. * nand_scan - [NAND Interface] Scan for the NAND device
  4528. * @mtd: MTD device structure
  4529. * @maxchips: number of chips to scan for
  4530. *
  4531. * This fills out all the uninitialized function pointers with the defaults.
  4532. * The flash ID is read and the mtd/chip structures are filled with the
  4533. * appropriate values.
  4534. */
  4535. int nand_scan(struct mtd_info *mtd, int maxchips)
  4536. {
  4537. int ret;
  4538. ret = nand_scan_ident(mtd, maxchips, NULL);
  4539. if (!ret)
  4540. ret = nand_scan_tail(mtd);
  4541. return ret;
  4542. }
  4543. EXPORT_SYMBOL(nand_scan);
  4544. MODULE_LICENSE("GPL");
  4545. MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
  4546. MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
  4547. MODULE_DESCRIPTION("Generic NAND flash driver code");