bcm2835_sdhost.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * bcm2835 sdhost driver.
  4. *
  5. * The 2835 has two SD controllers: The Arasan sdhci controller
  6. * (supported by the iproc driver) and a custom sdhost controller
  7. * (supported by this driver).
  8. *
  9. * The sdhci controller supports both sdcard and sdio. The sdhost
  10. * controller supports the sdcard only, but has better performance.
  11. * Also note that the rpi3 has sdio wifi, so driving the sdcard with
  12. * the sdhost controller allows to use the sdhci controller for wifi
  13. * support.
  14. *
  15. * The configuration is done by devicetree via pin muxing. Both
  16. * SD controller are available on the same pins (2 pin groups = pin 22
  17. * to 27 + pin 48 to 53). So it's possible to use both SD controllers
  18. * at the same time with different pin groups.
  19. *
  20. * This code was ported to U-Boot by
  21. * Alexander Graf <agraf@suse.de>
  22. * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by
  23. * Phil Elwell <phil@raspberrypi.org>
  24. * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
  25. * which is based on
  26. * mmc-bcm2835.c by Gellert Weisz
  27. * which is, in turn, based on
  28. * sdhci-bcm2708.c by Broadcom
  29. * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
  30. * sdhci.c and sdhci-pci.c by Pierre Ossman
  31. */
  32. #include <clk.h>
  33. #include <common.h>
  34. #include <dm.h>
  35. #include <mmc.h>
  36. #include <asm/arch/msg.h>
  37. #include <asm/arch/mbox.h>
  38. #include <asm/unaligned.h>
  39. #include <dm/device_compat.h>
  40. #include <linux/bug.h>
  41. #include <linux/compat.h>
  42. #include <linux/io.h>
  43. #include <linux/iopoll.h>
  44. #include <linux/sizes.h>
  45. #include <mach/gpio.h>
  46. #include <power/regulator.h>
  47. #define msleep(a) udelay(a * 1000)
  48. #define SDCMD 0x00 /* Command to SD card - 16 R/W */
  49. #define SDARG 0x04 /* Argument to SD card - 32 R/W */
  50. #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
  51. #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
  52. #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
  53. #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
  54. #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
  55. #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
  56. #define SDHSTS 0x20 /* SD host status - 11 R/W */
  57. #define SDVDD 0x30 /* SD card power control - 1 R/W */
  58. #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
  59. #define SDHCFG 0x38 /* Host configuration - 2 R/W */
  60. #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
  61. #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
  62. #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
  63. #define SDCMD_NEW_FLAG 0x8000
  64. #define SDCMD_FAIL_FLAG 0x4000
  65. #define SDCMD_BUSYWAIT 0x800
  66. #define SDCMD_NO_RESPONSE 0x400
  67. #define SDCMD_LONG_RESPONSE 0x200
  68. #define SDCMD_WRITE_CMD 0x80
  69. #define SDCMD_READ_CMD 0x40
  70. #define SDCMD_CMD_MASK 0x3f
  71. #define SDCDIV_MAX_CDIV 0x7ff
  72. #define SDHSTS_BUSY_IRPT 0x400
  73. #define SDHSTS_BLOCK_IRPT 0x200
  74. #define SDHSTS_SDIO_IRPT 0x100
  75. #define SDHSTS_REW_TIME_OUT 0x80
  76. #define SDHSTS_CMD_TIME_OUT 0x40
  77. #define SDHSTS_CRC16_ERROR 0x20
  78. #define SDHSTS_CRC7_ERROR 0x10
  79. #define SDHSTS_FIFO_ERROR 0x08
  80. #define SDHSTS_DATA_FLAG 0x01
  81. #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \
  82. SDHSTS_BLOCK_IRPT | \
  83. SDHSTS_SDIO_IRPT | \
  84. SDHSTS_REW_TIME_OUT | \
  85. SDHSTS_CMD_TIME_OUT | \
  86. SDHSTS_CRC16_ERROR | \
  87. SDHSTS_CRC7_ERROR | \
  88. SDHSTS_FIFO_ERROR)
  89. #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
  90. SDHSTS_CRC16_ERROR | \
  91. SDHSTS_REW_TIME_OUT | \
  92. SDHSTS_FIFO_ERROR)
  93. #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
  94. SDHSTS_TRANSFER_ERROR_MASK)
  95. #define SDHCFG_BUSY_IRPT_EN BIT(10)
  96. #define SDHCFG_BLOCK_IRPT_EN BIT(8)
  97. #define SDHCFG_SDIO_IRPT_EN BIT(5)
  98. #define SDHCFG_DATA_IRPT_EN BIT(4)
  99. #define SDHCFG_SLOW_CARD BIT(3)
  100. #define SDHCFG_WIDE_EXT_BUS BIT(2)
  101. #define SDHCFG_WIDE_INT_BUS BIT(1)
  102. #define SDHCFG_REL_CMD_LINE BIT(0)
  103. #define SDVDD_POWER_OFF 0
  104. #define SDVDD_POWER_ON 1
  105. #define SDEDM_FORCE_DATA_MODE BIT(19)
  106. #define SDEDM_CLOCK_PULSE BIT(20)
  107. #define SDEDM_BYPASS BIT(21)
  108. #define SDEDM_FIFO_FILL_SHIFT 4
  109. #define SDEDM_FIFO_FILL_MASK 0x1f
  110. static u32 edm_fifo_fill(u32 edm)
  111. {
  112. return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK;
  113. }
  114. #define SDEDM_WRITE_THRESHOLD_SHIFT 9
  115. #define SDEDM_READ_THRESHOLD_SHIFT 14
  116. #define SDEDM_THRESHOLD_MASK 0x1f
  117. #define SDEDM_FSM_MASK 0xf
  118. #define SDEDM_FSM_IDENTMODE 0x0
  119. #define SDEDM_FSM_DATAMODE 0x1
  120. #define SDEDM_FSM_READDATA 0x2
  121. #define SDEDM_FSM_WRITEDATA 0x3
  122. #define SDEDM_FSM_READWAIT 0x4
  123. #define SDEDM_FSM_READCRC 0x5
  124. #define SDEDM_FSM_WRITECRC 0x6
  125. #define SDEDM_FSM_WRITEWAIT1 0x7
  126. #define SDEDM_FSM_POWERDOWN 0x8
  127. #define SDEDM_FSM_POWERUP 0x9
  128. #define SDEDM_FSM_WRITESTART1 0xa
  129. #define SDEDM_FSM_WRITESTART2 0xb
  130. #define SDEDM_FSM_GENPULSES 0xc
  131. #define SDEDM_FSM_WRITEWAIT2 0xd
  132. #define SDEDM_FSM_STARTPOWDOWN 0xf
  133. #define SDDATA_FIFO_WORDS 16
  134. #define FIFO_READ_THRESHOLD 4
  135. #define FIFO_WRITE_THRESHOLD 4
  136. #define SDDATA_FIFO_PIO_BURST 8
  137. #define SDHST_TIMEOUT_MAX_USEC 100000
  138. struct bcm2835_plat {
  139. struct mmc_config cfg;
  140. struct mmc mmc;
  141. };
  142. struct bcm2835_host {
  143. void __iomem *ioaddr;
  144. u32 phys_addr;
  145. int clock; /* Current clock speed */
  146. unsigned int max_clk; /* Max possible freq */
  147. unsigned int blocks; /* remaining PIO blocks */
  148. u32 ns_per_fifo_word;
  149. /* cached registers */
  150. u32 hcfg;
  151. u32 cdiv;
  152. struct mmc_cmd *cmd; /* Current command */
  153. struct mmc_data *data; /* Current data request */
  154. bool use_busy:1; /* Wait for busy interrupt */
  155. struct udevice *dev;
  156. struct mmc *mmc;
  157. struct bcm2835_plat *plat;
  158. };
  159. static void bcm2835_dumpregs(struct bcm2835_host *host)
  160. {
  161. dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
  162. dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
  163. dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
  164. dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
  165. dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
  166. dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
  167. dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
  168. dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
  169. dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
  170. dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
  171. dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
  172. dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
  173. dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
  174. dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
  175. dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
  176. dev_dbg(dev, "===========================================\n");
  177. }
  178. static void bcm2835_reset_internal(struct bcm2835_host *host)
  179. {
  180. u32 temp;
  181. writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
  182. writel(0, host->ioaddr + SDCMD);
  183. writel(0, host->ioaddr + SDARG);
  184. /* Set timeout to a big enough value so we don't hit it */
  185. writel(0xf00000, host->ioaddr + SDTOUT);
  186. writel(0, host->ioaddr + SDCDIV);
  187. /* Clear status register */
  188. writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS);
  189. writel(0, host->ioaddr + SDHCFG);
  190. writel(0, host->ioaddr + SDHBCT);
  191. writel(0, host->ioaddr + SDHBLC);
  192. /* Limit fifo usage due to silicon bug */
  193. temp = readl(host->ioaddr + SDEDM);
  194. temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
  195. (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
  196. temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
  197. (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
  198. writel(temp, host->ioaddr + SDEDM);
  199. /* Wait for FIFO threshold to populate */
  200. msleep(20);
  201. writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
  202. /* Wait for all components to go through power on cycle */
  203. msleep(20);
  204. host->clock = 0;
  205. writel(host->hcfg, host->ioaddr + SDHCFG);
  206. writel(host->cdiv, host->ioaddr + SDCDIV);
  207. }
  208. static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
  209. {
  210. ulong tstart_ms = get_timer(0);
  211. while (1) {
  212. u32 edm, fsm;
  213. edm = readl(host->ioaddr + SDEDM);
  214. fsm = edm & SDEDM_FSM_MASK;
  215. if ((fsm == SDEDM_FSM_IDENTMODE) ||
  216. (fsm == SDEDM_FSM_DATAMODE))
  217. break;
  218. if ((fsm == SDEDM_FSM_READWAIT) ||
  219. (fsm == SDEDM_FSM_WRITESTART1) ||
  220. (fsm == SDEDM_FSM_READDATA)) {
  221. writel(edm | SDEDM_FORCE_DATA_MODE,
  222. host->ioaddr + SDEDM);
  223. break;
  224. }
  225. /* Error out after ~1s */
  226. ulong tlapse_ms = get_timer(tstart_ms);
  227. if ( tlapse_ms > 1000 /* ms */ ) {
  228. dev_err(host->dev,
  229. "wait_transfer_complete - still waiting after %lu ms\n",
  230. tlapse_ms);
  231. bcm2835_dumpregs(host);
  232. return -ETIMEDOUT;
  233. }
  234. }
  235. return 0;
  236. }
  237. static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
  238. {
  239. struct mmc_data *data = host->data;
  240. size_t blksize = data->blocksize;
  241. int copy_words;
  242. u32 hsts = 0;
  243. u32 *buf;
  244. if (blksize % sizeof(u32))
  245. return -EINVAL;
  246. buf = is_read ? (u32 *)data->dest : (u32 *)data->src;
  247. if (is_read)
  248. data->dest += blksize;
  249. else
  250. data->src += blksize;
  251. copy_words = blksize / sizeof(u32);
  252. /*
  253. * Copy all contents from/to the FIFO as far as it reaches,
  254. * then wait for it to fill/empty again and rewind.
  255. */
  256. while (copy_words) {
  257. int burst_words, words;
  258. u32 edm;
  259. burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
  260. edm = readl(host->ioaddr + SDEDM);
  261. if (is_read)
  262. words = edm_fifo_fill(edm);
  263. else
  264. words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm);
  265. if (words < burst_words) {
  266. int fsm_state = (edm & SDEDM_FSM_MASK);
  267. if ((is_read &&
  268. (fsm_state != SDEDM_FSM_READDATA &&
  269. fsm_state != SDEDM_FSM_READWAIT &&
  270. fsm_state != SDEDM_FSM_READCRC)) ||
  271. (!is_read &&
  272. (fsm_state != SDEDM_FSM_WRITEDATA &&
  273. fsm_state != SDEDM_FSM_WRITEWAIT1 &&
  274. fsm_state != SDEDM_FSM_WRITEWAIT2 &&
  275. fsm_state != SDEDM_FSM_WRITECRC &&
  276. fsm_state != SDEDM_FSM_WRITESTART1 &&
  277. fsm_state != SDEDM_FSM_WRITESTART2))) {
  278. hsts = readl(host->ioaddr + SDHSTS);
  279. printf("fsm %x, hsts %08x\n", fsm_state, hsts);
  280. if (hsts & SDHSTS_ERROR_MASK)
  281. break;
  282. }
  283. continue;
  284. } else if (words > copy_words) {
  285. words = copy_words;
  286. }
  287. copy_words -= words;
  288. /* Copy current chunk to/from the FIFO */
  289. while (words) {
  290. if (is_read)
  291. *(buf++) = readl(host->ioaddr + SDDATA);
  292. else
  293. writel(*(buf++), host->ioaddr + SDDATA);
  294. words--;
  295. }
  296. }
  297. return 0;
  298. }
  299. static int bcm2835_transfer_pio(struct bcm2835_host *host)
  300. {
  301. u32 sdhsts;
  302. bool is_read;
  303. int ret = 0;
  304. is_read = (host->data->flags & MMC_DATA_READ) != 0;
  305. ret = bcm2835_transfer_block_pio(host, is_read);
  306. if (ret)
  307. return ret;
  308. sdhsts = readl(host->ioaddr + SDHSTS);
  309. if (sdhsts & (SDHSTS_CRC16_ERROR |
  310. SDHSTS_CRC7_ERROR |
  311. SDHSTS_FIFO_ERROR)) {
  312. printf("%s transfer error - HSTS %08x\n",
  313. is_read ? "read" : "write", sdhsts);
  314. ret = -EILSEQ;
  315. } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
  316. SDHSTS_REW_TIME_OUT))) {
  317. printf("%s timeout error - HSTS %08x\n",
  318. is_read ? "read" : "write", sdhsts);
  319. ret = -ETIMEDOUT;
  320. }
  321. return ret;
  322. }
  323. static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
  324. struct mmc_data *data)
  325. {
  326. WARN_ON(host->data);
  327. host->data = data;
  328. if (!data)
  329. return;
  330. /* Use PIO */
  331. host->blocks = data->blocks;
  332. writel(data->blocksize, host->ioaddr + SDHBCT);
  333. writel(data->blocks, host->ioaddr + SDHBLC);
  334. }
  335. static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host)
  336. {
  337. u32 value;
  338. int ret;
  339. int timeout_us = SDHST_TIMEOUT_MAX_USEC;
  340. ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
  341. !(value & SDCMD_NEW_FLAG), timeout_us);
  342. if (ret == -ETIMEDOUT)
  343. printf("%s: timeout (%d us)\n", __func__, timeout_us);
  344. return value;
  345. }
  346. static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd,
  347. struct mmc_data *data)
  348. {
  349. u32 sdcmd, sdhsts;
  350. WARN_ON(host->cmd);
  351. if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) {
  352. printf("unsupported response type!\n");
  353. return -EINVAL;
  354. }
  355. sdcmd = bcm2835_read_wait_sdcmd(host);
  356. if (sdcmd & SDCMD_NEW_FLAG) {
  357. printf("previous command never completed.\n");
  358. bcm2835_dumpregs(host);
  359. return -EBUSY;
  360. }
  361. host->cmd = cmd;
  362. /* Clear any error flags */
  363. sdhsts = readl(host->ioaddr + SDHSTS);
  364. if (sdhsts & SDHSTS_ERROR_MASK)
  365. writel(sdhsts, host->ioaddr + SDHSTS);
  366. bcm2835_prepare_data(host, cmd, data);
  367. writel(cmd->cmdarg, host->ioaddr + SDARG);
  368. sdcmd = cmd->cmdidx & SDCMD_CMD_MASK;
  369. host->use_busy = false;
  370. if (!(cmd->resp_type & MMC_RSP_PRESENT)) {
  371. sdcmd |= SDCMD_NO_RESPONSE;
  372. } else {
  373. if (cmd->resp_type & MMC_RSP_136)
  374. sdcmd |= SDCMD_LONG_RESPONSE;
  375. if (cmd->resp_type & MMC_RSP_BUSY) {
  376. sdcmd |= SDCMD_BUSYWAIT;
  377. host->use_busy = true;
  378. }
  379. }
  380. if (data) {
  381. if (data->flags & MMC_DATA_WRITE)
  382. sdcmd |= SDCMD_WRITE_CMD;
  383. if (data->flags & MMC_DATA_READ)
  384. sdcmd |= SDCMD_READ_CMD;
  385. }
  386. writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
  387. return 0;
  388. }
  389. static int bcm2835_finish_command(struct bcm2835_host *host)
  390. {
  391. struct mmc_cmd *cmd = host->cmd;
  392. u32 sdcmd;
  393. int ret = 0;
  394. sdcmd = bcm2835_read_wait_sdcmd(host);
  395. /* Check for errors */
  396. if (sdcmd & SDCMD_NEW_FLAG) {
  397. printf("command never completed.\n");
  398. bcm2835_dumpregs(host);
  399. return -EIO;
  400. } else if (sdcmd & SDCMD_FAIL_FLAG) {
  401. u32 sdhsts = readl(host->ioaddr + SDHSTS);
  402. /* Clear the errors */
  403. writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
  404. if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
  405. (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
  406. if (sdhsts & SDHSTS_CMD_TIME_OUT) {
  407. ret = -ETIMEDOUT;
  408. } else {
  409. printf("unexpected command %d error\n",
  410. host->cmd->cmdidx);
  411. bcm2835_dumpregs(host);
  412. ret = -EILSEQ;
  413. }
  414. return ret;
  415. }
  416. }
  417. if (cmd->resp_type & MMC_RSP_PRESENT) {
  418. if (cmd->resp_type & MMC_RSP_136) {
  419. int i;
  420. for (i = 0; i < 4; i++) {
  421. cmd->response[3 - i] =
  422. readl(host->ioaddr + SDRSP0 + i * 4);
  423. }
  424. } else {
  425. cmd->response[0] = readl(host->ioaddr + SDRSP0);
  426. }
  427. }
  428. /* Processed actual command. */
  429. host->cmd = NULL;
  430. return ret;
  431. }
  432. static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
  433. {
  434. int ret = -EINVAL;
  435. if (!(intmask & SDHSTS_ERROR_MASK))
  436. return 0;
  437. if (!host->cmd)
  438. return -EINVAL;
  439. printf("sdhost_busy_irq: intmask %08x\n", intmask);
  440. if (intmask & SDHSTS_CRC7_ERROR) {
  441. ret = -EILSEQ;
  442. } else if (intmask & (SDHSTS_CRC16_ERROR |
  443. SDHSTS_FIFO_ERROR)) {
  444. ret = -EILSEQ;
  445. } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) {
  446. ret = -ETIMEDOUT;
  447. }
  448. bcm2835_dumpregs(host);
  449. return ret;
  450. }
  451. static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
  452. {
  453. int ret = 0;
  454. if (!host->data)
  455. return 0;
  456. if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
  457. ret = -EILSEQ;
  458. if (intmask & SDHSTS_REW_TIME_OUT)
  459. ret = -ETIMEDOUT;
  460. if (ret)
  461. printf("%s:%d %d\n", __func__, __LINE__, ret);
  462. return ret;
  463. }
  464. static int bcm2835_transmit(struct bcm2835_host *host)
  465. {
  466. u32 intmask = readl(host->ioaddr + SDHSTS);
  467. int ret;
  468. /* Check for errors */
  469. ret = bcm2835_check_data_error(host, intmask);
  470. if (ret)
  471. return ret;
  472. ret = bcm2835_check_cmd_error(host, intmask);
  473. if (ret)
  474. return ret;
  475. /* Handle wait for busy end */
  476. if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) {
  477. writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS);
  478. host->use_busy = false;
  479. bcm2835_finish_command(host);
  480. }
  481. /* Handle PIO data transfer */
  482. if (host->data) {
  483. ret = bcm2835_transfer_pio(host);
  484. if (ret)
  485. return ret;
  486. host->blocks--;
  487. if (host->blocks == 0) {
  488. /* Wait for command to complete for real */
  489. ret = bcm2835_wait_transfer_complete(host);
  490. if (ret)
  491. return ret;
  492. /* Transfer complete */
  493. host->data = NULL;
  494. }
  495. }
  496. return 0;
  497. }
  498. static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
  499. {
  500. int div;
  501. /* The SDCDIV register has 11 bits, and holds (div - 2). But
  502. * in data mode the max is 50MHz wihout a minimum, and only
  503. * the bottom 3 bits are used. Since the switch over is
  504. * automatic (unless we have marked the card as slow...),
  505. * chosen values have to make sense in both modes. Ident mode
  506. * must be 100-400KHz, so can range check the requested
  507. * clock. CMD15 must be used to return to data mode, so this
  508. * can be monitored.
  509. *
  510. * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
  511. * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
  512. *
  513. * 623->400KHz/27.8MHz
  514. * reset value (507)->491159/50MHz
  515. *
  516. * BUT, the 3-bit clock divisor in data mode is too small if
  517. * the core clock is higher than 250MHz, so instead use the
  518. * SLOW_CARD configuration bit to force the use of the ident
  519. * clock divisor at all times.
  520. */
  521. if (clock < 100000) {
  522. /* Can't stop the clock, but make it as slow as possible
  523. * to show willing
  524. */
  525. host->cdiv = SDCDIV_MAX_CDIV;
  526. writel(host->cdiv, host->ioaddr + SDCDIV);
  527. return;
  528. }
  529. div = host->max_clk / clock;
  530. if (div < 2)
  531. div = 2;
  532. if ((host->max_clk / div) > clock)
  533. div++;
  534. div -= 2;
  535. if (div > SDCDIV_MAX_CDIV)
  536. div = SDCDIV_MAX_CDIV;
  537. clock = host->max_clk / (div + 2);
  538. host->mmc->clock = clock;
  539. /* Calibrate some delays */
  540. host->ns_per_fifo_word = (1000000000 / clock) *
  541. ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
  542. host->cdiv = div;
  543. writel(host->cdiv, host->ioaddr + SDCDIV);
  544. /* Set the timeout to 500ms */
  545. writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
  546. }
  547. static inline int is_power_of_2(u64 x)
  548. {
  549. return !(x & (x - 1));
  550. }
  551. static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  552. struct mmc_data *data)
  553. {
  554. struct bcm2835_host *host = dev_get_priv(dev);
  555. u32 edm, fsm;
  556. int ret = 0;
  557. if (data && !is_power_of_2(data->blocksize)) {
  558. printf("unsupported block size (%d bytes)\n", data->blocksize);
  559. if (cmd)
  560. return -EINVAL;
  561. }
  562. edm = readl(host->ioaddr + SDEDM);
  563. fsm = edm & SDEDM_FSM_MASK;
  564. if ((fsm != SDEDM_FSM_IDENTMODE) &&
  565. (fsm != SDEDM_FSM_DATAMODE) &&
  566. (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
  567. printf("previous command (%d) not complete (EDM %08x)\n",
  568. readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm);
  569. bcm2835_dumpregs(host);
  570. if (cmd)
  571. return -EILSEQ;
  572. return 0;
  573. }
  574. if (cmd) {
  575. ret = bcm2835_send_command(host, cmd, data);
  576. if (!ret && !host->use_busy)
  577. ret = bcm2835_finish_command(host);
  578. }
  579. /* Wait for completion of busy signal or data transfer */
  580. while (host->use_busy || host->data) {
  581. ret = bcm2835_transmit(host);
  582. if (ret)
  583. break;
  584. }
  585. return ret;
  586. }
  587. static int bcm2835_set_ios(struct udevice *dev)
  588. {
  589. struct bcm2835_host *host = dev_get_priv(dev);
  590. struct mmc *mmc = mmc_get_mmc_dev(dev);
  591. if (!mmc->clock || mmc->clock != host->clock) {
  592. bcm2835_set_clock(host, mmc->clock);
  593. host->clock = mmc->clock;
  594. }
  595. /* set bus width */
  596. host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
  597. if (mmc->bus_width == 4)
  598. host->hcfg |= SDHCFG_WIDE_EXT_BUS;
  599. host->hcfg |= SDHCFG_WIDE_INT_BUS;
  600. /* Disable clever clock switching, to cope with fast core clocks */
  601. host->hcfg |= SDHCFG_SLOW_CARD;
  602. writel(host->hcfg, host->ioaddr + SDHCFG);
  603. return 0;
  604. }
  605. static void bcm2835_add_host(struct bcm2835_host *host)
  606. {
  607. struct mmc_config *cfg = &host->plat->cfg;
  608. cfg->f_max = host->max_clk;
  609. cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
  610. cfg->b_max = 65535;
  611. dev_dbg(dev, "f_max %d, f_min %d\n",
  612. cfg->f_max, cfg->f_min);
  613. /* host controller capabilities */
  614. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
  615. /* report supported voltage ranges */
  616. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  617. /* Set interrupt enables */
  618. host->hcfg = SDHCFG_BUSY_IRPT_EN;
  619. bcm2835_reset_internal(host);
  620. }
  621. static int bcm2835_probe(struct udevice *dev)
  622. {
  623. struct bcm2835_plat *plat = dev_get_platdata(dev);
  624. struct bcm2835_host *host = dev_get_priv(dev);
  625. struct mmc *mmc = mmc_get_mmc_dev(dev);
  626. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  627. host->dev = dev;
  628. host->mmc = mmc;
  629. host->plat = plat;
  630. upriv->mmc = &plat->mmc;
  631. plat->cfg.name = dev->name;
  632. host->phys_addr = devfdt_get_addr(dev);
  633. if (host->phys_addr == FDT_ADDR_T_NONE)
  634. return -EINVAL;
  635. host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256);
  636. if (!host->ioaddr)
  637. return -ENOMEM;
  638. host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
  639. bcm2835_add_host(host);
  640. dev_dbg(dev, "%s -> OK\n", __func__);
  641. return 0;
  642. }
  643. static const struct udevice_id bcm2835_match[] = {
  644. { .compatible = "brcm,bcm2835-sdhost" },
  645. { }
  646. };
  647. static const struct dm_mmc_ops bcm2835_ops = {
  648. .send_cmd = bcm2835_send_cmd,
  649. .set_ios = bcm2835_set_ios,
  650. };
  651. static int bcm2835_bind(struct udevice *dev)
  652. {
  653. struct bcm2835_plat *plat = dev_get_platdata(dev);
  654. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  655. }
  656. U_BOOT_DRIVER(bcm2835_sdhost) = {
  657. .name = "bcm2835-sdhost",
  658. .id = UCLASS_MMC,
  659. .of_match = bcm2835_match,
  660. .bind = bcm2835_bind,
  661. .probe = bcm2835_probe,
  662. .priv_auto_alloc_size = sizeof(struct bcm2835_host),
  663. .platdata_auto_alloc_size = sizeof(struct bcm2835_plat),
  664. .ops = &bcm2835_ops,
  665. };