clk-uniphier-core.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016-2017 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <dm/device_compat.h>
  10. #include <linux/bitops.h>
  11. #include <linux/bug.h>
  12. #include <linux/io.h>
  13. #include <linux/sizes.h>
  14. #include "clk-uniphier.h"
  15. /**
  16. * struct uniphier_clk_priv - private data for UniPhier clock driver
  17. *
  18. * @base: base address of the clock provider
  19. * @data: SoC specific data
  20. */
  21. struct uniphier_clk_priv {
  22. struct udevice *dev;
  23. void __iomem *base;
  24. const struct uniphier_clk_data *data;
  25. };
  26. static void uniphier_clk_gate_enable(struct uniphier_clk_priv *priv,
  27. const struct uniphier_clk_gate_data *gate)
  28. {
  29. u32 val;
  30. val = readl(priv->base + gate->reg);
  31. val |= BIT(gate->bit);
  32. writel(val, priv->base + gate->reg);
  33. }
  34. static void uniphier_clk_mux_set_parent(struct uniphier_clk_priv *priv,
  35. const struct uniphier_clk_mux_data *mux,
  36. u8 id)
  37. {
  38. u32 val;
  39. int i;
  40. for (i = 0; i < mux->num_parents; i++) {
  41. if (mux->parent_ids[i] != id)
  42. continue;
  43. val = readl(priv->base + mux->reg);
  44. val &= ~mux->masks[i];
  45. val |= mux->vals[i];
  46. writel(val, priv->base + mux->reg);
  47. return;
  48. }
  49. WARN_ON(1);
  50. }
  51. static u8 uniphier_clk_mux_get_parent(struct uniphier_clk_priv *priv,
  52. const struct uniphier_clk_mux_data *mux)
  53. {
  54. u32 val;
  55. int i;
  56. val = readl(priv->base + mux->reg);
  57. for (i = 0; i < mux->num_parents; i++)
  58. if ((mux->masks[i] & val) == mux->vals[i])
  59. return mux->parent_ids[i];
  60. dev_err(priv->dev, "invalid mux setting\n");
  61. return UNIPHIER_CLK_ID_INVALID;
  62. }
  63. static const struct uniphier_clk_data *uniphier_clk_get_data(
  64. struct uniphier_clk_priv *priv, u8 id)
  65. {
  66. const struct uniphier_clk_data *data;
  67. for (data = priv->data; data->type != UNIPHIER_CLK_TYPE_END; data++)
  68. if (data->id == id)
  69. return data;
  70. dev_err(priv->dev, "id=%u not found\n", id);
  71. return NULL;
  72. }
  73. static const struct uniphier_clk_data *uniphier_clk_get_parent_data(
  74. struct uniphier_clk_priv *priv,
  75. const struct uniphier_clk_data *data)
  76. {
  77. const struct uniphier_clk_data *parent_data;
  78. u8 parent_id = UNIPHIER_CLK_ID_INVALID;
  79. switch (data->type) {
  80. case UNIPHIER_CLK_TYPE_GATE:
  81. parent_id = data->data.gate.parent_id;
  82. break;
  83. case UNIPHIER_CLK_TYPE_MUX:
  84. parent_id = uniphier_clk_mux_get_parent(priv, &data->data.mux);
  85. break;
  86. default:
  87. break;
  88. }
  89. if (parent_id == UNIPHIER_CLK_ID_INVALID)
  90. return NULL;
  91. parent_data = uniphier_clk_get_data(priv, parent_id);
  92. WARN_ON(!parent_data);
  93. return parent_data;
  94. }
  95. static void __uniphier_clk_enable(struct uniphier_clk_priv *priv,
  96. const struct uniphier_clk_data *data)
  97. {
  98. const struct uniphier_clk_data *parent_data;
  99. if (data->type == UNIPHIER_CLK_TYPE_GATE)
  100. uniphier_clk_gate_enable(priv, &data->data.gate);
  101. parent_data = uniphier_clk_get_parent_data(priv, data);
  102. if (!parent_data)
  103. return;
  104. return __uniphier_clk_enable(priv, parent_data);
  105. }
  106. static int uniphier_clk_enable(struct clk *clk)
  107. {
  108. struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
  109. const struct uniphier_clk_data *data;
  110. data = uniphier_clk_get_data(priv, clk->id);
  111. if (!data)
  112. return -ENODEV;
  113. __uniphier_clk_enable(priv, data);
  114. return 0;
  115. }
  116. static unsigned long __uniphier_clk_get_rate(
  117. struct uniphier_clk_priv *priv,
  118. const struct uniphier_clk_data *data)
  119. {
  120. const struct uniphier_clk_data *parent_data;
  121. if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
  122. return data->data.rate.fixed_rate;
  123. parent_data = uniphier_clk_get_parent_data(priv, data);
  124. if (!parent_data)
  125. return 0;
  126. return __uniphier_clk_get_rate(priv, parent_data);
  127. }
  128. static unsigned long uniphier_clk_get_rate(struct clk *clk)
  129. {
  130. struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
  131. const struct uniphier_clk_data *data;
  132. data = uniphier_clk_get_data(priv, clk->id);
  133. if (!data)
  134. return -ENODEV;
  135. return __uniphier_clk_get_rate(priv, data);
  136. }
  137. static unsigned long __uniphier_clk_set_rate(
  138. struct uniphier_clk_priv *priv,
  139. const struct uniphier_clk_data *data,
  140. unsigned long rate, bool set)
  141. {
  142. const struct uniphier_clk_data *best_parent_data = NULL;
  143. const struct uniphier_clk_data *parent_data;
  144. unsigned long best_rate = 0;
  145. unsigned long parent_rate;
  146. u8 parent_id;
  147. int i;
  148. if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
  149. return data->data.rate.fixed_rate;
  150. if (data->type == UNIPHIER_CLK_TYPE_GATE) {
  151. parent_data = uniphier_clk_get_parent_data(priv, data);
  152. if (!parent_data)
  153. return 0;
  154. return __uniphier_clk_set_rate(priv, parent_data, rate, set);
  155. }
  156. if (WARN_ON(data->type != UNIPHIER_CLK_TYPE_MUX))
  157. return -EINVAL;
  158. for (i = 0; i < data->data.mux.num_parents; i++) {
  159. parent_id = data->data.mux.parent_ids[i];
  160. parent_data = uniphier_clk_get_data(priv, parent_id);
  161. if (WARN_ON(!parent_data))
  162. return -EINVAL;
  163. parent_rate = __uniphier_clk_set_rate(priv, parent_data, rate,
  164. false);
  165. if (parent_rate <= rate && best_rate < parent_rate) {
  166. best_rate = parent_rate;
  167. best_parent_data = parent_data;
  168. }
  169. }
  170. dev_dbg(priv->dev, "id=%u, best_rate=%lu\n", data->id, best_rate);
  171. if (!best_parent_data)
  172. return -EINVAL;
  173. if (!set)
  174. return best_rate;
  175. uniphier_clk_mux_set_parent(priv, &data->data.mux,
  176. best_parent_data->id);
  177. return best_rate = __uniphier_clk_set_rate(priv, best_parent_data,
  178. rate, true);
  179. }
  180. static unsigned long uniphier_clk_set_rate(struct clk *clk, ulong rate)
  181. {
  182. struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
  183. const struct uniphier_clk_data *data;
  184. data = uniphier_clk_get_data(priv, clk->id);
  185. if (!data)
  186. return -ENODEV;
  187. return __uniphier_clk_set_rate(priv, data, rate, true);
  188. }
  189. static const struct clk_ops uniphier_clk_ops = {
  190. .enable = uniphier_clk_enable,
  191. .get_rate = uniphier_clk_get_rate,
  192. .set_rate = uniphier_clk_set_rate,
  193. };
  194. static int uniphier_clk_probe(struct udevice *dev)
  195. {
  196. struct uniphier_clk_priv *priv = dev_get_priv(dev);
  197. fdt_addr_t addr;
  198. addr = devfdt_get_addr(dev->parent);
  199. if (addr == FDT_ADDR_T_NONE)
  200. return -EINVAL;
  201. priv->base = devm_ioremap(dev, addr, SZ_4K);
  202. if (!priv->base)
  203. return -ENOMEM;
  204. priv->dev = dev;
  205. priv->data = (void *)dev_get_driver_data(dev);
  206. return 0;
  207. }
  208. static const struct udevice_id uniphier_clk_match[] = {
  209. /* System clock */
  210. {
  211. .compatible = "socionext,uniphier-ld4-clock",
  212. .data = (ulong)uniphier_pxs2_sys_clk_data,
  213. },
  214. {
  215. .compatible = "socionext,uniphier-pro4-clock",
  216. .data = (ulong)uniphier_pxs2_sys_clk_data,
  217. },
  218. {
  219. .compatible = "socionext,uniphier-sld8-clock",
  220. .data = (ulong)uniphier_pxs2_sys_clk_data,
  221. },
  222. {
  223. .compatible = "socionext,uniphier-pro5-clock",
  224. .data = (ulong)uniphier_pxs2_sys_clk_data,
  225. },
  226. {
  227. .compatible = "socionext,uniphier-pxs2-clock",
  228. .data = (ulong)uniphier_pxs2_sys_clk_data,
  229. },
  230. {
  231. .compatible = "socionext,uniphier-ld11-clock",
  232. .data = (ulong)uniphier_ld20_sys_clk_data,
  233. },
  234. {
  235. .compatible = "socionext,uniphier-ld20-clock",
  236. .data = (ulong)uniphier_ld20_sys_clk_data,
  237. },
  238. {
  239. .compatible = "socionext,uniphier-pxs3-clock",
  240. .data = (ulong)uniphier_pxs3_sys_clk_data,
  241. },
  242. /* Media I/O clock */
  243. {
  244. .compatible = "socionext,uniphier-ld4-mio-clock",
  245. .data = (ulong)uniphier_mio_clk_data,
  246. },
  247. {
  248. .compatible = "socionext,uniphier-pro4-mio-clock",
  249. .data = (ulong)uniphier_mio_clk_data,
  250. },
  251. {
  252. .compatible = "socionext,uniphier-sld8-mio-clock",
  253. .data = (ulong)uniphier_mio_clk_data,
  254. },
  255. {
  256. .compatible = "socionext,uniphier-pro5-sd-clock",
  257. .data = (ulong)uniphier_mio_clk_data,
  258. },
  259. {
  260. .compatible = "socionext,uniphier-pxs2-sd-clock",
  261. .data = (ulong)uniphier_mio_clk_data,
  262. },
  263. {
  264. .compatible = "socionext,uniphier-ld11-mio-clock",
  265. .data = (ulong)uniphier_mio_clk_data,
  266. },
  267. {
  268. .compatible = "socionext,uniphier-ld20-sd-clock",
  269. .data = (ulong)uniphier_mio_clk_data,
  270. },
  271. {
  272. .compatible = "socionext,uniphier-pxs3-sd-clock",
  273. .data = (ulong)uniphier_mio_clk_data,
  274. },
  275. { /* sentinel */ }
  276. };
  277. U_BOOT_DRIVER(uniphier_clk) = {
  278. .name = "uniphier-clk",
  279. .id = UCLASS_CLK,
  280. .of_match = uniphier_clk_match,
  281. .probe = uniphier_clk_probe,
  282. .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
  283. .ops = &uniphier_clk_ops,
  284. };