ctrl_regs.c 70 KB

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  1. /*
  2. * Copyright 2008-2014 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  8. * Based on code from spd_sdram.c
  9. * Author: James Yang [at freescale.com]
  10. */
  11. #include <common.h>
  12. #include <fsl_ddr_sdram.h>
  13. #include <fsl_ddr.h>
  14. #include <fsl_immap.h>
  15. #include <asm/io.h>
  16. /*
  17. * Determine Rtt value.
  18. *
  19. * This should likely be either board or controller specific.
  20. *
  21. * Rtt(nominal) - DDR2:
  22. * 0 = Rtt disabled
  23. * 1 = 75 ohm
  24. * 2 = 150 ohm
  25. * 3 = 50 ohm
  26. * Rtt(nominal) - DDR3:
  27. * 0 = Rtt disabled
  28. * 1 = 60 ohm
  29. * 2 = 120 ohm
  30. * 3 = 40 ohm
  31. * 4 = 20 ohm
  32. * 5 = 30 ohm
  33. *
  34. * FIXME: Apparently 8641 needs a value of 2
  35. * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  36. *
  37. * FIXME: There was some effort down this line earlier:
  38. *
  39. * unsigned int i;
  40. * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  41. * if (popts->dimmslot[i].num_valid_cs
  42. * && (popts->cs_local_opts[2*i].odt_rd_cfg
  43. * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  44. * rtt = 2;
  45. * break;
  46. * }
  47. * }
  48. */
  49. static inline int fsl_ddr_get_rtt(void)
  50. {
  51. int rtt;
  52. #if defined(CONFIG_SYS_FSL_DDR1)
  53. rtt = 0;
  54. #elif defined(CONFIG_SYS_FSL_DDR2)
  55. rtt = 3;
  56. #else
  57. rtt = 0;
  58. #endif
  59. return rtt;
  60. }
  61. #ifdef CONFIG_SYS_FSL_DDR4
  62. /*
  63. * compute CAS write latency according to DDR4 spec
  64. * CWL = 9 for <= 1600MT/s
  65. * 10 for <= 1866MT/s
  66. * 11 for <= 2133MT/s
  67. * 12 for <= 2400MT/s
  68. * 14 for <= 2667MT/s
  69. * 16 for <= 2933MT/s
  70. * 18 for higher
  71. */
  72. static inline unsigned int compute_cas_write_latency(
  73. const unsigned int ctrl_num)
  74. {
  75. unsigned int cwl;
  76. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  77. if (mclk_ps >= 1250)
  78. cwl = 9;
  79. else if (mclk_ps >= 1070)
  80. cwl = 10;
  81. else if (mclk_ps >= 935)
  82. cwl = 11;
  83. else if (mclk_ps >= 833)
  84. cwl = 12;
  85. else if (mclk_ps >= 750)
  86. cwl = 14;
  87. else if (mclk_ps >= 681)
  88. cwl = 16;
  89. else
  90. cwl = 18;
  91. return cwl;
  92. }
  93. #else
  94. /*
  95. * compute the CAS write latency according to DDR3 spec
  96. * CWL = 5 if tCK >= 2.5ns
  97. * 6 if 2.5ns > tCK >= 1.875ns
  98. * 7 if 1.875ns > tCK >= 1.5ns
  99. * 8 if 1.5ns > tCK >= 1.25ns
  100. * 9 if 1.25ns > tCK >= 1.07ns
  101. * 10 if 1.07ns > tCK >= 0.935ns
  102. * 11 if 0.935ns > tCK >= 0.833ns
  103. * 12 if 0.833ns > tCK >= 0.75ns
  104. */
  105. static inline unsigned int compute_cas_write_latency(
  106. const unsigned int ctrl_num)
  107. {
  108. unsigned int cwl;
  109. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  110. if (mclk_ps >= 2500)
  111. cwl = 5;
  112. else if (mclk_ps >= 1875)
  113. cwl = 6;
  114. else if (mclk_ps >= 1500)
  115. cwl = 7;
  116. else if (mclk_ps >= 1250)
  117. cwl = 8;
  118. else if (mclk_ps >= 1070)
  119. cwl = 9;
  120. else if (mclk_ps >= 935)
  121. cwl = 10;
  122. else if (mclk_ps >= 833)
  123. cwl = 11;
  124. else if (mclk_ps >= 750)
  125. cwl = 12;
  126. else {
  127. cwl = 12;
  128. printf("Warning: CWL is out of range\n");
  129. }
  130. return cwl;
  131. }
  132. #endif
  133. /* Chip Select Configuration (CSn_CONFIG) */
  134. static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
  135. const memctl_options_t *popts,
  136. const dimm_params_t *dimm_params)
  137. {
  138. unsigned int cs_n_en = 0; /* Chip Select enable */
  139. unsigned int intlv_en = 0; /* Memory controller interleave enable */
  140. unsigned int intlv_ctl = 0; /* Interleaving control */
  141. unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
  142. unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
  143. unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
  144. unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
  145. unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
  146. unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
  147. int go_config = 0;
  148. #ifdef CONFIG_SYS_FSL_DDR4
  149. unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
  150. #else
  151. unsigned int n_banks_per_sdram_device;
  152. #endif
  153. /* Compute CS_CONFIG only for existing ranks of each DIMM. */
  154. switch (i) {
  155. case 0:
  156. if (dimm_params[dimm_number].n_ranks > 0) {
  157. go_config = 1;
  158. /* These fields only available in CS0_CONFIG */
  159. if (!popts->memctl_interleaving)
  160. break;
  161. switch (popts->memctl_interleaving_mode) {
  162. case FSL_DDR_256B_INTERLEAVING:
  163. case FSL_DDR_CACHE_LINE_INTERLEAVING:
  164. case FSL_DDR_PAGE_INTERLEAVING:
  165. case FSL_DDR_BANK_INTERLEAVING:
  166. case FSL_DDR_SUPERBANK_INTERLEAVING:
  167. intlv_en = popts->memctl_interleaving;
  168. intlv_ctl = popts->memctl_interleaving_mode;
  169. break;
  170. default:
  171. break;
  172. }
  173. }
  174. break;
  175. case 1:
  176. if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
  177. (dimm_number == 1 && dimm_params[1].n_ranks > 0))
  178. go_config = 1;
  179. break;
  180. case 2:
  181. if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
  182. (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
  183. go_config = 1;
  184. break;
  185. case 3:
  186. if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
  187. (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
  188. (dimm_number == 3 && dimm_params[3].n_ranks > 0))
  189. go_config = 1;
  190. break;
  191. default:
  192. break;
  193. }
  194. if (go_config) {
  195. cs_n_en = 1;
  196. ap_n_en = popts->cs_local_opts[i].auto_precharge;
  197. odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
  198. odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
  199. #ifdef CONFIG_SYS_FSL_DDR4
  200. ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
  201. bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
  202. #else
  203. n_banks_per_sdram_device
  204. = dimm_params[dimm_number].n_banks_per_sdram_device;
  205. ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
  206. #endif
  207. row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
  208. col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
  209. }
  210. ddr->cs[i].config = (0
  211. | ((cs_n_en & 0x1) << 31)
  212. | ((intlv_en & 0x3) << 29)
  213. | ((intlv_ctl & 0xf) << 24)
  214. | ((ap_n_en & 0x1) << 23)
  215. /* XXX: some implementation only have 1 bit starting at left */
  216. | ((odt_rd_cfg & 0x7) << 20)
  217. /* XXX: Some implementation only have 1 bit starting at left */
  218. | ((odt_wr_cfg & 0x7) << 16)
  219. | ((ba_bits_cs_n & 0x3) << 14)
  220. | ((row_bits_cs_n & 0x7) << 8)
  221. #ifdef CONFIG_SYS_FSL_DDR4
  222. | ((bg_bits_cs_n & 0x3) << 4)
  223. #endif
  224. | ((col_bits_cs_n & 0x7) << 0)
  225. );
  226. debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
  227. }
  228. /* Chip Select Configuration 2 (CSn_CONFIG_2) */
  229. /* FIXME: 8572 */
  230. static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
  231. {
  232. unsigned int pasr_cfg = 0; /* Partial array self refresh config */
  233. ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
  234. debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
  235. }
  236. /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
  237. #if !defined(CONFIG_SYS_FSL_DDR1)
  238. /*
  239. * Check DIMM configuration, return 2 if quad-rank or two dual-rank
  240. * Return 1 if other two slots configuration. Return 0 if single slot.
  241. */
  242. static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
  243. {
  244. #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
  245. if (dimm_params[0].n_ranks == 4)
  246. return 2;
  247. #endif
  248. #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
  249. if ((dimm_params[0].n_ranks == 2) &&
  250. (dimm_params[1].n_ranks == 2))
  251. return 2;
  252. #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  253. if (dimm_params[0].n_ranks == 4)
  254. return 2;
  255. #endif
  256. if ((dimm_params[0].n_ranks != 0) &&
  257. (dimm_params[2].n_ranks != 0))
  258. return 1;
  259. #endif
  260. return 0;
  261. }
  262. /*
  263. * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
  264. *
  265. * Avoid writing for DDR I. The new PQ38 DDR controller
  266. * dreams up non-zero default values to be backwards compatible.
  267. */
  268. static void set_timing_cfg_0(const unsigned int ctrl_num,
  269. fsl_ddr_cfg_regs_t *ddr,
  270. const memctl_options_t *popts,
  271. const dimm_params_t *dimm_params)
  272. {
  273. unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
  274. unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
  275. /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
  276. unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
  277. unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
  278. /* Active powerdown exit timing (tXARD and tXARDS). */
  279. unsigned char act_pd_exit_mclk;
  280. /* Precharge powerdown exit timing (tXP). */
  281. unsigned char pre_pd_exit_mclk;
  282. /* ODT powerdown exit timing (tAXPD). */
  283. unsigned char taxpd_mclk = 0;
  284. /* Mode register set cycle time (tMRD). */
  285. unsigned char tmrd_mclk;
  286. #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
  287. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  288. #endif
  289. #ifdef CONFIG_SYS_FSL_DDR4
  290. /* tXP=max(4nCK, 6ns) */
  291. int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
  292. unsigned int data_rate = get_ddr_freq(ctrl_num);
  293. /* for faster clock, need more time for data setup */
  294. trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
  295. /*
  296. * for single quad-rank DIMM and two-slot DIMMs
  297. * to avoid ODT overlap
  298. */
  299. switch (avoid_odt_overlap(dimm_params)) {
  300. case 2:
  301. twrt_mclk = 2;
  302. twwt_mclk = 2;
  303. trrt_mclk = 2;
  304. break;
  305. default:
  306. twrt_mclk = 1;
  307. twwt_mclk = 1;
  308. trrt_mclk = 0;
  309. break;
  310. }
  311. act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
  312. pre_pd_exit_mclk = act_pd_exit_mclk;
  313. /*
  314. * MRS_CYC = max(tMRD, tMOD)
  315. * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
  316. */
  317. tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
  318. #elif defined(CONFIG_SYS_FSL_DDR3)
  319. unsigned int data_rate = get_ddr_freq(ctrl_num);
  320. int txp;
  321. unsigned int ip_rev;
  322. int odt_overlap;
  323. /*
  324. * (tXARD and tXARDS). Empirical?
  325. * The DDR3 spec has not tXARD,
  326. * we use the tXP instead of it.
  327. * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
  328. * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
  329. * spec has not the tAXPD, we use
  330. * tAXPD=1, need design to confirm.
  331. */
  332. txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
  333. ip_rev = fsl_ddr_get_version(ctrl_num);
  334. if (ip_rev >= 0x40700) {
  335. /*
  336. * MRS_CYC = max(tMRD, tMOD)
  337. * tMRD = 4nCK (8nCK for RDIMM)
  338. * tMOD = max(12nCK, 15ns)
  339. */
  340. tmrd_mclk = max((unsigned int)12,
  341. picos_to_mclk(ctrl_num, 15000));
  342. } else {
  343. /*
  344. * MRS_CYC = tMRD
  345. * tMRD = 4nCK (8nCK for RDIMM)
  346. */
  347. if (popts->registered_dimm_en)
  348. tmrd_mclk = 8;
  349. else
  350. tmrd_mclk = 4;
  351. }
  352. /* set the turnaround time */
  353. /*
  354. * for single quad-rank DIMM and two-slot DIMMs
  355. * to avoid ODT overlap
  356. */
  357. odt_overlap = avoid_odt_overlap(dimm_params);
  358. switch (odt_overlap) {
  359. case 2:
  360. twwt_mclk = 2;
  361. trrt_mclk = 1;
  362. break;
  363. case 1:
  364. twwt_mclk = 1;
  365. trrt_mclk = 0;
  366. break;
  367. default:
  368. break;
  369. }
  370. /* for faster clock, need more time for data setup */
  371. trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
  372. if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
  373. twrt_mclk = 1;
  374. if (popts->dynamic_power == 0) { /* powerdown is not used */
  375. act_pd_exit_mclk = 1;
  376. pre_pd_exit_mclk = 1;
  377. taxpd_mclk = 1;
  378. } else {
  379. /* act_pd_exit_mclk = tXARD, see above */
  380. act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
  381. /* Mode register MR0[A12] is '1' - fast exit */
  382. pre_pd_exit_mclk = act_pd_exit_mclk;
  383. taxpd_mclk = 1;
  384. }
  385. #else /* CONFIG_SYS_FSL_DDR2 */
  386. /*
  387. * (tXARD and tXARDS). Empirical?
  388. * tXARD = 2 for DDR2
  389. * tXP=2
  390. * tAXPD=8
  391. */
  392. act_pd_exit_mclk = 2;
  393. pre_pd_exit_mclk = 2;
  394. taxpd_mclk = 8;
  395. tmrd_mclk = 2;
  396. #endif
  397. if (popts->trwt_override)
  398. trwt_mclk = popts->trwt;
  399. ddr->timing_cfg_0 = (0
  400. | ((trwt_mclk & 0x3) << 30) /* RWT */
  401. | ((twrt_mclk & 0x3) << 28) /* WRT */
  402. | ((trrt_mclk & 0x3) << 26) /* RRT */
  403. | ((twwt_mclk & 0x3) << 24) /* WWT */
  404. | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
  405. | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
  406. | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
  407. | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
  408. );
  409. debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
  410. }
  411. #endif /* !defined(CONFIG_SYS_FSL_DDR1) */
  412. /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
  413. static void set_timing_cfg_3(const unsigned int ctrl_num,
  414. fsl_ddr_cfg_regs_t *ddr,
  415. const memctl_options_t *popts,
  416. const common_timing_params_t *common_dimm,
  417. unsigned int cas_latency,
  418. unsigned int additive_latency)
  419. {
  420. /* Extended precharge to activate interval (tRP) */
  421. unsigned int ext_pretoact = 0;
  422. /* Extended Activate to precharge interval (tRAS) */
  423. unsigned int ext_acttopre = 0;
  424. /* Extended activate to read/write interval (tRCD) */
  425. unsigned int ext_acttorw = 0;
  426. /* Extended refresh recovery time (tRFC) */
  427. unsigned int ext_refrec;
  428. /* Extended MCAS latency from READ cmd */
  429. unsigned int ext_caslat = 0;
  430. /* Extended additive latency */
  431. unsigned int ext_add_lat = 0;
  432. /* Extended last data to precharge interval (tWR) */
  433. unsigned int ext_wrrec = 0;
  434. /* Control Adjust */
  435. unsigned int cntl_adj = 0;
  436. ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
  437. ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
  438. ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
  439. ext_caslat = (2 * cas_latency - 1) >> 4;
  440. ext_add_lat = additive_latency >> 4;
  441. #ifdef CONFIG_SYS_FSL_DDR4
  442. ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
  443. #else
  444. ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
  445. /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
  446. #endif
  447. ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
  448. (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
  449. ddr->timing_cfg_3 = (0
  450. | ((ext_pretoact & 0x1) << 28)
  451. | ((ext_acttopre & 0x3) << 24)
  452. | ((ext_acttorw & 0x1) << 22)
  453. | ((ext_refrec & 0x1F) << 16)
  454. | ((ext_caslat & 0x3) << 12)
  455. | ((ext_add_lat & 0x1) << 10)
  456. | ((ext_wrrec & 0x1) << 8)
  457. | ((cntl_adj & 0x7) << 0)
  458. );
  459. debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
  460. }
  461. /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
  462. static void set_timing_cfg_1(const unsigned int ctrl_num,
  463. fsl_ddr_cfg_regs_t *ddr,
  464. const memctl_options_t *popts,
  465. const common_timing_params_t *common_dimm,
  466. unsigned int cas_latency)
  467. {
  468. /* Precharge-to-activate interval (tRP) */
  469. unsigned char pretoact_mclk;
  470. /* Activate to precharge interval (tRAS) */
  471. unsigned char acttopre_mclk;
  472. /* Activate to read/write interval (tRCD) */
  473. unsigned char acttorw_mclk;
  474. /* CASLAT */
  475. unsigned char caslat_ctrl;
  476. /* Refresh recovery time (tRFC) ; trfc_low */
  477. unsigned char refrec_ctrl;
  478. /* Last data to precharge minimum interval (tWR) */
  479. unsigned char wrrec_mclk;
  480. /* Activate-to-activate interval (tRRD) */
  481. unsigned char acttoact_mclk;
  482. /* Last write data pair to read command issue interval (tWTR) */
  483. unsigned char wrtord_mclk;
  484. #ifdef CONFIG_SYS_FSL_DDR4
  485. /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
  486. static const u8 wrrec_table[] = {
  487. 10, 10, 10, 10, 10,
  488. 10, 10, 10, 10, 10,
  489. 12, 12, 14, 14, 16,
  490. 16, 18, 18, 20, 20,
  491. 24, 24, 24, 24};
  492. #else
  493. /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
  494. static const u8 wrrec_table[] = {
  495. 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
  496. #endif
  497. pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
  498. acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
  499. acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
  500. /*
  501. * Translate CAS Latency to a DDR controller field value:
  502. *
  503. * CAS Lat DDR I DDR II Ctrl
  504. * Clocks SPD Bit SPD Bit Value
  505. * ------- ------- ------- -----
  506. * 1.0 0 0001
  507. * 1.5 1 0010
  508. * 2.0 2 2 0011
  509. * 2.5 3 0100
  510. * 3.0 4 3 0101
  511. * 3.5 5 0110
  512. * 4.0 4 0111
  513. * 4.5 1000
  514. * 5.0 5 1001
  515. */
  516. #if defined(CONFIG_SYS_FSL_DDR1)
  517. caslat_ctrl = (cas_latency + 1) & 0x07;
  518. #elif defined(CONFIG_SYS_FSL_DDR2)
  519. caslat_ctrl = 2 * cas_latency - 1;
  520. #else
  521. /*
  522. * if the CAS latency more than 8 cycle,
  523. * we need set extend bit for it at
  524. * TIMING_CFG_3[EXT_CASLAT]
  525. */
  526. if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
  527. caslat_ctrl = 2 * cas_latency - 1;
  528. else
  529. caslat_ctrl = (cas_latency - 1) << 1;
  530. #endif
  531. #ifdef CONFIG_SYS_FSL_DDR4
  532. refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
  533. wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
  534. acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
  535. wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
  536. if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
  537. printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
  538. else
  539. wrrec_mclk = wrrec_table[wrrec_mclk - 1];
  540. #else
  541. refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
  542. wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
  543. acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
  544. wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
  545. if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
  546. printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
  547. else
  548. wrrec_mclk = wrrec_table[wrrec_mclk - 1];
  549. #endif
  550. if (popts->otf_burst_chop_en)
  551. wrrec_mclk += 2;
  552. /*
  553. * JEDEC has min requirement for tRRD
  554. */
  555. #if defined(CONFIG_SYS_FSL_DDR3)
  556. if (acttoact_mclk < 4)
  557. acttoact_mclk = 4;
  558. #endif
  559. /*
  560. * JEDEC has some min requirements for tWTR
  561. */
  562. #if defined(CONFIG_SYS_FSL_DDR2)
  563. if (wrtord_mclk < 2)
  564. wrtord_mclk = 2;
  565. #elif defined(CONFIG_SYS_FSL_DDR3)
  566. if (wrtord_mclk < 4)
  567. wrtord_mclk = 4;
  568. #endif
  569. if (popts->otf_burst_chop_en)
  570. wrtord_mclk += 2;
  571. ddr->timing_cfg_1 = (0
  572. | ((pretoact_mclk & 0x0F) << 28)
  573. | ((acttopre_mclk & 0x0F) << 24)
  574. | ((acttorw_mclk & 0xF) << 20)
  575. | ((caslat_ctrl & 0xF) << 16)
  576. | ((refrec_ctrl & 0xF) << 12)
  577. | ((wrrec_mclk & 0x0F) << 8)
  578. | ((acttoact_mclk & 0x0F) << 4)
  579. | ((wrtord_mclk & 0x0F) << 0)
  580. );
  581. debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
  582. }
  583. /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
  584. static void set_timing_cfg_2(const unsigned int ctrl_num,
  585. fsl_ddr_cfg_regs_t *ddr,
  586. const memctl_options_t *popts,
  587. const common_timing_params_t *common_dimm,
  588. unsigned int cas_latency,
  589. unsigned int additive_latency)
  590. {
  591. /* Additive latency */
  592. unsigned char add_lat_mclk;
  593. /* CAS-to-preamble override */
  594. unsigned short cpo;
  595. /* Write latency */
  596. unsigned char wr_lat;
  597. /* Read to precharge (tRTP) */
  598. unsigned char rd_to_pre;
  599. /* Write command to write data strobe timing adjustment */
  600. unsigned char wr_data_delay;
  601. /* Minimum CKE pulse width (tCKE) */
  602. unsigned char cke_pls;
  603. /* Window for four activates (tFAW) */
  604. unsigned short four_act;
  605. #ifdef CONFIG_SYS_FSL_DDR3
  606. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  607. #endif
  608. /* FIXME add check that this must be less than acttorw_mclk */
  609. add_lat_mclk = additive_latency;
  610. cpo = popts->cpo_override;
  611. #if defined(CONFIG_SYS_FSL_DDR1)
  612. /*
  613. * This is a lie. It should really be 1, but if it is
  614. * set to 1, bits overlap into the old controller's
  615. * otherwise unused ACSM field. If we leave it 0, then
  616. * the HW will magically treat it as 1 for DDR 1. Oh Yea.
  617. */
  618. wr_lat = 0;
  619. #elif defined(CONFIG_SYS_FSL_DDR2)
  620. wr_lat = cas_latency - 1;
  621. #else
  622. wr_lat = compute_cas_write_latency(ctrl_num);
  623. #endif
  624. #ifdef CONFIG_SYS_FSL_DDR4
  625. rd_to_pre = picos_to_mclk(ctrl_num, 7500);
  626. #else
  627. rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
  628. #endif
  629. /*
  630. * JEDEC has some min requirements for tRTP
  631. */
  632. #if defined(CONFIG_SYS_FSL_DDR2)
  633. if (rd_to_pre < 2)
  634. rd_to_pre = 2;
  635. #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  636. if (rd_to_pre < 4)
  637. rd_to_pre = 4;
  638. #endif
  639. if (popts->otf_burst_chop_en)
  640. rd_to_pre += 2; /* according to UM */
  641. wr_data_delay = popts->write_data_delay;
  642. #ifdef CONFIG_SYS_FSL_DDR4
  643. cpo = 0;
  644. cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
  645. #elif defined(CONFIG_SYS_FSL_DDR3)
  646. /*
  647. * cke pulse = max(3nCK, 7.5ns) for DDR3-800
  648. * max(3nCK, 5.625ns) for DDR3-1066, 1333
  649. * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
  650. */
  651. cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
  652. (mclk_ps > 1245 ? 5625 : 5000)));
  653. #else
  654. cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
  655. #endif
  656. four_act = picos_to_mclk(ctrl_num,
  657. popts->tfaw_window_four_activates_ps);
  658. ddr->timing_cfg_2 = (0
  659. | ((add_lat_mclk & 0xf) << 28)
  660. | ((cpo & 0x1f) << 23)
  661. | ((wr_lat & 0xf) << 19)
  662. | ((wr_lat & 0x10) << 14)
  663. | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
  664. | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
  665. | ((cke_pls & 0x7) << 6)
  666. | ((four_act & 0x3f) << 0)
  667. );
  668. debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
  669. }
  670. /* DDR SDRAM Register Control Word */
  671. static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
  672. const memctl_options_t *popts,
  673. const common_timing_params_t *common_dimm)
  674. {
  675. if (common_dimm->all_dimms_registered &&
  676. !common_dimm->all_dimms_unbuffered) {
  677. if (popts->rcw_override) {
  678. ddr->ddr_sdram_rcw_1 = popts->rcw_1;
  679. ddr->ddr_sdram_rcw_2 = popts->rcw_2;
  680. } else {
  681. ddr->ddr_sdram_rcw_1 =
  682. common_dimm->rcw[0] << 28 | \
  683. common_dimm->rcw[1] << 24 | \
  684. common_dimm->rcw[2] << 20 | \
  685. common_dimm->rcw[3] << 16 | \
  686. common_dimm->rcw[4] << 12 | \
  687. common_dimm->rcw[5] << 8 | \
  688. common_dimm->rcw[6] << 4 | \
  689. common_dimm->rcw[7];
  690. ddr->ddr_sdram_rcw_2 =
  691. common_dimm->rcw[8] << 28 | \
  692. common_dimm->rcw[9] << 24 | \
  693. common_dimm->rcw[10] << 20 | \
  694. common_dimm->rcw[11] << 16 | \
  695. common_dimm->rcw[12] << 12 | \
  696. common_dimm->rcw[13] << 8 | \
  697. common_dimm->rcw[14] << 4 | \
  698. common_dimm->rcw[15];
  699. }
  700. debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
  701. debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
  702. }
  703. }
  704. /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
  705. static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
  706. const memctl_options_t *popts,
  707. const common_timing_params_t *common_dimm)
  708. {
  709. unsigned int mem_en; /* DDR SDRAM interface logic enable */
  710. unsigned int sren; /* Self refresh enable (during sleep) */
  711. unsigned int ecc_en; /* ECC enable. */
  712. unsigned int rd_en; /* Registered DIMM enable */
  713. unsigned int sdram_type; /* Type of SDRAM */
  714. unsigned int dyn_pwr; /* Dynamic power management mode */
  715. unsigned int dbw; /* DRAM dta bus width */
  716. unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
  717. unsigned int ncap = 0; /* Non-concurrent auto-precharge */
  718. unsigned int threet_en; /* Enable 3T timing */
  719. unsigned int twot_en; /* Enable 2T timing */
  720. unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
  721. unsigned int x32_en = 0; /* x32 enable */
  722. unsigned int pchb8 = 0; /* precharge bit 8 enable */
  723. unsigned int hse; /* Global half strength override */
  724. unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
  725. unsigned int mem_halt = 0; /* memory controller halt */
  726. unsigned int bi = 0; /* Bypass initialization */
  727. mem_en = 1;
  728. sren = popts->self_refresh_in_sleep;
  729. if (common_dimm->all_dimms_ecc_capable) {
  730. /* Allow setting of ECC only if all DIMMs are ECC. */
  731. ecc_en = popts->ecc_mode;
  732. } else {
  733. ecc_en = 0;
  734. }
  735. if (common_dimm->all_dimms_registered &&
  736. !common_dimm->all_dimms_unbuffered) {
  737. rd_en = 1;
  738. twot_en = 0;
  739. } else {
  740. rd_en = 0;
  741. twot_en = popts->twot_en;
  742. }
  743. sdram_type = CONFIG_FSL_SDRAM_TYPE;
  744. dyn_pwr = popts->dynamic_power;
  745. dbw = popts->data_bus_width;
  746. /* 8-beat burst enable DDR-III case
  747. * we must clear it when use the on-the-fly mode,
  748. * must set it when use the 32-bits bus mode.
  749. */
  750. if ((sdram_type == SDRAM_TYPE_DDR3) ||
  751. (sdram_type == SDRAM_TYPE_DDR4)) {
  752. if (popts->burst_length == DDR_BL8)
  753. eight_be = 1;
  754. if (popts->burst_length == DDR_OTF)
  755. eight_be = 0;
  756. if (dbw == 0x1)
  757. eight_be = 1;
  758. }
  759. threet_en = popts->threet_en;
  760. ba_intlv_ctl = popts->ba_intlv_ctl;
  761. hse = popts->half_strength_driver_enable;
  762. /* set when ddr bus width < 64 */
  763. acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
  764. ddr->ddr_sdram_cfg = (0
  765. | ((mem_en & 0x1) << 31)
  766. | ((sren & 0x1) << 30)
  767. | ((ecc_en & 0x1) << 29)
  768. | ((rd_en & 0x1) << 28)
  769. | ((sdram_type & 0x7) << 24)
  770. | ((dyn_pwr & 0x1) << 21)
  771. | ((dbw & 0x3) << 19)
  772. | ((eight_be & 0x1) << 18)
  773. | ((ncap & 0x1) << 17)
  774. | ((threet_en & 0x1) << 16)
  775. | ((twot_en & 0x1) << 15)
  776. | ((ba_intlv_ctl & 0x7F) << 8)
  777. | ((x32_en & 0x1) << 5)
  778. | ((pchb8 & 0x1) << 4)
  779. | ((hse & 0x1) << 3)
  780. | ((acc_ecc_en & 0x1) << 2)
  781. | ((mem_halt & 0x1) << 1)
  782. | ((bi & 0x1) << 0)
  783. );
  784. debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
  785. }
  786. /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
  787. static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
  788. fsl_ddr_cfg_regs_t *ddr,
  789. const memctl_options_t *popts,
  790. const unsigned int unq_mrs_en)
  791. {
  792. unsigned int frc_sr = 0; /* Force self refresh */
  793. unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
  794. unsigned int odt_cfg = 0; /* ODT configuration */
  795. unsigned int num_pr; /* Number of posted refreshes */
  796. unsigned int slow = 0; /* DDR will be run less than 1250 */
  797. unsigned int x4_en = 0; /* x4 DRAM enable */
  798. unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
  799. unsigned int ap_en; /* Address Parity Enable */
  800. unsigned int d_init; /* DRAM data initialization */
  801. unsigned int rcw_en = 0; /* Register Control Word Enable */
  802. unsigned int md_en = 0; /* Mirrored DIMM Enable */
  803. unsigned int qd_en = 0; /* quad-rank DIMM Enable */
  804. int i;
  805. #ifndef CONFIG_SYS_FSL_DDR4
  806. unsigned int dll_rst_dis = 1; /* DLL reset disable */
  807. unsigned int dqs_cfg; /* DQS configuration */
  808. dqs_cfg = popts->dqs_config;
  809. #endif
  810. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  811. if (popts->cs_local_opts[i].odt_rd_cfg
  812. || popts->cs_local_opts[i].odt_wr_cfg) {
  813. odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
  814. break;
  815. }
  816. }
  817. sr_ie = popts->self_refresh_interrupt_en;
  818. num_pr = 1; /* Make this configurable */
  819. /*
  820. * 8572 manual says
  821. * {TIMING_CFG_1[PRETOACT]
  822. * + [DDR_SDRAM_CFG_2[NUM_PR]
  823. * * ({EXT_REFREC || REFREC} + 8 + 2)]}
  824. * << DDR_SDRAM_INTERVAL[REFINT]
  825. */
  826. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  827. obc_cfg = popts->otf_burst_chop_en;
  828. #else
  829. obc_cfg = 0;
  830. #endif
  831. #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
  832. slow = get_ddr_freq(ctrl_num) < 1249000000;
  833. #endif
  834. if (popts->registered_dimm_en)
  835. rcw_en = 1;
  836. /* DDR4 can have address parity for UDIMM and discrete */
  837. if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
  838. (!popts->registered_dimm_en)) {
  839. ap_en = 0;
  840. } else {
  841. ap_en = popts->ap_en;
  842. }
  843. x4_en = popts->x4_en ? 1 : 0;
  844. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  845. /* Use the DDR controller to auto initialize memory. */
  846. d_init = popts->ecc_init_using_memctl;
  847. ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
  848. debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
  849. #else
  850. /* Memory will be initialized via DMA, or not at all. */
  851. d_init = 0;
  852. #endif
  853. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  854. md_en = popts->mirrored_dimm;
  855. #endif
  856. qd_en = popts->quad_rank_present ? 1 : 0;
  857. ddr->ddr_sdram_cfg_2 = (0
  858. | ((frc_sr & 0x1) << 31)
  859. | ((sr_ie & 0x1) << 30)
  860. #ifndef CONFIG_SYS_FSL_DDR4
  861. | ((dll_rst_dis & 0x1) << 29)
  862. | ((dqs_cfg & 0x3) << 26)
  863. #endif
  864. | ((odt_cfg & 0x3) << 21)
  865. | ((num_pr & 0xf) << 12)
  866. | ((slow & 1) << 11)
  867. | (x4_en << 10)
  868. | (qd_en << 9)
  869. | (unq_mrs_en << 8)
  870. | ((obc_cfg & 0x1) << 6)
  871. | ((ap_en & 0x1) << 5)
  872. | ((d_init & 0x1) << 4)
  873. | ((rcw_en & 0x1) << 2)
  874. | ((md_en & 0x1) << 0)
  875. );
  876. debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
  877. }
  878. #ifdef CONFIG_SYS_FSL_DDR4
  879. /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
  880. static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
  881. fsl_ddr_cfg_regs_t *ddr,
  882. const memctl_options_t *popts,
  883. const common_timing_params_t *common_dimm,
  884. const unsigned int unq_mrs_en)
  885. {
  886. unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
  887. unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
  888. int i;
  889. unsigned int wr_crc = 0; /* Disable */
  890. unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
  891. unsigned int srt = 0; /* self-refresh temerature, normal range */
  892. unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
  893. unsigned int mpr = 0; /* serial */
  894. unsigned int wc_lat;
  895. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  896. if (popts->rtt_override)
  897. rtt_wr = popts->rtt_wr_override_value;
  898. else
  899. rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
  900. if (common_dimm->extended_op_srt)
  901. srt = common_dimm->extended_op_srt;
  902. esdmode2 = (0
  903. | ((wr_crc & 0x1) << 12)
  904. | ((rtt_wr & 0x3) << 9)
  905. | ((srt & 0x3) << 6)
  906. | ((cwl & 0x7) << 3));
  907. if (mclk_ps >= 1250)
  908. wc_lat = 0;
  909. else if (mclk_ps >= 833)
  910. wc_lat = 1;
  911. else
  912. wc_lat = 2;
  913. esdmode3 = (0
  914. | ((mpr & 0x3) << 11)
  915. | ((wc_lat & 0x3) << 9));
  916. ddr->ddr_sdram_mode_2 = (0
  917. | ((esdmode2 & 0xFFFF) << 16)
  918. | ((esdmode3 & 0xFFFF) << 0)
  919. );
  920. debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
  921. if (unq_mrs_en) { /* unique mode registers are supported */
  922. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  923. if (popts->rtt_override)
  924. rtt_wr = popts->rtt_wr_override_value;
  925. else
  926. rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
  927. esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
  928. esdmode2 |= (rtt_wr & 0x3) << 9;
  929. switch (i) {
  930. case 1:
  931. ddr->ddr_sdram_mode_4 = (0
  932. | ((esdmode2 & 0xFFFF) << 16)
  933. | ((esdmode3 & 0xFFFF) << 0)
  934. );
  935. break;
  936. case 2:
  937. ddr->ddr_sdram_mode_6 = (0
  938. | ((esdmode2 & 0xFFFF) << 16)
  939. | ((esdmode3 & 0xFFFF) << 0)
  940. );
  941. break;
  942. case 3:
  943. ddr->ddr_sdram_mode_8 = (0
  944. | ((esdmode2 & 0xFFFF) << 16)
  945. | ((esdmode3 & 0xFFFF) << 0)
  946. );
  947. break;
  948. }
  949. }
  950. debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
  951. ddr->ddr_sdram_mode_4);
  952. debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
  953. ddr->ddr_sdram_mode_6);
  954. debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
  955. ddr->ddr_sdram_mode_8);
  956. }
  957. }
  958. #elif defined(CONFIG_SYS_FSL_DDR3)
  959. /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
  960. static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
  961. fsl_ddr_cfg_regs_t *ddr,
  962. const memctl_options_t *popts,
  963. const common_timing_params_t *common_dimm,
  964. const unsigned int unq_mrs_en)
  965. {
  966. unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
  967. unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
  968. int i;
  969. unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
  970. unsigned int srt = 0; /* self-refresh temerature, normal range */
  971. unsigned int asr = 0; /* auto self-refresh disable */
  972. unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
  973. unsigned int pasr = 0; /* partial array self refresh disable */
  974. if (popts->rtt_override)
  975. rtt_wr = popts->rtt_wr_override_value;
  976. else
  977. rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
  978. if (common_dimm->extended_op_srt)
  979. srt = common_dimm->extended_op_srt;
  980. esdmode2 = (0
  981. | ((rtt_wr & 0x3) << 9)
  982. | ((srt & 0x1) << 7)
  983. | ((asr & 0x1) << 6)
  984. | ((cwl & 0x7) << 3)
  985. | ((pasr & 0x7) << 0));
  986. ddr->ddr_sdram_mode_2 = (0
  987. | ((esdmode2 & 0xFFFF) << 16)
  988. | ((esdmode3 & 0xFFFF) << 0)
  989. );
  990. debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
  991. if (unq_mrs_en) { /* unique mode registers are supported */
  992. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  993. if (popts->rtt_override)
  994. rtt_wr = popts->rtt_wr_override_value;
  995. else
  996. rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
  997. esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
  998. esdmode2 |= (rtt_wr & 0x3) << 9;
  999. switch (i) {
  1000. case 1:
  1001. ddr->ddr_sdram_mode_4 = (0
  1002. | ((esdmode2 & 0xFFFF) << 16)
  1003. | ((esdmode3 & 0xFFFF) << 0)
  1004. );
  1005. break;
  1006. case 2:
  1007. ddr->ddr_sdram_mode_6 = (0
  1008. | ((esdmode2 & 0xFFFF) << 16)
  1009. | ((esdmode3 & 0xFFFF) << 0)
  1010. );
  1011. break;
  1012. case 3:
  1013. ddr->ddr_sdram_mode_8 = (0
  1014. | ((esdmode2 & 0xFFFF) << 16)
  1015. | ((esdmode3 & 0xFFFF) << 0)
  1016. );
  1017. break;
  1018. }
  1019. }
  1020. debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
  1021. ddr->ddr_sdram_mode_4);
  1022. debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
  1023. ddr->ddr_sdram_mode_6);
  1024. debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
  1025. ddr->ddr_sdram_mode_8);
  1026. }
  1027. }
  1028. #else /* for DDR2 and DDR1 */
  1029. /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
  1030. static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
  1031. fsl_ddr_cfg_regs_t *ddr,
  1032. const memctl_options_t *popts,
  1033. const common_timing_params_t *common_dimm,
  1034. const unsigned int unq_mrs_en)
  1035. {
  1036. unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
  1037. unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
  1038. ddr->ddr_sdram_mode_2 = (0
  1039. | ((esdmode2 & 0xFFFF) << 16)
  1040. | ((esdmode3 & 0xFFFF) << 0)
  1041. );
  1042. debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
  1043. }
  1044. #endif
  1045. #ifdef CONFIG_SYS_FSL_DDR4
  1046. /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
  1047. static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
  1048. const memctl_options_t *popts,
  1049. const common_timing_params_t *common_dimm,
  1050. const unsigned int unq_mrs_en)
  1051. {
  1052. int i;
  1053. unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
  1054. unsigned short esdmode5; /* Extended SDRAM mode 5 */
  1055. int rtt_park = 0;
  1056. bool four_cs = false;
  1057. const unsigned int mclk_ps = get_memory_clk_period_ps(0);
  1058. #if CONFIG_CHIP_SELECTS_PER_CTRL == 4
  1059. if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
  1060. (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
  1061. (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
  1062. (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
  1063. four_cs = true;
  1064. #endif
  1065. if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
  1066. esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */
  1067. rtt_park = four_cs ? 0 : 1;
  1068. } else {
  1069. esdmode5 = 0x00000400; /* Data mask enabled */
  1070. }
  1071. /* set command/address parity latency */
  1072. if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
  1073. if (mclk_ps >= 935) {
  1074. /* for DDR4-1600/1866/2133 */
  1075. esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
  1076. } else if (mclk_ps >= 833) {
  1077. /* for DDR4-2400 */
  1078. esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
  1079. } else {
  1080. printf("parity: mclk_ps = %d not supported\n", mclk_ps);
  1081. }
  1082. }
  1083. ddr->ddr_sdram_mode_9 = (0
  1084. | ((esdmode4 & 0xffff) << 16)
  1085. | ((esdmode5 & 0xffff) << 0)
  1086. );
  1087. /* Normally only the first enabled CS use 0x500, others use 0x400
  1088. * But when four chip-selects are all enabled, all mode registers
  1089. * need 0x500 to park.
  1090. */
  1091. debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
  1092. if (unq_mrs_en) { /* unique mode registers are supported */
  1093. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  1094. if (!rtt_park &&
  1095. (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
  1096. esdmode5 |= 0x00000500; /* RTT_PARK */
  1097. rtt_park = four_cs ? 0 : 1;
  1098. } else {
  1099. esdmode5 = 0x00000400;
  1100. }
  1101. if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
  1102. if (mclk_ps >= 935) {
  1103. /* for DDR4-1600/1866/2133 */
  1104. esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
  1105. } else if (mclk_ps >= 833) {
  1106. /* for DDR4-2400 */
  1107. esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
  1108. } else {
  1109. printf("parity: mclk_ps = %d not supported\n",
  1110. mclk_ps);
  1111. }
  1112. }
  1113. switch (i) {
  1114. case 1:
  1115. ddr->ddr_sdram_mode_11 = (0
  1116. | ((esdmode4 & 0xFFFF) << 16)
  1117. | ((esdmode5 & 0xFFFF) << 0)
  1118. );
  1119. break;
  1120. case 2:
  1121. ddr->ddr_sdram_mode_13 = (0
  1122. | ((esdmode4 & 0xFFFF) << 16)
  1123. | ((esdmode5 & 0xFFFF) << 0)
  1124. );
  1125. break;
  1126. case 3:
  1127. ddr->ddr_sdram_mode_15 = (0
  1128. | ((esdmode4 & 0xFFFF) << 16)
  1129. | ((esdmode5 & 0xFFFF) << 0)
  1130. );
  1131. break;
  1132. }
  1133. }
  1134. debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
  1135. ddr->ddr_sdram_mode_11);
  1136. debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
  1137. ddr->ddr_sdram_mode_13);
  1138. debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
  1139. ddr->ddr_sdram_mode_15);
  1140. }
  1141. }
  1142. /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
  1143. static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
  1144. fsl_ddr_cfg_regs_t *ddr,
  1145. const memctl_options_t *popts,
  1146. const common_timing_params_t *common_dimm,
  1147. const unsigned int unq_mrs_en)
  1148. {
  1149. int i;
  1150. unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
  1151. unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
  1152. unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
  1153. esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
  1154. if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
  1155. esdmode6 |= 1 << 6; /* Range 2 */
  1156. ddr->ddr_sdram_mode_10 = (0
  1157. | ((esdmode6 & 0xffff) << 16)
  1158. | ((esdmode7 & 0xffff) << 0)
  1159. );
  1160. debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
  1161. if (unq_mrs_en) { /* unique mode registers are supported */
  1162. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  1163. switch (i) {
  1164. case 1:
  1165. ddr->ddr_sdram_mode_12 = (0
  1166. | ((esdmode6 & 0xFFFF) << 16)
  1167. | ((esdmode7 & 0xFFFF) << 0)
  1168. );
  1169. break;
  1170. case 2:
  1171. ddr->ddr_sdram_mode_14 = (0
  1172. | ((esdmode6 & 0xFFFF) << 16)
  1173. | ((esdmode7 & 0xFFFF) << 0)
  1174. );
  1175. break;
  1176. case 3:
  1177. ddr->ddr_sdram_mode_16 = (0
  1178. | ((esdmode6 & 0xFFFF) << 16)
  1179. | ((esdmode7 & 0xFFFF) << 0)
  1180. );
  1181. break;
  1182. }
  1183. }
  1184. debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
  1185. ddr->ddr_sdram_mode_12);
  1186. debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
  1187. ddr->ddr_sdram_mode_14);
  1188. debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
  1189. ddr->ddr_sdram_mode_16);
  1190. }
  1191. }
  1192. #endif
  1193. /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
  1194. static void set_ddr_sdram_interval(const unsigned int ctrl_num,
  1195. fsl_ddr_cfg_regs_t *ddr,
  1196. const memctl_options_t *popts,
  1197. const common_timing_params_t *common_dimm)
  1198. {
  1199. unsigned int refint; /* Refresh interval */
  1200. unsigned int bstopre; /* Precharge interval */
  1201. refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
  1202. bstopre = popts->bstopre;
  1203. /* refint field used 0x3FFF in earlier controllers */
  1204. ddr->ddr_sdram_interval = (0
  1205. | ((refint & 0xFFFF) << 16)
  1206. | ((bstopre & 0x3FFF) << 0)
  1207. );
  1208. debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
  1209. }
  1210. #ifdef CONFIG_SYS_FSL_DDR4
  1211. /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
  1212. static void set_ddr_sdram_mode(const unsigned int ctrl_num,
  1213. fsl_ddr_cfg_regs_t *ddr,
  1214. const memctl_options_t *popts,
  1215. const common_timing_params_t *common_dimm,
  1216. unsigned int cas_latency,
  1217. unsigned int additive_latency,
  1218. const unsigned int unq_mrs_en)
  1219. {
  1220. int i;
  1221. unsigned short esdmode; /* Extended SDRAM mode */
  1222. unsigned short sdmode; /* SDRAM mode */
  1223. /* Mode Register - MR1 */
  1224. unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
  1225. unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
  1226. unsigned int rtt;
  1227. unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
  1228. unsigned int al = 0; /* Posted CAS# additive latency (AL) */
  1229. unsigned int dic = 0; /* Output driver impedance, 40ohm */
  1230. unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
  1231. 0=Disable (Test/Debug) */
  1232. /* Mode Register - MR0 */
  1233. unsigned int wr = 0; /* Write Recovery */
  1234. unsigned int dll_rst; /* DLL Reset */
  1235. unsigned int mode; /* Normal=0 or Test=1 */
  1236. unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
  1237. /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
  1238. unsigned int bt;
  1239. unsigned int bl; /* BL: Burst Length */
  1240. unsigned int wr_mclk;
  1241. /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
  1242. static const u8 wr_table[] = {
  1243. 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
  1244. /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
  1245. static const u8 cas_latency_table[] = {
  1246. 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
  1247. 9, 9, 10, 10, 11, 11};
  1248. if (popts->rtt_override)
  1249. rtt = popts->rtt_override_value;
  1250. else
  1251. rtt = popts->cs_local_opts[0].odt_rtt_norm;
  1252. if (additive_latency == (cas_latency - 1))
  1253. al = 1;
  1254. if (additive_latency == (cas_latency - 2))
  1255. al = 2;
  1256. if (popts->quad_rank_present)
  1257. dic = 1; /* output driver impedance 240/7 ohm */
  1258. /*
  1259. * The esdmode value will also be used for writing
  1260. * MR1 during write leveling for DDR3, although the
  1261. * bits specifically related to the write leveling
  1262. * scheme will be handled automatically by the DDR
  1263. * controller. so we set the wrlvl_en = 0 here.
  1264. */
  1265. esdmode = (0
  1266. | ((qoff & 0x1) << 12)
  1267. | ((tdqs_en & 0x1) << 11)
  1268. | ((rtt & 0x7) << 8)
  1269. | ((wrlvl_en & 0x1) << 7)
  1270. | ((al & 0x3) << 3)
  1271. | ((dic & 0x3) << 1) /* DIC field is split */
  1272. | ((dll_en & 0x1) << 0)
  1273. );
  1274. /*
  1275. * DLL control for precharge PD
  1276. * 0=slow exit DLL off (tXPDLL)
  1277. * 1=fast exit DLL on (tXP)
  1278. */
  1279. wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
  1280. if (wr_mclk <= 24) {
  1281. wr = wr_table[wr_mclk - 10];
  1282. } else {
  1283. printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
  1284. wr_mclk);
  1285. }
  1286. dll_rst = 0; /* dll no reset */
  1287. mode = 0; /* normal mode */
  1288. /* look up table to get the cas latency bits */
  1289. if (cas_latency >= 9 && cas_latency <= 24)
  1290. caslat = cas_latency_table[cas_latency - 9];
  1291. else
  1292. printf("Error: unsupported cas latency for mode register\n");
  1293. bt = 0; /* Nibble sequential */
  1294. switch (popts->burst_length) {
  1295. case DDR_BL8:
  1296. bl = 0;
  1297. break;
  1298. case DDR_OTF:
  1299. bl = 1;
  1300. break;
  1301. case DDR_BC4:
  1302. bl = 2;
  1303. break;
  1304. default:
  1305. printf("Error: invalid burst length of %u specified. ",
  1306. popts->burst_length);
  1307. puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
  1308. bl = 1;
  1309. break;
  1310. }
  1311. sdmode = (0
  1312. | ((wr & 0x7) << 9)
  1313. | ((dll_rst & 0x1) << 8)
  1314. | ((mode & 0x1) << 7)
  1315. | (((caslat >> 1) & 0x7) << 4)
  1316. | ((bt & 0x1) << 3)
  1317. | ((caslat & 1) << 2)
  1318. | ((bl & 0x3) << 0)
  1319. );
  1320. ddr->ddr_sdram_mode = (0
  1321. | ((esdmode & 0xFFFF) << 16)
  1322. | ((sdmode & 0xFFFF) << 0)
  1323. );
  1324. debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
  1325. if (unq_mrs_en) { /* unique mode registers are supported */
  1326. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  1327. if (popts->rtt_override)
  1328. rtt = popts->rtt_override_value;
  1329. else
  1330. rtt = popts->cs_local_opts[i].odt_rtt_norm;
  1331. esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
  1332. esdmode |= (rtt & 0x7) << 8;
  1333. switch (i) {
  1334. case 1:
  1335. ddr->ddr_sdram_mode_3 = (0
  1336. | ((esdmode & 0xFFFF) << 16)
  1337. | ((sdmode & 0xFFFF) << 0)
  1338. );
  1339. break;
  1340. case 2:
  1341. ddr->ddr_sdram_mode_5 = (0
  1342. | ((esdmode & 0xFFFF) << 16)
  1343. | ((sdmode & 0xFFFF) << 0)
  1344. );
  1345. break;
  1346. case 3:
  1347. ddr->ddr_sdram_mode_7 = (0
  1348. | ((esdmode & 0xFFFF) << 16)
  1349. | ((sdmode & 0xFFFF) << 0)
  1350. );
  1351. break;
  1352. }
  1353. }
  1354. debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
  1355. ddr->ddr_sdram_mode_3);
  1356. debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
  1357. ddr->ddr_sdram_mode_5);
  1358. debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
  1359. ddr->ddr_sdram_mode_5);
  1360. }
  1361. }
  1362. #elif defined(CONFIG_SYS_FSL_DDR3)
  1363. /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
  1364. static void set_ddr_sdram_mode(const unsigned int ctrl_num,
  1365. fsl_ddr_cfg_regs_t *ddr,
  1366. const memctl_options_t *popts,
  1367. const common_timing_params_t *common_dimm,
  1368. unsigned int cas_latency,
  1369. unsigned int additive_latency,
  1370. const unsigned int unq_mrs_en)
  1371. {
  1372. int i;
  1373. unsigned short esdmode; /* Extended SDRAM mode */
  1374. unsigned short sdmode; /* SDRAM mode */
  1375. /* Mode Register - MR1 */
  1376. unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
  1377. unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
  1378. unsigned int rtt;
  1379. unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
  1380. unsigned int al = 0; /* Posted CAS# additive latency (AL) */
  1381. unsigned int dic = 0; /* Output driver impedance, 40ohm */
  1382. unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
  1383. 1=Disable (Test/Debug) */
  1384. /* Mode Register - MR0 */
  1385. unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
  1386. unsigned int wr = 0; /* Write Recovery */
  1387. unsigned int dll_rst; /* DLL Reset */
  1388. unsigned int mode; /* Normal=0 or Test=1 */
  1389. unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
  1390. /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
  1391. unsigned int bt;
  1392. unsigned int bl; /* BL: Burst Length */
  1393. unsigned int wr_mclk;
  1394. /*
  1395. * DDR_SDRAM_MODE doesn't support 9,11,13,15
  1396. * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
  1397. * for this table
  1398. */
  1399. static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
  1400. if (popts->rtt_override)
  1401. rtt = popts->rtt_override_value;
  1402. else
  1403. rtt = popts->cs_local_opts[0].odt_rtt_norm;
  1404. if (additive_latency == (cas_latency - 1))
  1405. al = 1;
  1406. if (additive_latency == (cas_latency - 2))
  1407. al = 2;
  1408. if (popts->quad_rank_present)
  1409. dic = 1; /* output driver impedance 240/7 ohm */
  1410. /*
  1411. * The esdmode value will also be used for writing
  1412. * MR1 during write leveling for DDR3, although the
  1413. * bits specifically related to the write leveling
  1414. * scheme will be handled automatically by the DDR
  1415. * controller. so we set the wrlvl_en = 0 here.
  1416. */
  1417. esdmode = (0
  1418. | ((qoff & 0x1) << 12)
  1419. | ((tdqs_en & 0x1) << 11)
  1420. | ((rtt & 0x4) << 7) /* rtt field is split */
  1421. | ((wrlvl_en & 0x1) << 7)
  1422. | ((rtt & 0x2) << 5) /* rtt field is split */
  1423. | ((dic & 0x2) << 4) /* DIC field is split */
  1424. | ((al & 0x3) << 3)
  1425. | ((rtt & 0x1) << 2) /* rtt field is split */
  1426. | ((dic & 0x1) << 1) /* DIC field is split */
  1427. | ((dll_en & 0x1) << 0)
  1428. );
  1429. /*
  1430. * DLL control for precharge PD
  1431. * 0=slow exit DLL off (tXPDLL)
  1432. * 1=fast exit DLL on (tXP)
  1433. */
  1434. dll_on = 1;
  1435. wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
  1436. if (wr_mclk <= 16) {
  1437. wr = wr_table[wr_mclk - 5];
  1438. } else {
  1439. printf("Error: unsupported write recovery for mode register "
  1440. "wr_mclk = %d\n", wr_mclk);
  1441. }
  1442. dll_rst = 0; /* dll no reset */
  1443. mode = 0; /* normal mode */
  1444. /* look up table to get the cas latency bits */
  1445. if (cas_latency >= 5 && cas_latency <= 16) {
  1446. unsigned char cas_latency_table[] = {
  1447. 0x2, /* 5 clocks */
  1448. 0x4, /* 6 clocks */
  1449. 0x6, /* 7 clocks */
  1450. 0x8, /* 8 clocks */
  1451. 0xa, /* 9 clocks */
  1452. 0xc, /* 10 clocks */
  1453. 0xe, /* 11 clocks */
  1454. 0x1, /* 12 clocks */
  1455. 0x3, /* 13 clocks */
  1456. 0x5, /* 14 clocks */
  1457. 0x7, /* 15 clocks */
  1458. 0x9, /* 16 clocks */
  1459. };
  1460. caslat = cas_latency_table[cas_latency - 5];
  1461. } else {
  1462. printf("Error: unsupported cas latency for mode register\n");
  1463. }
  1464. bt = 0; /* Nibble sequential */
  1465. switch (popts->burst_length) {
  1466. case DDR_BL8:
  1467. bl = 0;
  1468. break;
  1469. case DDR_OTF:
  1470. bl = 1;
  1471. break;
  1472. case DDR_BC4:
  1473. bl = 2;
  1474. break;
  1475. default:
  1476. printf("Error: invalid burst length of %u specified. "
  1477. " Defaulting to on-the-fly BC4 or BL8 beats.\n",
  1478. popts->burst_length);
  1479. bl = 1;
  1480. break;
  1481. }
  1482. sdmode = (0
  1483. | ((dll_on & 0x1) << 12)
  1484. | ((wr & 0x7) << 9)
  1485. | ((dll_rst & 0x1) << 8)
  1486. | ((mode & 0x1) << 7)
  1487. | (((caslat >> 1) & 0x7) << 4)
  1488. | ((bt & 0x1) << 3)
  1489. | ((caslat & 1) << 2)
  1490. | ((bl & 0x3) << 0)
  1491. );
  1492. ddr->ddr_sdram_mode = (0
  1493. | ((esdmode & 0xFFFF) << 16)
  1494. | ((sdmode & 0xFFFF) << 0)
  1495. );
  1496. debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
  1497. if (unq_mrs_en) { /* unique mode registers are supported */
  1498. for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  1499. if (popts->rtt_override)
  1500. rtt = popts->rtt_override_value;
  1501. else
  1502. rtt = popts->cs_local_opts[i].odt_rtt_norm;
  1503. esdmode &= 0xFDBB; /* clear bit 9,6,2 */
  1504. esdmode |= (0
  1505. | ((rtt & 0x4) << 7) /* rtt field is split */
  1506. | ((rtt & 0x2) << 5) /* rtt field is split */
  1507. | ((rtt & 0x1) << 2) /* rtt field is split */
  1508. );
  1509. switch (i) {
  1510. case 1:
  1511. ddr->ddr_sdram_mode_3 = (0
  1512. | ((esdmode & 0xFFFF) << 16)
  1513. | ((sdmode & 0xFFFF) << 0)
  1514. );
  1515. break;
  1516. case 2:
  1517. ddr->ddr_sdram_mode_5 = (0
  1518. | ((esdmode & 0xFFFF) << 16)
  1519. | ((sdmode & 0xFFFF) << 0)
  1520. );
  1521. break;
  1522. case 3:
  1523. ddr->ddr_sdram_mode_7 = (0
  1524. | ((esdmode & 0xFFFF) << 16)
  1525. | ((sdmode & 0xFFFF) << 0)
  1526. );
  1527. break;
  1528. }
  1529. }
  1530. debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
  1531. ddr->ddr_sdram_mode_3);
  1532. debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
  1533. ddr->ddr_sdram_mode_5);
  1534. debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
  1535. ddr->ddr_sdram_mode_5);
  1536. }
  1537. }
  1538. #else /* !CONFIG_SYS_FSL_DDR3 */
  1539. /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
  1540. static void set_ddr_sdram_mode(const unsigned int ctrl_num,
  1541. fsl_ddr_cfg_regs_t *ddr,
  1542. const memctl_options_t *popts,
  1543. const common_timing_params_t *common_dimm,
  1544. unsigned int cas_latency,
  1545. unsigned int additive_latency,
  1546. const unsigned int unq_mrs_en)
  1547. {
  1548. unsigned short esdmode; /* Extended SDRAM mode */
  1549. unsigned short sdmode; /* SDRAM mode */
  1550. /*
  1551. * FIXME: This ought to be pre-calculated in a
  1552. * technology-specific routine,
  1553. * e.g. compute_DDR2_mode_register(), and then the
  1554. * sdmode and esdmode passed in as part of common_dimm.
  1555. */
  1556. /* Extended Mode Register */
  1557. unsigned int mrs = 0; /* Mode Register Set */
  1558. unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
  1559. unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
  1560. unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
  1561. unsigned int ocd = 0; /* 0x0=OCD not supported,
  1562. 0x7=OCD default state */
  1563. unsigned int rtt;
  1564. unsigned int al; /* Posted CAS# additive latency (AL) */
  1565. unsigned int ods = 0; /* Output Drive Strength:
  1566. 0 = Full strength (18ohm)
  1567. 1 = Reduced strength (4ohm) */
  1568. unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
  1569. 1=Disable (Test/Debug) */
  1570. /* Mode Register (MR) */
  1571. unsigned int mr; /* Mode Register Definition */
  1572. unsigned int pd; /* Power-Down Mode */
  1573. unsigned int wr; /* Write Recovery */
  1574. unsigned int dll_res; /* DLL Reset */
  1575. unsigned int mode; /* Normal=0 or Test=1 */
  1576. unsigned int caslat = 0;/* CAS# latency */
  1577. /* BT: Burst Type (0=Sequential, 1=Interleaved) */
  1578. unsigned int bt;
  1579. unsigned int bl; /* BL: Burst Length */
  1580. dqs_en = !popts->dqs_config;
  1581. rtt = fsl_ddr_get_rtt();
  1582. al = additive_latency;
  1583. esdmode = (0
  1584. | ((mrs & 0x3) << 14)
  1585. | ((outputs & 0x1) << 12)
  1586. | ((rdqs_en & 0x1) << 11)
  1587. | ((dqs_en & 0x1) << 10)
  1588. | ((ocd & 0x7) << 7)
  1589. | ((rtt & 0x2) << 5) /* rtt field is split */
  1590. | ((al & 0x7) << 3)
  1591. | ((rtt & 0x1) << 2) /* rtt field is split */
  1592. | ((ods & 0x1) << 1)
  1593. | ((dll_en & 0x1) << 0)
  1594. );
  1595. mr = 0; /* FIXME: CHECKME */
  1596. /*
  1597. * 0 = Fast Exit (Normal)
  1598. * 1 = Slow Exit (Low Power)
  1599. */
  1600. pd = 0;
  1601. #if defined(CONFIG_SYS_FSL_DDR1)
  1602. wr = 0; /* Historical */
  1603. #elif defined(CONFIG_SYS_FSL_DDR2)
  1604. wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
  1605. #endif
  1606. dll_res = 0;
  1607. mode = 0;
  1608. #if defined(CONFIG_SYS_FSL_DDR1)
  1609. if (1 <= cas_latency && cas_latency <= 4) {
  1610. unsigned char mode_caslat_table[4] = {
  1611. 0x5, /* 1.5 clocks */
  1612. 0x2, /* 2.0 clocks */
  1613. 0x6, /* 2.5 clocks */
  1614. 0x3 /* 3.0 clocks */
  1615. };
  1616. caslat = mode_caslat_table[cas_latency - 1];
  1617. } else {
  1618. printf("Warning: unknown cas_latency %d\n", cas_latency);
  1619. }
  1620. #elif defined(CONFIG_SYS_FSL_DDR2)
  1621. caslat = cas_latency;
  1622. #endif
  1623. bt = 0;
  1624. switch (popts->burst_length) {
  1625. case DDR_BL4:
  1626. bl = 2;
  1627. break;
  1628. case DDR_BL8:
  1629. bl = 3;
  1630. break;
  1631. default:
  1632. printf("Error: invalid burst length of %u specified. "
  1633. " Defaulting to 4 beats.\n",
  1634. popts->burst_length);
  1635. bl = 2;
  1636. break;
  1637. }
  1638. sdmode = (0
  1639. | ((mr & 0x3) << 14)
  1640. | ((pd & 0x1) << 12)
  1641. | ((wr & 0x7) << 9)
  1642. | ((dll_res & 0x1) << 8)
  1643. | ((mode & 0x1) << 7)
  1644. | ((caslat & 0x7) << 4)
  1645. | ((bt & 0x1) << 3)
  1646. | ((bl & 0x7) << 0)
  1647. );
  1648. ddr->ddr_sdram_mode = (0
  1649. | ((esdmode & 0xFFFF) << 16)
  1650. | ((sdmode & 0xFFFF) << 0)
  1651. );
  1652. debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
  1653. }
  1654. #endif
  1655. /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
  1656. static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
  1657. {
  1658. unsigned int init_value; /* Initialization value */
  1659. #ifdef CONFIG_MEM_INIT_VALUE
  1660. init_value = CONFIG_MEM_INIT_VALUE;
  1661. #else
  1662. init_value = 0xDEADBEEF;
  1663. #endif
  1664. ddr->ddr_data_init = init_value;
  1665. }
  1666. /*
  1667. * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
  1668. * The old controller on the 8540/60 doesn't have this register.
  1669. * Hope it's OK to set it (to 0) anyway.
  1670. */
  1671. static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
  1672. const memctl_options_t *popts)
  1673. {
  1674. unsigned int clk_adjust; /* Clock adjust */
  1675. unsigned int ss_en = 0; /* Source synchronous enable */
  1676. #if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
  1677. /* Per FSL Application Note: AN2805 */
  1678. ss_en = 1;
  1679. #endif
  1680. clk_adjust = popts->clk_adjust;
  1681. ddr->ddr_sdram_clk_cntl = (0
  1682. | ((ss_en & 0x1) << 31)
  1683. | ((clk_adjust & 0xF) << 23)
  1684. );
  1685. debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
  1686. }
  1687. /* DDR Initialization Address (DDR_INIT_ADDR) */
  1688. static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
  1689. {
  1690. unsigned int init_addr = 0; /* Initialization address */
  1691. ddr->ddr_init_addr = init_addr;
  1692. }
  1693. /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
  1694. static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
  1695. {
  1696. unsigned int uia = 0; /* Use initialization address */
  1697. unsigned int init_ext_addr = 0; /* Initialization address */
  1698. ddr->ddr_init_ext_addr = (0
  1699. | ((uia & 0x1) << 31)
  1700. | (init_ext_addr & 0xF)
  1701. );
  1702. }
  1703. /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
  1704. static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
  1705. const memctl_options_t *popts)
  1706. {
  1707. unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
  1708. unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
  1709. unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
  1710. unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
  1711. unsigned int trwt_mclk = 0; /* ext_rwt */
  1712. unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
  1713. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  1714. if (popts->burst_length == DDR_BL8) {
  1715. /* We set BL/2 for fixed BL8 */
  1716. rrt = 0; /* BL/2 clocks */
  1717. wwt = 0; /* BL/2 clocks */
  1718. } else {
  1719. /* We need to set BL/2 + 2 to BC4 and OTF */
  1720. rrt = 2; /* BL/2 + 2 clocks */
  1721. wwt = 2; /* BL/2 + 2 clocks */
  1722. }
  1723. #endif
  1724. #ifdef CONFIG_SYS_FSL_DDR4
  1725. dll_lock = 2; /* tDLLK = 1024 clocks */
  1726. #elif defined(CONFIG_SYS_FSL_DDR3)
  1727. dll_lock = 1; /* tDLLK = 512 clocks from spec */
  1728. #endif
  1729. if (popts->trwt_override)
  1730. trwt_mclk = popts->trwt;
  1731. ddr->timing_cfg_4 = (0
  1732. | ((rwt & 0xf) << 28)
  1733. | ((wrt & 0xf) << 24)
  1734. | ((rrt & 0xf) << 20)
  1735. | ((wwt & 0xf) << 16)
  1736. | ((trwt_mclk & 0xc) << 12)
  1737. | (dll_lock & 0x3)
  1738. );
  1739. debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
  1740. }
  1741. /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
  1742. static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
  1743. {
  1744. unsigned int rodt_on = 0; /* Read to ODT on */
  1745. unsigned int rodt_off = 0; /* Read to ODT off */
  1746. unsigned int wodt_on = 0; /* Write to ODT on */
  1747. unsigned int wodt_off = 0; /* Write to ODT off */
  1748. #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  1749. unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
  1750. ((ddr->timing_cfg_2 & 0x00040000) >> 14);
  1751. /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
  1752. if (cas_latency >= wr_lat)
  1753. rodt_on = cas_latency - wr_lat + 1;
  1754. rodt_off = 4; /* 4 clocks */
  1755. wodt_on = 1; /* 1 clocks */
  1756. wodt_off = 4; /* 4 clocks */
  1757. #endif
  1758. ddr->timing_cfg_5 = (0
  1759. | ((rodt_on & 0x1f) << 24)
  1760. | ((rodt_off & 0x7) << 20)
  1761. | ((wodt_on & 0x1f) << 12)
  1762. | ((wodt_off & 0x7) << 8)
  1763. );
  1764. debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
  1765. }
  1766. #ifdef CONFIG_SYS_FSL_DDR4
  1767. static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
  1768. {
  1769. unsigned int hs_caslat = 0;
  1770. unsigned int hs_wrlat = 0;
  1771. unsigned int hs_wrrec = 0;
  1772. unsigned int hs_clkadj = 0;
  1773. unsigned int hs_wrlvl_start = 0;
  1774. ddr->timing_cfg_6 = (0
  1775. | ((hs_caslat & 0x1f) << 24)
  1776. | ((hs_wrlat & 0x1f) << 19)
  1777. | ((hs_wrrec & 0x1f) << 12)
  1778. | ((hs_clkadj & 0x1f) << 6)
  1779. | ((hs_wrlvl_start & 0x1f) << 0)
  1780. );
  1781. debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
  1782. }
  1783. static void set_timing_cfg_7(const unsigned int ctrl_num,
  1784. fsl_ddr_cfg_regs_t *ddr,
  1785. const common_timing_params_t *common_dimm)
  1786. {
  1787. unsigned int txpr, tcksre, tcksrx;
  1788. unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
  1789. const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  1790. txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
  1791. tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
  1792. tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
  1793. if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
  1794. if (mclk_ps >= 935) {
  1795. /* parity latency 4 clocks in case of 1600/1866/2133 */
  1796. par_lat = 4;
  1797. } else if (mclk_ps >= 833) {
  1798. /* parity latency 5 clocks for DDR4-2400 */
  1799. par_lat = 5;
  1800. } else {
  1801. printf("parity: mclk_ps = %d not supported\n", mclk_ps);
  1802. }
  1803. }
  1804. cs_to_cmd = 0;
  1805. if (txpr <= 200)
  1806. cke_rst = 0;
  1807. else if (txpr <= 256)
  1808. cke_rst = 1;
  1809. else if (txpr <= 512)
  1810. cke_rst = 2;
  1811. else
  1812. cke_rst = 3;
  1813. if (tcksre <= 19)
  1814. cksre = tcksre - 5;
  1815. else
  1816. cksre = 15;
  1817. if (tcksrx <= 19)
  1818. cksrx = tcksrx - 5;
  1819. else
  1820. cksrx = 15;
  1821. ddr->timing_cfg_7 = (0
  1822. | ((cke_rst & 0x3) << 28)
  1823. | ((cksre & 0xf) << 24)
  1824. | ((cksrx & 0xf) << 20)
  1825. | ((par_lat & 0xf) << 16)
  1826. | ((cs_to_cmd & 0xf) << 4)
  1827. );
  1828. debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
  1829. }
  1830. static void set_timing_cfg_8(const unsigned int ctrl_num,
  1831. fsl_ddr_cfg_regs_t *ddr,
  1832. const memctl_options_t *popts,
  1833. const common_timing_params_t *common_dimm,
  1834. unsigned int cas_latency)
  1835. {
  1836. unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
  1837. unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
  1838. unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
  1839. unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
  1840. ((ddr->timing_cfg_2 & 0x00040000) >> 14);
  1841. rwt_bg = cas_latency + 2 + 4 - wr_lat;
  1842. if (rwt_bg < tccdl)
  1843. rwt_bg = tccdl - rwt_bg;
  1844. else
  1845. rwt_bg = 0;
  1846. wrt_bg = wr_lat + 4 + 1 - cas_latency;
  1847. if (wrt_bg < tccdl)
  1848. wrt_bg = tccdl - wrt_bg;
  1849. else
  1850. wrt_bg = 0;
  1851. if (popts->burst_length == DDR_BL8) {
  1852. rrt_bg = tccdl - 4;
  1853. wwt_bg = tccdl - 4;
  1854. } else {
  1855. rrt_bg = tccdl - 2;
  1856. wwt_bg = tccdl - 2;
  1857. }
  1858. acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
  1859. wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
  1860. if (popts->otf_burst_chop_en)
  1861. wrtord_bg += 2;
  1862. pre_all_rec = 0;
  1863. ddr->timing_cfg_8 = (0
  1864. | ((rwt_bg & 0xf) << 28)
  1865. | ((wrt_bg & 0xf) << 24)
  1866. | ((rrt_bg & 0xf) << 20)
  1867. | ((wwt_bg & 0xf) << 16)
  1868. | ((acttoact_bg & 0xf) << 12)
  1869. | ((wrtord_bg & 0xf) << 8)
  1870. | ((pre_all_rec & 0x1f) << 0)
  1871. );
  1872. debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
  1873. }
  1874. static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
  1875. {
  1876. ddr->timing_cfg_9 = 0;
  1877. debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
  1878. }
  1879. /* This function needs to be called after set_ddr_sdram_cfg() is called */
  1880. static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
  1881. const dimm_params_t *dimm_params)
  1882. {
  1883. unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
  1884. int i;
  1885. for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  1886. if (dimm_params[i].n_ranks)
  1887. break;
  1888. }
  1889. if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
  1890. puts("DDR error: no DIMM found!\n");
  1891. return;
  1892. }
  1893. ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
  1894. ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
  1895. ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
  1896. ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
  1897. ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
  1898. ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
  1899. ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
  1900. ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
  1901. ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
  1902. ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
  1903. ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
  1904. ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
  1905. ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
  1906. ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
  1907. ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
  1908. /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
  1909. ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
  1910. ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
  1911. (acc_ecc_en ? 0 :
  1912. (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
  1913. dimm_params[i].dq_mapping_ors;
  1914. debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
  1915. debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
  1916. debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
  1917. debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
  1918. }
  1919. static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
  1920. const memctl_options_t *popts)
  1921. {
  1922. int rd_pre;
  1923. rd_pre = popts->quad_rank_present ? 1 : 0;
  1924. ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
  1925. debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
  1926. }
  1927. #endif /* CONFIG_SYS_FSL_DDR4 */
  1928. /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
  1929. static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
  1930. {
  1931. unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
  1932. /* Normal Operation Full Calibration Time (tZQoper) */
  1933. unsigned int zqoper = 0;
  1934. /* Normal Operation Short Calibration Time (tZQCS) */
  1935. unsigned int zqcs = 0;
  1936. #ifdef CONFIG_SYS_FSL_DDR4
  1937. unsigned int zqcs_init;
  1938. #endif
  1939. if (zq_en) {
  1940. #ifdef CONFIG_SYS_FSL_DDR4
  1941. zqinit = 10; /* 1024 clocks */
  1942. zqoper = 9; /* 512 clocks */
  1943. zqcs = 7; /* 128 clocks */
  1944. zqcs_init = 5; /* 1024 refresh sequences */
  1945. #else
  1946. zqinit = 9; /* 512 clocks */
  1947. zqoper = 8; /* 256 clocks */
  1948. zqcs = 6; /* 64 clocks */
  1949. #endif
  1950. }
  1951. ddr->ddr_zq_cntl = (0
  1952. | ((zq_en & 0x1) << 31)
  1953. | ((zqinit & 0xF) << 24)
  1954. | ((zqoper & 0xF) << 16)
  1955. | ((zqcs & 0xF) << 8)
  1956. #ifdef CONFIG_SYS_FSL_DDR4
  1957. | ((zqcs_init & 0xF) << 0)
  1958. #endif
  1959. );
  1960. debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
  1961. }
  1962. /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
  1963. static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
  1964. const memctl_options_t *popts)
  1965. {
  1966. /*
  1967. * First DQS pulse rising edge after margining mode
  1968. * is programmed (tWL_MRD)
  1969. */
  1970. unsigned int wrlvl_mrd = 0;
  1971. /* ODT delay after margining mode is programmed (tWL_ODTEN) */
  1972. unsigned int wrlvl_odten = 0;
  1973. /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
  1974. unsigned int wrlvl_dqsen = 0;
  1975. /* WRLVL_SMPL: Write leveling sample time */
  1976. unsigned int wrlvl_smpl = 0;
  1977. /* WRLVL_WLR: Write leveling repeition time */
  1978. unsigned int wrlvl_wlr = 0;
  1979. /* WRLVL_START: Write leveling start time */
  1980. unsigned int wrlvl_start = 0;
  1981. /* suggest enable write leveling for DDR3 due to fly-by topology */
  1982. if (wrlvl_en) {
  1983. /* tWL_MRD min = 40 nCK, we set it 64 */
  1984. wrlvl_mrd = 0x6;
  1985. /* tWL_ODTEN 128 */
  1986. wrlvl_odten = 0x7;
  1987. /* tWL_DQSEN min = 25 nCK, we set it 32 */
  1988. wrlvl_dqsen = 0x5;
  1989. /*
  1990. * Write leveling sample time at least need 6 clocks
  1991. * higher than tWLO to allow enough time for progagation
  1992. * delay and sampling the prime data bits.
  1993. */
  1994. wrlvl_smpl = 0xf;
  1995. /*
  1996. * Write leveling repetition time
  1997. * at least tWLO + 6 clocks clocks
  1998. * we set it 64
  1999. */
  2000. wrlvl_wlr = 0x6;
  2001. /*
  2002. * Write leveling start time
  2003. * The value use for the DQS_ADJUST for the first sample
  2004. * when write leveling is enabled. It probably needs to be
  2005. * overriden per platform.
  2006. */
  2007. wrlvl_start = 0x8;
  2008. /*
  2009. * Override the write leveling sample and start time
  2010. * according to specific board
  2011. */
  2012. if (popts->wrlvl_override) {
  2013. wrlvl_smpl = popts->wrlvl_sample;
  2014. wrlvl_start = popts->wrlvl_start;
  2015. }
  2016. }
  2017. ddr->ddr_wrlvl_cntl = (0
  2018. | ((wrlvl_en & 0x1) << 31)
  2019. | ((wrlvl_mrd & 0x7) << 24)
  2020. | ((wrlvl_odten & 0x7) << 20)
  2021. | ((wrlvl_dqsen & 0x7) << 16)
  2022. | ((wrlvl_smpl & 0xf) << 12)
  2023. | ((wrlvl_wlr & 0x7) << 8)
  2024. | ((wrlvl_start & 0x1F) << 0)
  2025. );
  2026. debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
  2027. ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
  2028. debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
  2029. ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
  2030. debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
  2031. }
  2032. /* DDR Self Refresh Counter (DDR_SR_CNTR) */
  2033. static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
  2034. {
  2035. /* Self Refresh Idle Threshold */
  2036. ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
  2037. }
  2038. static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
  2039. {
  2040. if (popts->addr_hash) {
  2041. ddr->ddr_eor = 0x40000000; /* address hash enable */
  2042. puts("Address hashing enabled.\n");
  2043. }
  2044. }
  2045. static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
  2046. {
  2047. ddr->ddr_cdr1 = popts->ddr_cdr1;
  2048. debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
  2049. }
  2050. static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
  2051. {
  2052. ddr->ddr_cdr2 = popts->ddr_cdr2;
  2053. debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
  2054. }
  2055. unsigned int
  2056. check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
  2057. {
  2058. unsigned int res = 0;
  2059. /*
  2060. * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
  2061. * not set at the same time.
  2062. */
  2063. if (ddr->ddr_sdram_cfg & 0x10000000
  2064. && ddr->ddr_sdram_cfg & 0x00008000) {
  2065. printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
  2066. " should not be set at the same time.\n");
  2067. res++;
  2068. }
  2069. return res;
  2070. }
  2071. unsigned int
  2072. compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
  2073. const memctl_options_t *popts,
  2074. fsl_ddr_cfg_regs_t *ddr,
  2075. const common_timing_params_t *common_dimm,
  2076. const dimm_params_t *dimm_params,
  2077. unsigned int dbw_cap_adj,
  2078. unsigned int size_only)
  2079. {
  2080. unsigned int i;
  2081. unsigned int cas_latency;
  2082. unsigned int additive_latency;
  2083. unsigned int sr_it;
  2084. unsigned int zq_en;
  2085. unsigned int wrlvl_en;
  2086. unsigned int ip_rev = 0;
  2087. unsigned int unq_mrs_en = 0;
  2088. int cs_en = 1;
  2089. memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
  2090. if (common_dimm == NULL) {
  2091. printf("Error: subset DIMM params struct null pointer\n");
  2092. return 1;
  2093. }
  2094. /*
  2095. * Process overrides first.
  2096. *
  2097. * FIXME: somehow add dereated caslat to this
  2098. */
  2099. cas_latency = (popts->cas_latency_override)
  2100. ? popts->cas_latency_override_value
  2101. : common_dimm->lowest_common_spd_caslat;
  2102. additive_latency = (popts->additive_latency_override)
  2103. ? popts->additive_latency_override_value
  2104. : common_dimm->additive_latency;
  2105. sr_it = (popts->auto_self_refresh_en)
  2106. ? popts->sr_it
  2107. : 0;
  2108. /* ZQ calibration */
  2109. zq_en = (popts->zq_en) ? 1 : 0;
  2110. /* write leveling */
  2111. wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
  2112. /* Chip Select Memory Bounds (CSn_BNDS) */
  2113. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  2114. unsigned long long ea, sa;
  2115. unsigned int cs_per_dimm
  2116. = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
  2117. unsigned int dimm_number
  2118. = i / cs_per_dimm;
  2119. unsigned long long rank_density
  2120. = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
  2121. if (dimm_params[dimm_number].n_ranks == 0) {
  2122. debug("Skipping setup of CS%u "
  2123. "because n_ranks on DIMM %u is 0\n", i, dimm_number);
  2124. continue;
  2125. }
  2126. if (popts->memctl_interleaving) {
  2127. switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
  2128. case FSL_DDR_CS0_CS1_CS2_CS3:
  2129. break;
  2130. case FSL_DDR_CS0_CS1:
  2131. case FSL_DDR_CS0_CS1_AND_CS2_CS3:
  2132. if (i > 1)
  2133. cs_en = 0;
  2134. break;
  2135. case FSL_DDR_CS2_CS3:
  2136. default:
  2137. if (i > 0)
  2138. cs_en = 0;
  2139. break;
  2140. }
  2141. sa = common_dimm->base_address;
  2142. ea = sa + common_dimm->total_mem - 1;
  2143. } else if (!popts->memctl_interleaving) {
  2144. /*
  2145. * If memory interleaving between controllers is NOT
  2146. * enabled, the starting address for each memory
  2147. * controller is distinct. However, because rank
  2148. * interleaving is enabled, the starting and ending
  2149. * addresses of the total memory on that memory
  2150. * controller needs to be programmed into its
  2151. * respective CS0_BNDS.
  2152. */
  2153. switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
  2154. case FSL_DDR_CS0_CS1_CS2_CS3:
  2155. sa = common_dimm->base_address;
  2156. ea = sa + common_dimm->total_mem - 1;
  2157. break;
  2158. case FSL_DDR_CS0_CS1_AND_CS2_CS3:
  2159. if ((i >= 2) && (dimm_number == 0)) {
  2160. sa = dimm_params[dimm_number].base_address +
  2161. 2 * rank_density;
  2162. ea = sa + 2 * rank_density - 1;
  2163. } else {
  2164. sa = dimm_params[dimm_number].base_address;
  2165. ea = sa + 2 * rank_density - 1;
  2166. }
  2167. break;
  2168. case FSL_DDR_CS0_CS1:
  2169. if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
  2170. sa = dimm_params[dimm_number].base_address;
  2171. ea = sa + rank_density - 1;
  2172. if (i != 1)
  2173. sa += (i % cs_per_dimm) * rank_density;
  2174. ea += (i % cs_per_dimm) * rank_density;
  2175. } else {
  2176. sa = 0;
  2177. ea = 0;
  2178. }
  2179. if (i == 0)
  2180. ea += rank_density;
  2181. break;
  2182. case FSL_DDR_CS2_CS3:
  2183. if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
  2184. sa = dimm_params[dimm_number].base_address;
  2185. ea = sa + rank_density - 1;
  2186. if (i != 3)
  2187. sa += (i % cs_per_dimm) * rank_density;
  2188. ea += (i % cs_per_dimm) * rank_density;
  2189. } else {
  2190. sa = 0;
  2191. ea = 0;
  2192. }
  2193. if (i == 2)
  2194. ea += (rank_density >> dbw_cap_adj);
  2195. break;
  2196. default: /* No bank(chip-select) interleaving */
  2197. sa = dimm_params[dimm_number].base_address;
  2198. ea = sa + rank_density - 1;
  2199. if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
  2200. sa += (i % cs_per_dimm) * rank_density;
  2201. ea += (i % cs_per_dimm) * rank_density;
  2202. } else {
  2203. sa = 0;
  2204. ea = 0;
  2205. }
  2206. break;
  2207. }
  2208. }
  2209. sa >>= 24;
  2210. ea >>= 24;
  2211. if (cs_en) {
  2212. ddr->cs[i].bnds = (0
  2213. | ((sa & 0xffff) << 16) /* starting address */
  2214. | ((ea & 0xffff) << 0) /* ending address */
  2215. );
  2216. } else {
  2217. /* setting bnds to 0xffffffff for inactive CS */
  2218. ddr->cs[i].bnds = 0xffffffff;
  2219. }
  2220. debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
  2221. set_csn_config(dimm_number, i, ddr, popts, dimm_params);
  2222. set_csn_config_2(i, ddr);
  2223. }
  2224. /*
  2225. * In the case we only need to compute the ddr sdram size, we only need
  2226. * to set csn registers, so return from here.
  2227. */
  2228. if (size_only)
  2229. return 0;
  2230. set_ddr_eor(ddr, popts);
  2231. #if !defined(CONFIG_SYS_FSL_DDR1)
  2232. set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
  2233. #endif
  2234. set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
  2235. additive_latency);
  2236. set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
  2237. set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
  2238. cas_latency, additive_latency);
  2239. set_ddr_cdr1(ddr, popts);
  2240. set_ddr_cdr2(ddr, popts);
  2241. set_ddr_sdram_cfg(ddr, popts, common_dimm);
  2242. ip_rev = fsl_ddr_get_version(ctrl_num);
  2243. if (ip_rev > 0x40400)
  2244. unq_mrs_en = 1;
  2245. if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
  2246. ddr->debug[18] = popts->cswl_override;
  2247. set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
  2248. set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
  2249. cas_latency, additive_latency, unq_mrs_en);
  2250. set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
  2251. #ifdef CONFIG_SYS_FSL_DDR4
  2252. set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
  2253. set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
  2254. #endif
  2255. set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
  2256. set_ddr_data_init(ddr);
  2257. set_ddr_sdram_clk_cntl(ddr, popts);
  2258. set_ddr_init_addr(ddr);
  2259. set_ddr_init_ext_addr(ddr);
  2260. set_timing_cfg_4(ddr, popts);
  2261. set_timing_cfg_5(ddr, cas_latency);
  2262. #ifdef CONFIG_SYS_FSL_DDR4
  2263. set_ddr_sdram_cfg_3(ddr, popts);
  2264. set_timing_cfg_6(ddr);
  2265. set_timing_cfg_7(ctrl_num, ddr, common_dimm);
  2266. set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
  2267. set_timing_cfg_9(ddr);
  2268. set_ddr_dq_mapping(ddr, dimm_params);
  2269. #endif
  2270. set_ddr_zq_cntl(ddr, zq_en);
  2271. set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
  2272. set_ddr_sr_cntr(ddr, sr_it);
  2273. set_ddr_sdram_rcw(ddr, popts, common_dimm);
  2274. #ifdef CONFIG_SYS_FSL_DDR_EMU
  2275. /* disble DDR training for emulator */
  2276. ddr->debug[2] = 0x00000400;
  2277. ddr->debug[4] = 0xff800800;
  2278. ddr->debug[5] = 0x08000800;
  2279. ddr->debug[6] = 0x08000800;
  2280. ddr->debug[7] = 0x08000800;
  2281. ddr->debug[8] = 0x08000800;
  2282. #endif
  2283. #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
  2284. if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
  2285. ddr->debug[2] |= 0x00000200; /* set bit 22 */
  2286. #endif
  2287. return check_fsl_memctl_config_regs(ddr);
  2288. }