ls1043ardb.c 2.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135
  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <asm/arch/soc.h>
  12. #include <hwconfig.h>
  13. #include <ahci.h>
  14. #include <scsi.h>
  15. #include <fm_eth.h>
  16. #include <fsl_csu.h>
  17. #include <fsl_esdhc.h>
  18. #include <fsl_ifc.h>
  19. #include "cpld.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. int checkboard(void)
  22. {
  23. static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
  24. u8 cfg_rcw_src1, cfg_rcw_src2;
  25. u32 cfg_rcw_src;
  26. u32 sd1refclk_sel;
  27. printf("Board: LS1043ARDB, boot from ");
  28. cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
  29. cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
  30. cpld_rev_bit(&cfg_rcw_src1);
  31. cfg_rcw_src = cfg_rcw_src1;
  32. cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
  33. if (cfg_rcw_src == 0x25)
  34. printf("vBank %d\n", CPLD_READ(vbank));
  35. else if (cfg_rcw_src == 0x106)
  36. puts("NAND\n");
  37. else
  38. printf("Invalid setting of SW4\n");
  39. printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
  40. CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
  41. puts("SERDES Reference Clocks:\n");
  42. sd1refclk_sel = CPLD_READ(sd1refclk_sel);
  43. printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
  44. return 0;
  45. }
  46. int dram_init(void)
  47. {
  48. gd->ram_size = initdram(0);
  49. return 0;
  50. }
  51. int board_early_init_f(void)
  52. {
  53. fsl_lsch2_early_init_f();
  54. return 0;
  55. }
  56. int board_init(void)
  57. {
  58. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  59. /*
  60. * Set CCI-400 control override register to enable barrier
  61. * transaction
  62. */
  63. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  64. #ifdef CONFIG_FSL_IFC
  65. init_final_memctl_regs();
  66. #endif
  67. #ifdef CONFIG_ENV_IS_NOWHERE
  68. gd->env_addr = (ulong)&default_environment[0];
  69. #endif
  70. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  71. enable_layerscape_ns_access();
  72. #endif
  73. return 0;
  74. }
  75. int config_board_mux(void)
  76. {
  77. return 0;
  78. }
  79. #if defined(CONFIG_MISC_INIT_R)
  80. int misc_init_r(void)
  81. {
  82. config_board_mux();
  83. return 0;
  84. }
  85. #endif
  86. int ft_board_setup(void *blob, bd_t *bd)
  87. {
  88. ft_cpu_setup(blob, bd);
  89. #ifdef CONFIG_SYS_DPAA_FMAN
  90. fdt_fixup_fman_ethernet(blob);
  91. #endif
  92. return 0;
  93. }
  94. u8 flash_read8(void *addr)
  95. {
  96. return __raw_readb(addr + 1);
  97. }
  98. void flash_write16(u16 val, void *addr)
  99. {
  100. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  101. __raw_writew(shftval, addr);
  102. }
  103. u16 flash_read16(void *addr)
  104. {
  105. u16 val = __raw_readw(addr);
  106. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  107. }