eth.c 2.0 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677
  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <netdev.h>
  9. #include <fm_eth.h>
  10. #include <fsl_dtsec.h>
  11. #include <fsl_mdio.h>
  12. #include <malloc.h>
  13. #include "../common/fman.h"
  14. int board_eth_init(bd_t *bis)
  15. {
  16. #ifdef CONFIG_FMAN_ENET
  17. int i;
  18. struct memac_mdio_info dtsec_mdio_info;
  19. struct memac_mdio_info tgec_mdio_info;
  20. struct mii_dev *dev;
  21. u32 srds_s1;
  22. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  23. srds_s1 = in_be32(&gur->rcwsr[4]) &
  24. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  25. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  26. dtsec_mdio_info.regs =
  27. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  28. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  29. /* Register the 1G MDIO bus */
  30. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  31. tgec_mdio_info.regs =
  32. (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  33. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  34. /* Register the 10G MDIO bus */
  35. fm_memac_mdio_init(bis, &tgec_mdio_info);
  36. /* Set the two on-board RGMII PHY address */
  37. fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  38. fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  39. /* QSGMII on lane B, MAC 1/2/5/6 */
  40. fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
  41. fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
  42. fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
  43. fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
  44. switch (srds_s1) {
  45. case 0x1455:
  46. break;
  47. default:
  48. printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
  49. srds_s1);
  50. break;
  51. }
  52. dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  53. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
  54. fm_info_set_mdio(i, dev);
  55. /* XFI on lane A, MAC 9 */
  56. fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  57. dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  58. fm_info_set_mdio(FM1_10GEC1, dev);
  59. cpu_eth_init(bis);
  60. #endif
  61. return pci_eth_init(bis);
  62. }