pcm052.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
  5. *
  6. * Copyright 2013 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux-vf610.h>
  12. #include <asm/arch/ddrmc-vf610.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <env.h>
  16. #include <led.h>
  17. #include <miiphy.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. static struct ddrmc_cr_setting pcm052_cr_settings[] = {
  20. /* not in the datasheets, but in the original code */
  21. { 0x00002000, 105 },
  22. { 0x00000020, 110 },
  23. /* AXI */
  24. { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
  25. { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  26. { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  27. DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  28. { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  29. DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  30. { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  31. DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  32. { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  33. DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  34. { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  35. { DDRMC_CR126_PHY_RDLAT(11), 126 },
  36. { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
  37. { DDRMC_CR137_PHYCTL_DL(2), 137 },
  38. { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  39. DDRMC_CR139_PHY_WRLV_DLL(3) |
  40. DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  41. { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  42. DDRMC_CR154_PAD_ZQ_MODE(1) |
  43. DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  44. DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
  45. { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
  46. { DDRMC_CR158_TWR(6), 158 },
  47. { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
  48. DDRMC_CR161_TODTH_WR(6), 161 },
  49. /* end marker */
  50. { 0, -1 }
  51. };
  52. /* PHY settings -- most of them differ from default in imx-regs.h */
  53. #define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213
  54. #define PCM052_DDRMC_PHY_CTRL 0x00290000
  55. #define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00
  56. #define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020
  57. static struct ddrmc_phy_setting pcm052_phy_settings[] = {
  58. { PCM052_DDRMC_PHY_DQ_TIMING, 0 },
  59. { PCM052_DDRMC_PHY_DQ_TIMING, 16 },
  60. { PCM052_DDRMC_PHY_DQ_TIMING, 32 },
  61. { PCM052_DDRMC_PHY_DQ_TIMING, 48 },
  62. { DDRMC_PHY_DQS_TIMING, 1 },
  63. { DDRMC_PHY_DQS_TIMING, 17 },
  64. { DDRMC_PHY_DQS_TIMING, 33 },
  65. { DDRMC_PHY_DQS_TIMING, 49 },
  66. { PCM052_DDRMC_PHY_CTRL, 2 },
  67. { PCM052_DDRMC_PHY_CTRL, 18 },
  68. { PCM052_DDRMC_PHY_CTRL, 34 },
  69. { DDRMC_PHY_MASTER_CTRL, 3 },
  70. { DDRMC_PHY_MASTER_CTRL, 19 },
  71. { DDRMC_PHY_MASTER_CTRL, 35 },
  72. { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 },
  73. { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
  74. { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
  75. { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
  76. { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
  77. /* end marker */
  78. { 0, -1 }
  79. };
  80. int dram_init(void)
  81. {
  82. #if defined(CONFIG_TARGET_PCM052)
  83. static const struct ddr3_jedec_timings pcm052_ddr_timings = {
  84. .tinit = 5,
  85. .trst_pwron = 80000,
  86. .cke_inactive = 200000,
  87. .wrlat = 5,
  88. .caslat_lin = 12,
  89. .trc = 6,
  90. .trrd = 4,
  91. .tccd = 4,
  92. .tbst_int_interval = 4,
  93. .tfaw = 18,
  94. .trp = 6,
  95. .twtr = 4,
  96. .tras_min = 15,
  97. .tmrd = 4,
  98. .trtp = 4,
  99. .tras_max = 14040,
  100. .tmod = 12,
  101. .tckesr = 4,
  102. .tcke = 3,
  103. .trcd_int = 6,
  104. .tras_lockout = 1,
  105. .tdal = 10,
  106. .bstlen = 3,
  107. .tdll = 512,
  108. .trp_ab = 6,
  109. .tref = 1542,
  110. .trfc = 64,
  111. .tref_int = 5,
  112. .tpdex = 3,
  113. .txpdll = 10,
  114. .txsnr = 68,
  115. .txsr = 506,
  116. .cksrx = 5,
  117. .cksre = 5,
  118. .freq_chg_en = 1,
  119. .zqcl = 256,
  120. .zqinit = 512,
  121. .zqcs = 64,
  122. .ref_per_zq = 64,
  123. .zqcs_rotate = 1,
  124. .aprebit = 10,
  125. .cmd_age_cnt = 255,
  126. .age_cnt = 255,
  127. .q_fullness = 0,
  128. .odt_rd_mapcs0 = 1,
  129. .odt_wr_mapcs0 = 1,
  130. .wlmrd = 40,
  131. .wldqsen = 25,
  132. };
  133. const int row_diff = 2;
  134. #elif defined(CONFIG_TARGET_BK4R1)
  135. static const struct ddr3_jedec_timings pcm052_ddr_timings = {
  136. .tinit = 5,
  137. .trst_pwron = 80000,
  138. .cke_inactive = 200000,
  139. .wrlat = 5,
  140. .caslat_lin = 12,
  141. .trc = 6,
  142. .trrd = 4,
  143. .tccd = 4,
  144. .tbst_int_interval = 0,
  145. .tfaw = 16,
  146. .trp = 6,
  147. .twtr = 4,
  148. .tras_min = 15,
  149. .tmrd = 4,
  150. .trtp = 4,
  151. .tras_max = 28080,
  152. .tmod = 12,
  153. .tckesr = 4,
  154. .tcke = 3,
  155. .trcd_int = 6,
  156. .tras_lockout = 1,
  157. .tdal = 12,
  158. .bstlen = 3,
  159. .tdll = 512,
  160. .trp_ab = 6,
  161. .tref = 3120,
  162. .trfc = 104,
  163. .tref_int = 0,
  164. .tpdex = 3,
  165. .txpdll = 10,
  166. .txsnr = 108,
  167. .txsr = 512,
  168. .cksrx = 5,
  169. .cksre = 5,
  170. .freq_chg_en = 1,
  171. .zqcl = 256,
  172. .zqinit = 512,
  173. .zqcs = 64,
  174. .ref_per_zq = 64,
  175. .zqcs_rotate = 1,
  176. .aprebit = 10,
  177. .cmd_age_cnt = 255,
  178. .age_cnt = 255,
  179. .q_fullness = 0,
  180. .odt_rd_mapcs0 = 1,
  181. .odt_wr_mapcs0 = 1,
  182. .wlmrd = 40,
  183. .wldqsen = 25,
  184. };
  185. const int row_diff = 1;
  186. #else /* Unknown PCM052 variant */
  187. #error DDR characteristics undefined for this target. Please define them.
  188. #endif
  189. ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
  190. pcm052_phy_settings, 1, row_diff);
  191. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  192. return 0;
  193. }
  194. static void clock_init(void)
  195. {
  196. struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
  197. struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
  198. clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
  199. CCM_CCGR0_UART1_CTRL_MASK);
  200. clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
  201. CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
  202. clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
  203. CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
  204. CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
  205. CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
  206. CCM_CCGR2_QSPI0_CTRL_MASK);
  207. clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
  208. CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
  209. clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
  210. CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
  211. CCM_CCGR4_GPC_CTRL_MASK);
  212. clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
  213. CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
  214. clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
  215. CCM_CCGR7_SDHC1_CTRL_MASK);
  216. clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
  217. CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
  218. clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
  219. CCM_CCGR10_NFC_CTRL_MASK);
  220. clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
  221. ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
  222. clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
  223. ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
  224. clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
  225. CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
  226. clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
  227. CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
  228. CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
  229. CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
  230. CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
  231. CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
  232. CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
  233. clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
  234. CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
  235. CCM_CACRR_ARM_CLK_DIV(0));
  236. clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
  237. CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
  238. CCM_CSCMR1_QSPI0_CLK_SEL(3) |
  239. CCM_CSCMR1_NFC_CLK_SEL(0));
  240. clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
  241. CCM_CSCDR1_RMII_CLK_EN);
  242. clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
  243. CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
  244. CCM_CSCDR2_NFC_EN);
  245. clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
  246. CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
  247. CCM_CSCDR3_QSPI0_X2_DIV(1) |
  248. CCM_CSCDR3_QSPI0_X4_DIV(3) |
  249. CCM_CSCDR3_NFC_PRE_DIV(5));
  250. clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
  251. CCM_CSCMR2_RMII_CLK_SEL(0));
  252. }
  253. static void mscm_init(void)
  254. {
  255. struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
  256. int i;
  257. for (i = 0; i < MSCM_IRSPRC_NUM; i++)
  258. writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
  259. }
  260. int board_early_init_f(void)
  261. {
  262. clock_init();
  263. mscm_init();
  264. return 0;
  265. }
  266. int board_init(void)
  267. {
  268. struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
  269. /* address of boot parameters */
  270. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  271. /*
  272. * Enable external 32K Oscillator
  273. *
  274. * The internal clock experiences significant drift
  275. * so we must use the external oscillator in order
  276. * to maintain correct time in the hwclock
  277. */
  278. setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
  279. return 0;
  280. }
  281. #ifdef CONFIG_TARGET_BK4R1
  282. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  283. {
  284. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  285. struct fuse_bank *bank = &ocotp->bank[4];
  286. struct fuse_bank4_regs *fuse =
  287. (struct fuse_bank4_regs *)bank->fuse_regs;
  288. u32 value;
  289. /*
  290. * BK4 has different layout of stored MAC address
  291. * than one used in imx_get_mac_from_fuse() @ generic.c
  292. */
  293. switch (dev_id) {
  294. case 0:
  295. value = readl(&fuse->mac_addr1);
  296. mac[0] = value >> 8;
  297. mac[1] = value;
  298. value = readl(&fuse->mac_addr0);
  299. mac[2] = value >> 24;
  300. mac[3] = value >> 16;
  301. mac[4] = value >> 8;
  302. mac[5] = value;
  303. break;
  304. case 1:
  305. value = readl(&fuse->mac_addr2);
  306. mac[0] = value >> 24;
  307. mac[1] = value >> 16;
  308. mac[2] = value >> 8;
  309. mac[3] = value;
  310. value = readl(&fuse->mac_addr1);
  311. mac[4] = value >> 24;
  312. mac[5] = value >> 16;
  313. break;
  314. }
  315. }
  316. int board_late_init(void)
  317. {
  318. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  319. u32 reg;
  320. if (IS_ENABLED(CONFIG_LED))
  321. led_default_state();
  322. /*
  323. * BK4r1 handle emergency/service SD card boot
  324. * Checking the SBMR1 register BOOTCFG1 byte:
  325. * NAND:
  326. * bit [2] - NAND data width - 16
  327. * bit [5] - NAND fast boot
  328. * bit [7] = 1 - NAND as a source of booting
  329. * SD card (0x64):
  330. * bit [4] = 0 - SD card source
  331. * bit [6] = 1 - SD/MMC source
  332. */
  333. reg = readl(&psrc->sbmr1);
  334. if ((reg & SRC_SBMR1_BOOTCFG1_SDMMC) &&
  335. !(reg & SRC_SBMR1_BOOTCFG1_MMC)) {
  336. printf("------ SD card boot -------\n");
  337. env_set_default("!LVFBootloader", 0);
  338. env_set("bootcmd",
  339. "run prepare_install_bk4r1_envs; run install_bk4r1rs");
  340. }
  341. return 0;
  342. }
  343. /**
  344. * KSZ8081
  345. */
  346. #define MII_KSZ8081_REFERENCE_CLOCK_SELECT 0x1f
  347. #define RMII_50MHz_CLOCK 0x8180
  348. int board_phy_config(struct phy_device *phydev)
  349. {
  350. /* Set 50 MHz reference clock */
  351. phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8081_REFERENCE_CLOCK_SELECT,
  352. RMII_50MHz_CLOCK);
  353. return genphy_config(phydev);
  354. }
  355. #endif /* CONFIG_TARGET_BK4R1 */
  356. int checkboard(void)
  357. {
  358. #ifdef CONFIG_TARGET_BK4R1
  359. puts("Board: BK4r1 (L333)\n");
  360. #else
  361. puts("Board: PCM-052\n");
  362. #endif
  363. return 0;
  364. }