board.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Gumstix Pepper and AM335x-based boards
  4. *
  5. * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
  6. * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <errno.h>
  11. #include <spl.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/omap.h>
  15. #include <asm/arch/ddr_defs.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/gpio.h>
  18. #include <asm/arch/mmc_host_def.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/arch/mem.h>
  21. #include <asm/io.h>
  22. #include <asm/emif.h>
  23. #include <asm/gpio.h>
  24. #include <i2c.h>
  25. #include <miiphy.h>
  26. #include <cpsw.h>
  27. #include <power/tps65217.h>
  28. #include <watchdog.h>
  29. #include "board.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #ifdef CONFIG_SPL_BUILD
  32. #define OSC (V_OSCK/1000000)
  33. static const struct ddr_data ddr3_data = {
  34. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  35. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  36. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  37. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  38. };
  39. static const struct cmd_control ddr3_cmd_ctrl_data = {
  40. .cmd0csratio = MT41K256M16HA125E_RATIO,
  41. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  42. .cmd1csratio = MT41K256M16HA125E_RATIO,
  43. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  44. .cmd2csratio = MT41K256M16HA125E_RATIO,
  45. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  46. };
  47. static struct emif_regs ddr3_emif_reg_data = {
  48. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  49. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  50. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  51. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  52. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  53. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  54. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  55. };
  56. const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
  57. const struct ctrl_ioregs ioregs_ddr3 = {
  58. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  59. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  60. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  61. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  62. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  63. };
  64. static const struct ddr_data ddr2_data = {
  65. .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  66. .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  67. .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  68. };
  69. static const struct cmd_control ddr2_cmd_ctrl_data = {
  70. .cmd0csratio = MT47H128M16RT25E_RATIO,
  71. .cmd1csratio = MT47H128M16RT25E_RATIO,
  72. .cmd2csratio = MT47H128M16RT25E_RATIO,
  73. };
  74. static const struct emif_regs ddr2_emif_reg_data = {
  75. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  76. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  77. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  78. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  79. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  80. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  81. };
  82. const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
  83. const struct ctrl_ioregs ioregs_ddr2 = {
  84. .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  85. .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  86. .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  87. .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  88. .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  89. };
  90. static int read_eeprom(struct pepper_board_id *header)
  91. {
  92. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  93. return -ENODEV;
  94. }
  95. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  96. sizeof(struct pepper_board_id))) {
  97. return -EIO;
  98. }
  99. return 0;
  100. }
  101. const struct dpll_params *get_dpll_ddr_params(void)
  102. {
  103. struct pepper_board_id header;
  104. enable_i2c0_pin_mux();
  105. i2c_set_bus_num(0);
  106. if (read_eeprom(&header) < 0)
  107. return &dpll_ddr3;
  108. switch (header.device_vendor) {
  109. case GUMSTIX_PEPPER:
  110. return &dpll_ddr2;
  111. case GUMSTIX_PEPPER_DVI:
  112. return &dpll_ddr3;
  113. default:
  114. return &dpll_ddr3;
  115. }
  116. }
  117. void sdram_init(void)
  118. {
  119. const struct dpll_params *dpll = get_dpll_ddr_params();
  120. /*
  121. * Here we are assuming PLL clock reveals the type of RAM.
  122. * DDR2 = 266
  123. * DDR3 = 400
  124. * Note that DDR3 is the default.
  125. */
  126. if (dpll->m == 266) {
  127. config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
  128. &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
  129. }
  130. else if (dpll->m == 400) {
  131. config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
  132. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  133. }
  134. }
  135. #ifdef CONFIG_SPL_OS_BOOT
  136. int spl_start_uboot(void)
  137. {
  138. /* break into full u-boot on 'c' */
  139. return serial_tstc() && serial_getc() == 'c';
  140. }
  141. #endif
  142. void set_uart_mux_conf(void)
  143. {
  144. enable_uart0_pin_mux();
  145. }
  146. void set_mux_conf_regs(void)
  147. {
  148. enable_board_pin_mux();
  149. }
  150. #endif
  151. int board_init(void)
  152. {
  153. #if defined(CONFIG_HW_WATCHDOG)
  154. hw_watchdog_init();
  155. #endif
  156. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  157. gpmc_init();
  158. return 0;
  159. }
  160. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  161. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  162. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  163. static void cpsw_control(int enabled)
  164. {
  165. /* VTP can be added here */
  166. return;
  167. }
  168. static struct cpsw_slave_data cpsw_slaves[] = {
  169. {
  170. .slave_reg_ofs = 0x208,
  171. .sliver_reg_ofs = 0xd80,
  172. .phy_addr = 0,
  173. .phy_if = PHY_INTERFACE_MODE_RGMII,
  174. },
  175. };
  176. static struct cpsw_platform_data cpsw_data = {
  177. .mdio_base = CPSW_MDIO_BASE,
  178. .cpsw_base = CPSW_BASE,
  179. .mdio_div = 0xff,
  180. .channels = 8,
  181. .cpdma_reg_ofs = 0x800,
  182. .slaves = 1,
  183. .slave_data = cpsw_slaves,
  184. .ale_reg_ofs = 0xd00,
  185. .ale_entries = 1024,
  186. .host_port_reg_ofs = 0x108,
  187. .hw_stats_reg_ofs = 0x900,
  188. .bd_ram_ofs = 0x2000,
  189. .mac_control = (1 << 5),
  190. .control = cpsw_control,
  191. .host_port_num = 0,
  192. .version = CPSW_CTRL_VERSION_2,
  193. };
  194. int board_eth_init(bd_t *bis)
  195. {
  196. int rv, n = 0;
  197. uint8_t mac_addr[6];
  198. uint32_t mac_hi, mac_lo;
  199. const char *devname;
  200. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  201. /* try reading mac address from efuse */
  202. mac_lo = readl(&cdev->macid0l);
  203. mac_hi = readl(&cdev->macid0h);
  204. mac_addr[0] = mac_hi & 0xFF;
  205. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  206. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  207. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  208. mac_addr[4] = mac_lo & 0xFF;
  209. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  210. if (is_valid_ethaddr(mac_addr))
  211. eth_env_set_enetaddr("ethaddr", mac_addr);
  212. }
  213. writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
  214. rv = cpsw_register(&cpsw_data);
  215. if (rv < 0)
  216. printf("Error %d registering CPSW switch\n", rv);
  217. else
  218. n += rv;
  219. /*
  220. *
  221. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  222. * operating points. So we must set the TX clock delay feature
  223. * in the KSZ9021 PHY. Since we only support a single ethernet
  224. * device in U-Boot, we only do this for the current instance.
  225. */
  226. devname = miiphy_get_current_dev();
  227. /* max rx/tx clock delay, min rx/tx control delay */
  228. miiphy_write(devname, 0x0, 0x0b, 0x8104);
  229. miiphy_write(devname, 0x0, 0xc, 0xa0a0);
  230. /* min rx data delay */
  231. miiphy_write(devname, 0x0, 0x0b, 0x8105);
  232. miiphy_write(devname, 0x0, 0x0c, 0x0000);
  233. /* min tx data delay */
  234. miiphy_write(devname, 0x0, 0x0b, 0x8106);
  235. miiphy_write(devname, 0x0, 0x0c, 0x0000);
  236. return n;
  237. }
  238. #endif