opos6ul.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Armadeus Systems
  4. */
  5. #include <asm/arch/clock.h>
  6. #include <asm/arch/crm_regs.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/iomux.h>
  9. #include <asm/arch/mx6-pins.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/gpio.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <asm/io.h>
  14. #include <common.h>
  15. #include <env.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #ifdef CONFIG_FEC_MXC
  18. #include <miiphy.h>
  19. #define MDIO_PAD_CTRL ( \
  20. PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  21. PAD_CTL_DSE_40ohm \
  22. )
  23. #define ENET_PAD_CTRL_PU ( \
  24. PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  25. PAD_CTL_DSE_40ohm \
  26. )
  27. #define ENET_PAD_CTRL_PD ( \
  28. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
  29. PAD_CTL_DSE_40ohm \
  30. )
  31. #define ENET_CLK_PAD_CTRL ( \
  32. PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  33. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
  34. )
  35. static iomux_v3_cfg_t const fec1_pads[] = {
  36. MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  37. MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  38. MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  39. MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  40. MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  41. MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  42. MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
  43. MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
  44. MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
  45. /* PHY Int */
  46. MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
  47. /* PHY Reset */
  48. MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  49. MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  50. };
  51. int board_phy_config(struct phy_device *phydev)
  52. {
  53. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  54. if (phydev->drv->config)
  55. phydev->drv->config(phydev);
  56. return 0;
  57. }
  58. int board_eth_init(bd_t *bis)
  59. {
  60. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  61. struct gpio_desc rst;
  62. int ret;
  63. /* Use 50M anatop loopback REF_CLK1 for ENET1,
  64. * clear gpr1[13], set gpr1[17] */
  65. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  66. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  67. ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  68. if (ret)
  69. return ret;
  70. enable_enet_clk(1);
  71. imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
  72. ret = dm_gpio_lookup_name("GPIO4_2", &rst);
  73. if (ret) {
  74. printf("Cannot get GPIO4_2\n");
  75. return ret;
  76. }
  77. ret = dm_gpio_request(&rst, "phy-rst");
  78. if (ret) {
  79. printf("Cannot request GPIO4_2\n");
  80. return ret;
  81. }
  82. dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT);
  83. dm_gpio_set_value(&rst, 0);
  84. udelay(1000);
  85. dm_gpio_set_value(&rst, 1);
  86. return fecmxc_initialize(bis);
  87. }
  88. #endif /* CONFIG_FEC_MXC */
  89. int board_init(void)
  90. {
  91. /* Address of boot parameters */
  92. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  93. return 0;
  94. }
  95. int __weak opos6ul_board_late_init(void)
  96. {
  97. return 0;
  98. }
  99. int board_late_init(void)
  100. {
  101. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  102. unsigned reg = readl(&psrc->sbmr2);
  103. /* In bootstrap don't use the env vars */
  104. if (((reg & 0x3000000) >> 24) == 0x1) {
  105. env_set_default(NULL, 0);
  106. env_set("preboot", "");
  107. }
  108. return opos6ul_board_late_init();
  109. }
  110. int dram_init(void)
  111. {
  112. gd->ram_size = imx_ddr_size();
  113. return 0;
  114. }
  115. #ifdef CONFIG_SPL_BUILD
  116. #include <asm/arch/mx6-ddr.h>
  117. #include <linux/libfdt.h>
  118. #include <spl.h>
  119. static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  120. .grp_addds = 0x00000030,
  121. .grp_ddrmode_ctl = 0x00020000,
  122. .grp_b0ds = 0x00000030,
  123. .grp_ctlds = 0x00000030,
  124. .grp_b1ds = 0x00000030,
  125. .grp_ddrpke = 0x00000000,
  126. .grp_ddrmode = 0x00020000,
  127. .grp_ddr_type = 0x000c0000,
  128. };
  129. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  130. .dram_dqm0 = 0x00000030,
  131. .dram_dqm1 = 0x00000030,
  132. .dram_ras = 0x00000030,
  133. .dram_cas = 0x00000030,
  134. .dram_odt0 = 0x00000030,
  135. .dram_odt1 = 0x00000030,
  136. .dram_sdba2 = 0x00000000,
  137. .dram_sdclk_0 = 0x00000008,
  138. .dram_sdqs0 = 0x00000038,
  139. .dram_sdqs1 = 0x00000030,
  140. .dram_reset = 0x00000030,
  141. };
  142. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  143. .p0_mpwldectrl0 = 0x00070007,
  144. .p0_mpdgctrl0 = 0x41490145,
  145. .p0_mprddlctl = 0x40404546,
  146. .p0_mpwrdlctl = 0x4040524D,
  147. };
  148. struct mx6_ddr_sysinfo ddr_sysinfo = {
  149. .dsize = 0,
  150. .cs_density = 20,
  151. .ncs = 1,
  152. .cs1_mirror = 0,
  153. .rtt_wr = 2,
  154. .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  155. .walat = 1, /* Write additional latency */
  156. .ralat = 5, /* Read additional latency */
  157. .mif3_mode = 3, /* Command prediction working mode */
  158. .bi_on = 1, /* Bank interleaving enabled */
  159. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  160. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  161. .ddr_type = DDR_TYPE_DDR3,
  162. .refsel = 1, /* Refresh cycles at 32KHz */
  163. .refr = 7, /* 8 refreshes commands per refresh cycle */
  164. };
  165. static struct mx6_ddr3_cfg mem_ddr = {
  166. .mem_speed = 800,
  167. .density = 2,
  168. .width = 16,
  169. .banks = 8,
  170. .rowaddr = 14,
  171. .coladdr = 10,
  172. .pagesz = 2,
  173. .trcd = 1500,
  174. .trcmin = 5250,
  175. .trasmin = 3750,
  176. };
  177. void board_boot_order(u32 *spl_boot_list)
  178. {
  179. unsigned int bmode = readl(&src_base->sbmr2);
  180. if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
  181. spl_boot_list[0] = BOOT_DEVICE_UART;
  182. else
  183. spl_boot_list[0] = spl_boot_device();
  184. }
  185. static void ccgr_init(void)
  186. {
  187. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  188. writel(0xFFFFFFFF, &ccm->CCGR0);
  189. writel(0xFFFFFFFF, &ccm->CCGR1);
  190. writel(0xFFFFFFFF, &ccm->CCGR2);
  191. writel(0xFFFFFFFF, &ccm->CCGR3);
  192. writel(0xFFFFFFFF, &ccm->CCGR4);
  193. writel(0xFFFFFFFF, &ccm->CCGR5);
  194. writel(0xFFFFFFFF, &ccm->CCGR6);
  195. writel(0xFFFFFFFF, &ccm->CCGR7);
  196. }
  197. static void spl_dram_init(void)
  198. {
  199. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  200. struct fuse_bank *bank = &ocotp->bank[4];
  201. struct fuse_bank4_regs *fuse =
  202. (struct fuse_bank4_regs *)bank->fuse_regs;
  203. int reg = readl(&fuse->gp1);
  204. /* 512MB of RAM */
  205. if (reg & 0x1) {
  206. mem_ddr.density = 4;
  207. mem_ddr.rowaddr = 15;
  208. mem_ddr.trcd = 1375;
  209. mem_ddr.trcmin = 4875;
  210. mem_ddr.trasmin = 3500;
  211. }
  212. mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  213. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  214. }
  215. void spl_board_init(void)
  216. {
  217. preloader_console_init();
  218. }
  219. void board_init_f(ulong dummy)
  220. {
  221. ccgr_init();
  222. /* setup AIPS and disable watchdog */
  223. arch_cpu_init();
  224. /* setup GP timer */
  225. timer_init();
  226. /* DDR initialization */
  227. spl_dram_init();
  228. }
  229. #endif /* CONFIG_SPL_BUILD */