display.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Google Inc.
  4. *
  5. * Extracted from Chromium coreboot commit 3f59b13d
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <edid.h>
  10. #include <errno.h>
  11. #include <display.h>
  12. #include <edid.h>
  13. #include <lcd.h>
  14. #include <part.h>
  15. #include <video.h>
  16. #include <asm/gpio.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/pwm.h>
  20. #include <asm/arch-tegra/dc.h>
  21. #include <dm/uclass-internal.h>
  22. #include "displayport.h"
  23. /* return in 1000ths of a Hertz */
  24. static int tegra_dc_calc_refresh(const struct display_timing *timing)
  25. {
  26. int h_total, v_total, refresh;
  27. int pclk = timing->pixelclock.typ;
  28. h_total = timing->hactive.typ + timing->hfront_porch.typ +
  29. timing->hback_porch.typ + timing->hsync_len.typ;
  30. v_total = timing->vactive.typ + timing->vfront_porch.typ +
  31. timing->vback_porch.typ + timing->vsync_len.typ;
  32. if (!pclk || !h_total || !v_total)
  33. return 0;
  34. refresh = pclk / h_total;
  35. refresh *= 1000;
  36. refresh /= v_total;
  37. return refresh;
  38. }
  39. static void print_mode(const struct display_timing *timing)
  40. {
  41. int refresh = tegra_dc_calc_refresh(timing);
  42. debug("MODE:%dx%d@%d.%03uHz pclk=%d\n",
  43. timing->hactive.typ, timing->vactive.typ, refresh / 1000,
  44. refresh % 1000, timing->pixelclock.typ);
  45. }
  46. static int update_display_mode(struct dc_ctlr *disp_ctrl,
  47. const struct display_timing *timing,
  48. int href_to_sync, int vref_to_sync)
  49. {
  50. print_mode(timing);
  51. writel(0x1, &disp_ctrl->disp.disp_timing_opt);
  52. writel(vref_to_sync << 16 | href_to_sync,
  53. &disp_ctrl->disp.ref_to_sync);
  54. writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ,
  55. &disp_ctrl->disp.sync_width);
  56. writel(((timing->vback_porch.typ - vref_to_sync) << 16) |
  57. timing->hback_porch.typ, &disp_ctrl->disp.back_porch);
  58. writel(((timing->vfront_porch.typ + vref_to_sync) << 16) |
  59. timing->hfront_porch.typ, &disp_ctrl->disp.front_porch);
  60. writel(timing->hactive.typ | (timing->vactive.typ << 16),
  61. &disp_ctrl->disp.disp_active);
  62. /**
  63. * We want to use PLLD_out0, which is PLLD / 2:
  64. * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv.
  65. *
  66. * Currently most panels work inside clock range 50MHz~100MHz, and PLLD
  67. * has some requirements to have VCO in range 500MHz~1000MHz (see
  68. * clock.c for more detail). To simplify calculation, we set
  69. * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
  70. * may be calculated by clock_display, to allow wider frequency range.
  71. *
  72. * Note ShiftClockDiv is a 7.1 format value.
  73. */
  74. const u32 shift_clock_div = 1;
  75. writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
  76. ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT,
  77. &disp_ctrl->disp.disp_clk_ctrl);
  78. debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__,
  79. timing->pixelclock.typ, shift_clock_div);
  80. return 0;
  81. }
  82. static u32 tegra_dc_poll_register(void *reg,
  83. u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
  84. {
  85. u32 temp = timeout_us;
  86. u32 reg_val = 0;
  87. do {
  88. udelay(poll_interval_us);
  89. reg_val = readl(reg);
  90. if (timeout_us > poll_interval_us)
  91. timeout_us -= poll_interval_us;
  92. else
  93. break;
  94. } while ((reg_val & mask) != exp_val);
  95. if ((reg_val & mask) == exp_val)
  96. return 0; /* success */
  97. return temp;
  98. }
  99. int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl)
  100. {
  101. writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
  102. if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl,
  103. GENERAL_ACT_REQ, 0, 100,
  104. DC_POLL_TIMEOUT_MS * 1000)) {
  105. debug("dc timeout waiting for DC to stop\n");
  106. return -ETIMEDOUT;
  107. }
  108. return 0;
  109. }
  110. static struct display_timing min_mode = {
  111. .hsync_len = { .typ = 1 },
  112. .vsync_len = { .typ = 1 },
  113. .hback_porch = { .typ = 20 },
  114. .vback_porch = { .typ = 0 },
  115. .hactive = { .typ = 16 },
  116. .vactive = { .typ = 16 },
  117. .hfront_porch = { .typ = 1 },
  118. .vfront_porch = { .typ = 2 },
  119. };
  120. /* Disable windows and set minimum raster timings */
  121. void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
  122. int *dc_reg_ctx)
  123. {
  124. const int href_to_sync = 0, vref_to_sync = 1;
  125. int selected_windows, i;
  126. selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
  127. /* Store and clear window options */
  128. for (i = 0; i < DC_N_WINDOWS; ++i) {
  129. writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
  130. dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt);
  131. writel(0, &disp_ctrl->win.win_opt);
  132. writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
  133. }
  134. writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
  135. /* Store current raster timings and set minimum timings */
  136. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync);
  137. writel(href_to_sync | (vref_to_sync << 16),
  138. &disp_ctrl->disp.ref_to_sync);
  139. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width);
  140. writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16),
  141. &disp_ctrl->disp.sync_width);
  142. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch);
  143. writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16),
  144. &disp_ctrl->disp.back_porch);
  145. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch);
  146. writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16),
  147. &disp_ctrl->disp.front_porch);
  148. dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active);
  149. writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16),
  150. &disp_ctrl->disp.disp_active);
  151. writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
  152. }
  153. /* Restore previous windows status and raster timings */
  154. void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
  155. int *dc_reg_ctx)
  156. {
  157. int selected_windows, i;
  158. selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
  159. for (i = 0; i < DC_N_WINDOWS; ++i) {
  160. writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
  161. writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt);
  162. writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
  163. }
  164. writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
  165. writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync);
  166. writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width);
  167. writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch);
  168. writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch);
  169. writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active);
  170. writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl);
  171. }
  172. static int tegra_depth_for_bpp(int bpp)
  173. {
  174. switch (bpp) {
  175. case 32:
  176. return COLOR_DEPTH_R8G8B8A8;
  177. case 16:
  178. return COLOR_DEPTH_B5G6R5;
  179. default:
  180. debug("Unsupported LCD bit depth");
  181. return -1;
  182. }
  183. }
  184. static int update_window(struct dc_ctlr *disp_ctrl,
  185. u32 frame_buffer, int fb_bits_per_pixel,
  186. const struct display_timing *timing)
  187. {
  188. const u32 colour_white = 0xffffff;
  189. int colour_depth;
  190. u32 val;
  191. writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
  192. writel(((timing->vactive.typ << 16) | timing->hactive.typ),
  193. &disp_ctrl->win.size);
  194. writel(((timing->vactive.typ << 16) |
  195. (timing->hactive.typ * fb_bits_per_pixel / 8)),
  196. &disp_ctrl->win.prescaled_size);
  197. writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) /
  198. 32 * 32), &disp_ctrl->win.line_stride);
  199. colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel);
  200. if (colour_depth == -1)
  201. return -EINVAL;
  202. writel(colour_depth, &disp_ctrl->win.color_depth);
  203. writel(frame_buffer, &disp_ctrl->winbuf.start_addr);
  204. writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT,
  205. &disp_ctrl->win.dda_increment);
  206. writel(colour_white, &disp_ctrl->disp.blend_background_color);
  207. writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
  208. &disp_ctrl->cmd.disp_cmd);
  209. writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
  210. val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
  211. val |= GENERAL_UPDATE | WIN_A_UPDATE;
  212. writel(val, &disp_ctrl->cmd.state_ctrl);
  213. /* Enable win_a */
  214. val = readl(&disp_ctrl->win.win_opt);
  215. writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt);
  216. return 0;
  217. }
  218. static int tegra_dc_init(struct dc_ctlr *disp_ctrl)
  219. {
  220. /* do not accept interrupts during initialization */
  221. writel(0x00000000, &disp_ctrl->cmd.int_mask);
  222. writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
  223. &disp_ctrl->cmd.state_access);
  224. writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
  225. writel(0x00000000, &disp_ctrl->win.win_opt);
  226. writel(0x00000000, &disp_ctrl->win.byte_swap);
  227. writel(0x00000000, &disp_ctrl->win.buffer_ctrl);
  228. writel(0x00000000, &disp_ctrl->win.pos);
  229. writel(0x00000000, &disp_ctrl->win.h_initial_dda);
  230. writel(0x00000000, &disp_ctrl->win.v_initial_dda);
  231. writel(0x00000000, &disp_ctrl->win.dda_increment);
  232. writel(0x00000000, &disp_ctrl->win.dv_ctrl);
  233. writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl);
  234. writel(0x00000000, &disp_ctrl->win.blend_match_select);
  235. writel(0x00000000, &disp_ctrl->win.blend_nomatch_select);
  236. writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit);
  237. writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi);
  238. writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset);
  239. writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset);
  240. writel(0x00000000, &disp_ctrl->com.crc_checksum);
  241. writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]);
  242. writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]);
  243. writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]);
  244. writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]);
  245. writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0);
  246. return 0;
  247. }
  248. static void dump_config(int panel_bpp, struct display_timing *timing)
  249. {
  250. printf("timing->hactive.typ = %d\n", timing->hactive.typ);
  251. printf("timing->vactive.typ = %d\n", timing->vactive.typ);
  252. printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ);
  253. printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ);
  254. printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ);
  255. printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ);
  256. printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ);
  257. printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ);
  258. printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ);
  259. printf("panel_bits_per_pixel = %d\n", panel_bpp);
  260. }
  261. static int display_update_config_from_edid(struct udevice *dp_dev,
  262. int *panel_bppp,
  263. struct display_timing *timing)
  264. {
  265. return display_read_timing(dp_dev, timing);
  266. }
  267. static int display_init(struct udevice *dev, void *lcdbase,
  268. int fb_bits_per_pixel, struct display_timing *timing)
  269. {
  270. struct display_plat *disp_uc_plat;
  271. struct dc_ctlr *dc_ctlr;
  272. struct udevice *dp_dev;
  273. const int href_to_sync = 1, vref_to_sync = 1;
  274. int panel_bpp = 18; /* default 18 bits per pixel */
  275. u32 plld_rate;
  276. int ret;
  277. /*
  278. * Before we probe the display device (eDP), tell it that this device
  279. * is the source of the display data.
  280. */
  281. ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
  282. if (ret) {
  283. debug("%s: device '%s' display not found (ret=%d)\n", __func__,
  284. dev->name, ret);
  285. return ret;
  286. }
  287. disp_uc_plat = dev_get_uclass_platdata(dp_dev);
  288. debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name,
  289. disp_uc_plat);
  290. disp_uc_plat->src_dev = dev;
  291. ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
  292. if (ret) {
  293. debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret);
  294. return ret;
  295. }
  296. dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
  297. if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
  298. debug("%s: Failed to decode display timing\n", __func__);
  299. return -EINVAL;
  300. }
  301. ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
  302. if (ret) {
  303. debug("%s: Failed to decode EDID, using defaults\n", __func__);
  304. dump_config(panel_bpp, timing);
  305. }
  306. /*
  307. * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
  308. * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
  309. * update_display_mode() for detail.
  310. */
  311. plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2);
  312. if (plld_rate == 0) {
  313. printf("dc: clock init failed\n");
  314. return -EIO;
  315. } else if (plld_rate != timing->pixelclock.typ * 2) {
  316. debug("dc: plld rounded to %u\n", plld_rate);
  317. timing->pixelclock.typ = plld_rate / 2;
  318. }
  319. /* Init dc */
  320. ret = tegra_dc_init(dc_ctlr);
  321. if (ret) {
  322. debug("dc: init failed\n");
  323. return ret;
  324. }
  325. /* Configure dc mode */
  326. ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync);
  327. if (ret) {
  328. debug("dc: failed to configure display mode\n");
  329. return ret;
  330. }
  331. /* Enable dp */
  332. ret = display_enable(dp_dev, panel_bpp, timing);
  333. if (ret) {
  334. debug("dc: failed to enable display: ret=%d\n", ret);
  335. return ret;
  336. }
  337. ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
  338. if (ret) {
  339. debug("dc: failed to update window\n");
  340. return ret;
  341. }
  342. debug("%s: ready\n", __func__);
  343. return 0;
  344. }
  345. enum {
  346. /* Maximum LCD size we support */
  347. LCD_MAX_WIDTH = 1920,
  348. LCD_MAX_HEIGHT = 1200,
  349. LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
  350. };
  351. static int tegra124_lcd_init(struct udevice *dev, void *lcdbase,
  352. enum video_log2_bpp l2bpp)
  353. {
  354. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  355. struct display_timing timing;
  356. int ret;
  357. clock_set_up_plldp();
  358. clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
  359. clock_enable(PERIPH_ID_HOST1X);
  360. clock_enable(PERIPH_ID_DISP1);
  361. clock_enable(PERIPH_ID_PWM);
  362. clock_enable(PERIPH_ID_DPAUX);
  363. clock_enable(PERIPH_ID_SOR0);
  364. udelay(2);
  365. reset_set_enable(PERIPH_ID_HOST1X, 0);
  366. reset_set_enable(PERIPH_ID_DISP1, 0);
  367. reset_set_enable(PERIPH_ID_PWM, 0);
  368. reset_set_enable(PERIPH_ID_DPAUX, 0);
  369. reset_set_enable(PERIPH_ID_SOR0, 0);
  370. ret = display_init(dev, lcdbase, 1 << l2bpp, &timing);
  371. if (ret)
  372. return ret;
  373. uc_priv->xsize = roundup(timing.hactive.typ, 16);
  374. uc_priv->ysize = timing.vactive.typ;
  375. uc_priv->bpix = l2bpp;
  376. video_set_flush_dcache(dev, 1);
  377. debug("%s: done\n", __func__);
  378. return 0;
  379. }
  380. static int tegra124_lcd_probe(struct udevice *dev)
  381. {
  382. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  383. ulong start;
  384. int ret;
  385. start = get_timer(0);
  386. bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "lcd");
  387. ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16);
  388. bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
  389. debug("LCD init took %lu ms\n", get_timer(start));
  390. if (ret)
  391. printf("%s: Error %d\n", __func__, ret);
  392. return 0;
  393. }
  394. static int tegra124_lcd_bind(struct udevice *dev)
  395. {
  396. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  397. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  398. (1 << VIDEO_BPP16) / 8;
  399. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  400. return 0;
  401. }
  402. static const struct udevice_id tegra124_lcd_ids[] = {
  403. { .compatible = "nvidia,tegra124-dc" },
  404. { }
  405. };
  406. U_BOOT_DRIVER(tegra124_dc) = {
  407. .name = "tegra124-dc",
  408. .id = UCLASS_VIDEO,
  409. .of_match = tegra124_lcd_ids,
  410. .bind = tegra124_lcd_bind,
  411. .probe = tegra124_lcd_probe,
  412. };