tegra.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <fdtdec.h>
  8. #include <panel.h>
  9. #include <part.h>
  10. #include <pwm.h>
  11. #include <video.h>
  12. #include <asm/cache.h>
  13. #include <asm/system.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/funcmux.h>
  18. #include <asm/arch/pinmux.h>
  19. #include <asm/arch/pwm.h>
  20. #include <asm/arch/display.h>
  21. #include <asm/arch-tegra/timer.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. /* Information about the display controller */
  24. struct tegra_lcd_priv {
  25. int width; /* width in pixels */
  26. int height; /* height in pixels */
  27. enum video_log2_bpp log2_bpp; /* colour depth */
  28. struct display_timing timing;
  29. struct udevice *panel;
  30. struct disp_ctlr *disp; /* Display controller to use */
  31. fdt_addr_t frame_buffer; /* Address of frame buffer */
  32. unsigned pixel_clock; /* Pixel clock in Hz */
  33. };
  34. enum {
  35. /* Maximum LCD size we support */
  36. LCD_MAX_WIDTH = 1366,
  37. LCD_MAX_HEIGHT = 768,
  38. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  39. };
  40. static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
  41. {
  42. unsigned h_dda, v_dda;
  43. unsigned long val;
  44. val = readl(&dc->cmd.disp_win_header);
  45. val |= WINDOW_A_SELECT;
  46. writel(val, &dc->cmd.disp_win_header);
  47. writel(win->fmt, &dc->win.color_depth);
  48. clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
  49. BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
  50. val = win->out_x << H_POSITION_SHIFT;
  51. val |= win->out_y << V_POSITION_SHIFT;
  52. writel(val, &dc->win.pos);
  53. val = win->out_w << H_SIZE_SHIFT;
  54. val |= win->out_h << V_SIZE_SHIFT;
  55. writel(val, &dc->win.size);
  56. val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
  57. val |= win->h << V_PRESCALED_SIZE_SHIFT;
  58. writel(val, &dc->win.prescaled_size);
  59. writel(0, &dc->win.h_initial_dda);
  60. writel(0, &dc->win.v_initial_dda);
  61. h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
  62. v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
  63. val = h_dda << H_DDA_INC_SHIFT;
  64. val |= v_dda << V_DDA_INC_SHIFT;
  65. writel(val, &dc->win.dda_increment);
  66. writel(win->stride, &dc->win.line_stride);
  67. writel(0, &dc->win.buf_stride);
  68. val = WIN_ENABLE;
  69. if (win->bpp < 24)
  70. val |= COLOR_EXPAND;
  71. writel(val, &dc->win.win_opt);
  72. writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
  73. writel(win->x, &dc->winbuf.addr_h_offset);
  74. writel(win->y, &dc->winbuf.addr_v_offset);
  75. writel(0xff00, &dc->win.blend_nokey);
  76. writel(0xff00, &dc->win.blend_1win);
  77. val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
  78. val |= GENERAL_UPDATE | WIN_A_UPDATE;
  79. writel(val, &dc->cmd.state_ctrl);
  80. }
  81. static int update_display_mode(struct dc_disp_reg *disp,
  82. struct tegra_lcd_priv *priv)
  83. {
  84. struct display_timing *dt = &priv->timing;
  85. unsigned long val;
  86. unsigned long rate;
  87. unsigned long div;
  88. writel(0x0, &disp->disp_timing_opt);
  89. writel(1 | 1 << 16, &disp->ref_to_sync);
  90. writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
  91. writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
  92. &disp->back_porch);
  93. writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
  94. &disp->front_porch);
  95. writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
  96. val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
  97. val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
  98. writel(val, &disp->data_enable_opt);
  99. val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
  100. val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
  101. val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
  102. writel(val, &disp->disp_interface_ctrl);
  103. /*
  104. * The pixel clock divider is in 7.1 format (where the bottom bit
  105. * represents 0.5). Here we calculate the divider needed to get from
  106. * the display clock (typically 600MHz) to the pixel clock. We round
  107. * up or down as requried.
  108. */
  109. rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
  110. div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
  111. debug("Display clock %lu, divider %lu\n", rate, div);
  112. writel(0x00010001, &disp->shift_clk_opt);
  113. val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
  114. val |= div << SHIFT_CLK_DIVIDER_SHIFT;
  115. writel(val, &disp->disp_clk_ctrl);
  116. return 0;
  117. }
  118. /* Start up the display and turn on power to PWMs */
  119. static void basic_init(struct dc_cmd_reg *cmd)
  120. {
  121. u32 val;
  122. writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
  123. writel(0x0000011a, &cmd->cont_syncpt_vsync);
  124. writel(0x00000000, &cmd->int_type);
  125. writel(0x00000000, &cmd->int_polarity);
  126. writel(0x00000000, &cmd->int_mask);
  127. writel(0x00000000, &cmd->int_enb);
  128. val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
  129. val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
  130. val |= PM1_ENABLE;
  131. writel(val, &cmd->disp_pow_ctrl);
  132. val = readl(&cmd->disp_cmd);
  133. val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
  134. writel(val, &cmd->disp_cmd);
  135. }
  136. static void basic_init_timer(struct dc_disp_reg *disp)
  137. {
  138. writel(0x00000020, &disp->mem_high_pri);
  139. writel(0x00000001, &disp->mem_high_pri_timer);
  140. }
  141. static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
  142. 0x00000000,
  143. 0x00000000,
  144. 0x00000000,
  145. 0x00000000,
  146. };
  147. static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
  148. 0x00000000,
  149. 0x01000000,
  150. 0x00000000,
  151. 0x00000000,
  152. };
  153. static const u32 rgb_data_tab[PIN_REG_COUNT] = {
  154. 0x00000000,
  155. 0x00000000,
  156. 0x00000000,
  157. 0x00000000,
  158. };
  159. static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
  160. 0x00000000,
  161. 0x00000000,
  162. 0x00000000,
  163. 0x00000000,
  164. 0x00210222,
  165. 0x00002200,
  166. 0x00020000,
  167. };
  168. static void rgb_enable(struct dc_com_reg *com)
  169. {
  170. int i;
  171. for (i = 0; i < PIN_REG_COUNT; i++) {
  172. writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
  173. writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
  174. writel(rgb_data_tab[i], &com->pin_output_data[i]);
  175. }
  176. for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
  177. writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
  178. }
  179. static int setup_window(struct disp_ctl_win *win,
  180. struct tegra_lcd_priv *priv)
  181. {
  182. win->x = 0;
  183. win->y = 0;
  184. win->w = priv->width;
  185. win->h = priv->height;
  186. win->out_x = 0;
  187. win->out_y = 0;
  188. win->out_w = priv->width;
  189. win->out_h = priv->height;
  190. win->phys_addr = priv->frame_buffer;
  191. win->stride = priv->width * (1 << priv->log2_bpp) / 8;
  192. debug("%s: depth = %d\n", __func__, priv->log2_bpp);
  193. switch (priv->log2_bpp) {
  194. case VIDEO_BPP32:
  195. win->fmt = COLOR_DEPTH_R8G8B8A8;
  196. win->bpp = 32;
  197. break;
  198. case VIDEO_BPP16:
  199. win->fmt = COLOR_DEPTH_B5G6R5;
  200. win->bpp = 16;
  201. break;
  202. default:
  203. debug("Unsupported LCD bit depth");
  204. return -1;
  205. }
  206. return 0;
  207. }
  208. /**
  209. * Register a new display based on device tree configuration.
  210. *
  211. * The frame buffer can be positioned by U-Boot or overridden by the fdt.
  212. * You should pass in the U-Boot address here, and check the contents of
  213. * struct tegra_lcd_priv to see what was actually chosen.
  214. *
  215. * @param blob Device tree blob
  216. * @param priv Driver's private data
  217. * @param default_lcd_base Default address of LCD frame buffer
  218. * @return 0 if ok, -1 on error (unsupported bits per pixel)
  219. */
  220. static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
  221. void *default_lcd_base)
  222. {
  223. struct disp_ctl_win window;
  224. struct dc_ctlr *dc;
  225. priv->frame_buffer = (u32)default_lcd_base;
  226. dc = (struct dc_ctlr *)priv->disp;
  227. /*
  228. * A header file for clock constants was NAKed upstream.
  229. * TODO: Put this into the FDT and fdt_lcd struct when we have clock
  230. * support there
  231. */
  232. clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
  233. 144 * 1000000);
  234. clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
  235. 600 * 1000000);
  236. basic_init(&dc->cmd);
  237. basic_init_timer(&dc->disp);
  238. rgb_enable(&dc->com);
  239. if (priv->pixel_clock)
  240. update_display_mode(&dc->disp, priv);
  241. if (setup_window(&window, priv))
  242. return -1;
  243. update_window(dc, &window);
  244. return 0;
  245. }
  246. static int tegra_lcd_probe(struct udevice *dev)
  247. {
  248. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  249. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  250. struct tegra_lcd_priv *priv = dev_get_priv(dev);
  251. const void *blob = gd->fdt_blob;
  252. int ret;
  253. /* Initialize the Tegra display controller */
  254. funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
  255. if (tegra_display_probe(blob, priv, (void *)plat->base)) {
  256. printf("%s: Failed to probe display driver\n", __func__);
  257. return -1;
  258. }
  259. pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
  260. pinmux_tristate_disable(PMUX_PINGRP_GPU);
  261. ret = panel_enable_backlight(priv->panel);
  262. if (ret) {
  263. debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
  264. return ret;
  265. }
  266. mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
  267. DCACHE_WRITETHROUGH);
  268. /* Enable flushing after LCD writes if requested */
  269. video_set_flush_dcache(dev, true);
  270. uc_priv->xsize = priv->width;
  271. uc_priv->ysize = priv->height;
  272. uc_priv->bpix = priv->log2_bpp;
  273. debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
  274. plat->size);
  275. return 0;
  276. }
  277. static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
  278. {
  279. struct tegra_lcd_priv *priv = dev_get_priv(dev);
  280. const void *blob = gd->fdt_blob;
  281. struct display_timing *timing;
  282. int node = dev_of_offset(dev);
  283. int panel_node;
  284. int rgb;
  285. int ret;
  286. priv->disp = (struct disp_ctlr *)devfdt_get_addr(dev);
  287. if (!priv->disp) {
  288. debug("%s: No display controller address\n", __func__);
  289. return -EINVAL;
  290. }
  291. rgb = fdt_subnode_offset(blob, node, "rgb");
  292. if (rgb < 0) {
  293. debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
  294. __func__, dev->name, rgb);
  295. return -EINVAL;
  296. }
  297. ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
  298. if (ret) {
  299. debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
  300. __func__, dev->name, ret);
  301. return -EINVAL;
  302. }
  303. timing = &priv->timing;
  304. priv->width = timing->hactive.typ;
  305. priv->height = timing->vactive.typ;
  306. priv->pixel_clock = timing->pixelclock.typ;
  307. priv->log2_bpp = VIDEO_BPP16;
  308. /*
  309. * Sadly the panel phandle is in an rgb subnode so we cannot use
  310. * uclass_get_device_by_phandle().
  311. */
  312. panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
  313. if (panel_node < 0) {
  314. debug("%s: Cannot find panel information\n", __func__);
  315. return -EINVAL;
  316. }
  317. ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
  318. &priv->panel);
  319. if (ret) {
  320. debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
  321. dev->name, ret);
  322. return ret;
  323. }
  324. return 0;
  325. }
  326. static int tegra_lcd_bind(struct udevice *dev)
  327. {
  328. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  329. const void *blob = gd->fdt_blob;
  330. int node = dev_of_offset(dev);
  331. int rgb;
  332. rgb = fdt_subnode_offset(blob, node, "rgb");
  333. if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
  334. return -ENODEV;
  335. plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  336. (1 << LCD_MAX_LOG2_BPP) / 8;
  337. return 0;
  338. }
  339. static const struct video_ops tegra_lcd_ops = {
  340. };
  341. static const struct udevice_id tegra_lcd_ids[] = {
  342. { .compatible = "nvidia,tegra20-dc" },
  343. { }
  344. };
  345. U_BOOT_DRIVER(tegra_lcd) = {
  346. .name = "tegra_lcd",
  347. .id = UCLASS_VIDEO,
  348. .of_match = tegra_lcd_ids,
  349. .ops = &tegra_lcd_ops,
  350. .bind = tegra_lcd_bind,
  351. .probe = tegra_lcd_probe,
  352. .ofdata_to_platdata = tegra_lcd_ofdata_to_platdata,
  353. .priv_auto_alloc_size = sizeof(struct tegra_lcd_priv),
  354. };