sunxi_de2.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Allwinner DE2 display driver
  4. *
  5. * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
  6. */
  7. #include <common.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <edid.h>
  11. #include <efi_loader.h>
  12. #include <fdtdec.h>
  13. #include <fdt_support.h>
  14. #include <part.h>
  15. #include <video.h>
  16. #include <asm/global_data.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/display2.h>
  20. #include <dm/device-internal.h>
  21. #include <dm/uclass-internal.h>
  22. #include "simplefb_common.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. enum {
  25. /* Maximum LCD size we support */
  26. LCD_MAX_WIDTH = 3840,
  27. LCD_MAX_HEIGHT = 2160,
  28. LCD_MAX_LOG2_BPP = VIDEO_BPP32,
  29. };
  30. static void sunxi_de2_composer_init(void)
  31. {
  32. struct sunxi_ccm_reg * const ccm =
  33. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  34. #ifdef CONFIG_MACH_SUN50I
  35. u32 reg_value;
  36. /* set SRAM for video use (A64 only) */
  37. reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
  38. reg_value &= ~(0x01 << 24);
  39. writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
  40. #endif
  41. clock_set_pll10(432000000);
  42. /* Set DE parent to pll10 */
  43. clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
  44. CCM_DE2_CTRL_PLL10);
  45. /* Set ahb gating to pass */
  46. setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
  47. setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
  48. /* Clock on */
  49. setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
  50. }
  51. static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
  52. int bpp, ulong address, bool is_composite)
  53. {
  54. ulong de_mux_base = (mux == 0) ?
  55. SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
  56. struct de_clk * const de_clk_regs =
  57. (struct de_clk *)(SUNXI_DE2_BASE);
  58. struct de_glb * const de_glb_regs =
  59. (struct de_glb *)(de_mux_base +
  60. SUNXI_DE2_MUX_GLB_REGS);
  61. struct de_bld * const de_bld_regs =
  62. (struct de_bld *)(de_mux_base +
  63. SUNXI_DE2_MUX_BLD_REGS);
  64. struct de_ui * const de_ui_regs =
  65. (struct de_ui *)(de_mux_base +
  66. SUNXI_DE2_MUX_CHAN_REGS +
  67. SUNXI_DE2_MUX_CHAN_SZ * 1);
  68. struct de_csc * const de_csc_regs =
  69. (struct de_csc *)(de_mux_base +
  70. SUNXI_DE2_MUX_DCSC_REGS);
  71. u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
  72. int channel;
  73. u32 format;
  74. /* enable clock */
  75. #ifdef CONFIG_MACH_SUN8I_H3
  76. setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
  77. #else
  78. setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
  79. #endif
  80. setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
  81. setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
  82. clrbits_le32(&de_clk_regs->sel_cfg, 1);
  83. writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
  84. writel(0, &de_glb_regs->status);
  85. writel(1, &de_glb_regs->dbuff);
  86. writel(size, &de_glb_regs->size);
  87. for (channel = 0; channel < 4; channel++) {
  88. void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
  89. SUNXI_DE2_MUX_CHAN_SZ * channel);
  90. memset(ch, 0, (channel == 0) ?
  91. sizeof(struct de_vi) : sizeof(struct de_ui));
  92. }
  93. memset(de_bld_regs, 0, sizeof(struct de_bld));
  94. writel(0x00000101, &de_bld_regs->fcolor_ctl);
  95. writel(1, &de_bld_regs->route);
  96. writel(0, &de_bld_regs->premultiply);
  97. writel(0xff000000, &de_bld_regs->bkcolor);
  98. writel(0x03010301, &de_bld_regs->bld_mode[0]);
  99. writel(size, &de_bld_regs->output_size);
  100. writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
  101. &de_bld_regs->out_ctl);
  102. writel(0, &de_bld_regs->ck_ctl);
  103. writel(0xff000000, &de_bld_regs->attr[0].fcolor);
  104. writel(size, &de_bld_regs->attr[0].insize);
  105. /* Disable all other units */
  106. writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
  107. writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
  108. writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
  109. writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
  110. writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
  111. writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
  112. writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
  113. writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
  114. writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
  115. writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
  116. if (is_composite) {
  117. /* set CSC coefficients */
  118. writel(0x107, &de_csc_regs->coef11);
  119. writel(0x204, &de_csc_regs->coef12);
  120. writel(0x64, &de_csc_regs->coef13);
  121. writel(0x4200, &de_csc_regs->coef14);
  122. writel(0x1f68, &de_csc_regs->coef21);
  123. writel(0x1ed6, &de_csc_regs->coef22);
  124. writel(0x1c2, &de_csc_regs->coef23);
  125. writel(0x20200, &de_csc_regs->coef24);
  126. writel(0x1c2, &de_csc_regs->coef31);
  127. writel(0x1e87, &de_csc_regs->coef32);
  128. writel(0x1fb7, &de_csc_regs->coef33);
  129. writel(0x20200, &de_csc_regs->coef34);
  130. /* enable CSC unit */
  131. writel(1, &de_csc_regs->csc_ctl);
  132. } else {
  133. writel(0, &de_csc_regs->csc_ctl);
  134. }
  135. switch (bpp) {
  136. case 16:
  137. format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
  138. break;
  139. case 32:
  140. default:
  141. format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
  142. break;
  143. }
  144. writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
  145. writel(size, &de_ui_regs->cfg[0].size);
  146. writel(0, &de_ui_regs->cfg[0].coord);
  147. writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
  148. writel(address, &de_ui_regs->cfg[0].top_laddr);
  149. writel(size, &de_ui_regs->ovl_size);
  150. /* apply settings */
  151. writel(1, &de_glb_regs->dbuff);
  152. }
  153. static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
  154. enum video_log2_bpp l2bpp,
  155. struct udevice *disp, int mux, bool is_composite)
  156. {
  157. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  158. struct display_timing timing;
  159. struct display_plat *disp_uc_plat;
  160. int ret;
  161. disp_uc_plat = dev_get_uclass_platdata(disp);
  162. debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
  163. if (display_in_use(disp)) {
  164. debug(" - device in use\n");
  165. return -EBUSY;
  166. }
  167. disp_uc_plat->source_id = mux;
  168. ret = device_probe(disp);
  169. if (ret) {
  170. debug("%s: device '%s' display won't probe (ret=%d)\n",
  171. __func__, dev->name, ret);
  172. return ret;
  173. }
  174. ret = display_read_timing(disp, &timing);
  175. if (ret) {
  176. debug("%s: Failed to read timings\n", __func__);
  177. return ret;
  178. }
  179. sunxi_de2_composer_init();
  180. sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
  181. ret = display_enable(disp, 1 << l2bpp, &timing);
  182. if (ret) {
  183. debug("%s: Failed to enable display\n", __func__);
  184. return ret;
  185. }
  186. uc_priv->xsize = timing.hactive.typ;
  187. uc_priv->ysize = timing.vactive.typ;
  188. uc_priv->bpix = l2bpp;
  189. debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
  190. #ifdef CONFIG_EFI_LOADER
  191. efi_add_memory_map(fbbase,
  192. timing.hactive.typ * timing.vactive.typ *
  193. (1 << l2bpp) / 8,
  194. EFI_RESERVED_MEMORY_TYPE);
  195. #endif
  196. return 0;
  197. }
  198. static int sunxi_de2_probe(struct udevice *dev)
  199. {
  200. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  201. struct udevice *disp;
  202. int ret;
  203. /* Before relocation we don't need to do anything */
  204. if (!(gd->flags & GD_FLG_RELOC))
  205. return 0;
  206. ret = uclass_find_device_by_name(UCLASS_DISPLAY,
  207. "sunxi_lcd", &disp);
  208. if (!ret) {
  209. int mux;
  210. mux = 0;
  211. ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
  212. false);
  213. if (!ret) {
  214. video_set_flush_dcache(dev, 1);
  215. return 0;
  216. }
  217. }
  218. debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
  219. ret = uclass_find_device_by_name(UCLASS_DISPLAY,
  220. "sunxi_dw_hdmi", &disp);
  221. if (!ret) {
  222. int mux;
  223. if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
  224. mux = 0;
  225. else
  226. mux = 1;
  227. ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
  228. false);
  229. if (!ret) {
  230. video_set_flush_dcache(dev, 1);
  231. return 0;
  232. }
  233. }
  234. debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
  235. ret = uclass_find_device_by_name(UCLASS_DISPLAY,
  236. "sunxi_tve", &disp);
  237. if (ret) {
  238. debug("%s: tv not found (ret=%d)\n", __func__, ret);
  239. return ret;
  240. }
  241. ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
  242. if (ret)
  243. return ret;
  244. video_set_flush_dcache(dev, 1);
  245. return 0;
  246. }
  247. static int sunxi_de2_bind(struct udevice *dev)
  248. {
  249. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  250. plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  251. (1 << LCD_MAX_LOG2_BPP) / 8;
  252. return 0;
  253. }
  254. static const struct video_ops sunxi_de2_ops = {
  255. };
  256. U_BOOT_DRIVER(sunxi_de2) = {
  257. .name = "sunxi_de2",
  258. .id = UCLASS_VIDEO,
  259. .ops = &sunxi_de2_ops,
  260. .bind = sunxi_de2_bind,
  261. .probe = sunxi_de2_probe,
  262. .flags = DM_FLAG_PRE_RELOC,
  263. };
  264. U_BOOT_DEVICE(sunxi_de2) = {
  265. .name = "sunxi_de2"
  266. };
  267. /*
  268. * Simplefb support.
  269. */
  270. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
  271. int sunxi_simplefb_setup(void *blob)
  272. {
  273. struct udevice *de2, *hdmi, *lcd;
  274. struct video_priv *de2_priv;
  275. struct video_uc_platdata *de2_plat;
  276. int mux;
  277. int offset, ret;
  278. u64 start, size;
  279. const char *pipeline = NULL;
  280. debug("Setting up simplefb\n");
  281. if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
  282. mux = 0;
  283. else
  284. mux = 1;
  285. /* Skip simplefb setting if DE2 / HDMI is not present */
  286. ret = uclass_find_device_by_name(UCLASS_VIDEO,
  287. "sunxi_de2", &de2);
  288. if (ret) {
  289. debug("DE2 not present\n");
  290. return 0;
  291. } else if (!device_active(de2)) {
  292. debug("DE2 present but not probed\n");
  293. return 0;
  294. }
  295. ret = uclass_find_device_by_name(UCLASS_DISPLAY,
  296. "sunxi_dw_hdmi", &hdmi);
  297. if (ret) {
  298. debug("HDMI not present\n");
  299. } else if (device_active(hdmi)) {
  300. if (mux == 0)
  301. pipeline = "mixer0-lcd0-hdmi";
  302. else
  303. pipeline = "mixer1-lcd1-hdmi";
  304. } else {
  305. debug("HDMI present but not probed\n");
  306. }
  307. ret = uclass_find_device_by_name(UCLASS_DISPLAY,
  308. "sunxi_lcd", &lcd);
  309. if (ret)
  310. debug("LCD not present\n");
  311. else if (device_active(lcd))
  312. pipeline = "mixer0-lcd0";
  313. else
  314. debug("LCD present but not probed\n");
  315. if (!pipeline) {
  316. debug("No active display present\n");
  317. return 0;
  318. }
  319. de2_priv = dev_get_uclass_priv(de2);
  320. de2_plat = dev_get_uclass_platdata(de2);
  321. offset = sunxi_simplefb_fdt_match(blob, pipeline);
  322. if (offset < 0) {
  323. eprintf("Cannot setup simplefb: node not found\n");
  324. return 0; /* Keep older kernels working */
  325. }
  326. start = gd->bd->bi_dram[0].start;
  327. size = de2_plat->base - start;
  328. ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
  329. if (ret) {
  330. eprintf("Cannot setup simplefb: Error reserving memory\n");
  331. return ret;
  332. }
  333. ret = fdt_setup_simplefb_node(blob, offset, de2_plat->base,
  334. de2_priv->xsize, de2_priv->ysize,
  335. VNBYTES(de2_priv->bpix) * de2_priv->xsize,
  336. "x8r8g8b8");
  337. if (ret)
  338. eprintf("Cannot setup simplefb: Error setting properties\n");
  339. return ret;
  340. }
  341. #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */