meson_vclk.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic Meson Video Processing Unit driver
  4. *
  5. * Copyright (c) 2018 BayLibre, SAS.
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <edid.h>
  11. #include "meson_vpu.h"
  12. #include <linux/iopoll.h>
  13. #include <linux/math64.h>
  14. #define writel_bits(mask, val, addr) \
  15. writel((readl(addr) & ~(mask)) | (val), addr)
  16. enum {
  17. MESON_VCLK_TARGET_CVBS = 0,
  18. MESON_VCLK_TARGET_HDMI = 1,
  19. MESON_VCLK_TARGET_DMT = 2,
  20. };
  21. /* HHI Registers */
  22. #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
  23. #define VID_PLL_EN BIT(19)
  24. #define VID_PLL_BYPASS BIT(18)
  25. #define VID_PLL_PRESET BIT(15)
  26. #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
  27. #define VCLK2_DIV_MASK 0xff
  28. #define VCLK2_DIV_EN BIT(16)
  29. #define VCLK2_DIV_RESET BIT(17)
  30. #define CTS_VDAC_SEL_MASK (0xf << 28)
  31. #define CTS_VDAC_SEL_SHIFT 28
  32. #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
  33. #define VCLK2_EN BIT(19)
  34. #define VCLK2_SEL_MASK (0x7 << 16)
  35. #define VCLK2_SEL_SHIFT 16
  36. #define VCLK2_SOFT_RESET BIT(15)
  37. #define VCLK2_DIV1_EN BIT(0)
  38. #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
  39. #define VCLK_DIV_MASK 0xff
  40. #define VCLK_DIV_EN BIT(16)
  41. #define VCLK_DIV_RESET BIT(17)
  42. #define CTS_ENCP_SEL_MASK (0xf << 24)
  43. #define CTS_ENCP_SEL_SHIFT 24
  44. #define CTS_ENCI_SEL_MASK (0xf << 28)
  45. #define CTS_ENCI_SEL_SHIFT 28
  46. #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
  47. #define VCLK_EN BIT(19)
  48. #define VCLK_SEL_MASK (0x7 << 16)
  49. #define VCLK_SEL_SHIFT 16
  50. #define VCLK_SOFT_RESET BIT(15)
  51. #define VCLK_DIV1_EN BIT(0)
  52. #define VCLK_DIV2_EN BIT(1)
  53. #define VCLK_DIV4_EN BIT(2)
  54. #define VCLK_DIV6_EN BIT(3)
  55. #define VCLK_DIV12_EN BIT(4)
  56. #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
  57. #define CTS_ENCI_EN BIT(0)
  58. #define CTS_ENCP_EN BIT(2)
  59. #define CTS_VDAC_EN BIT(4)
  60. #define HDMI_TX_PIXEL_EN BIT(5)
  61. #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
  62. #define HDMI_TX_PIXEL_SEL_MASK (0xf << 16)
  63. #define HDMI_TX_PIXEL_SEL_SHIFT 16
  64. #define CTS_HDMI_SYS_SEL_MASK (0x7 << 9)
  65. #define CTS_HDMI_SYS_DIV_MASK (0x7f)
  66. #define CTS_HDMI_SYS_EN BIT(8)
  67. #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
  68. #define HHI_HDMI_PLL_CNTL_EN BIT(30)
  69. #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
  70. #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
  71. #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
  72. #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
  73. #define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
  74. #define HHI_HDMI_PLL_CNTL7 0x338 /* 0xce offset in data sheet */
  75. #define HDMI_PLL_RESET BIT(28)
  76. #define HDMI_PLL_RESET_G12A BIT(29)
  77. #define HDMI_PLL_LOCK BIT(31)
  78. #define HDMI_PLL_LOCK_G12A (3 << 30)
  79. #define FREQ_1000_1001(_freq) DIV_ROUND_CLOSEST(_freq * 1000, 1001)
  80. /* VID PLL Dividers */
  81. enum {
  82. VID_PLL_DIV_1 = 0,
  83. VID_PLL_DIV_2,
  84. VID_PLL_DIV_2p5,
  85. VID_PLL_DIV_3,
  86. VID_PLL_DIV_3p5,
  87. VID_PLL_DIV_3p75,
  88. VID_PLL_DIV_4,
  89. VID_PLL_DIV_5,
  90. VID_PLL_DIV_6,
  91. VID_PLL_DIV_6p25,
  92. VID_PLL_DIV_7,
  93. VID_PLL_DIV_7p5,
  94. VID_PLL_DIV_12,
  95. VID_PLL_DIV_14,
  96. VID_PLL_DIV_15,
  97. };
  98. void meson_vid_pll_set(struct meson_vpu_priv *priv, unsigned int div)
  99. {
  100. unsigned int shift_val = 0;
  101. unsigned int shift_sel = 0;
  102. /* Disable vid_pll output clock */
  103. hhi_update_bits(HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
  104. hhi_update_bits(HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
  105. switch (div) {
  106. case VID_PLL_DIV_2:
  107. shift_val = 0x0aaa;
  108. shift_sel = 0;
  109. break;
  110. case VID_PLL_DIV_2p5:
  111. shift_val = 0x5294;
  112. shift_sel = 2;
  113. break;
  114. case VID_PLL_DIV_3:
  115. shift_val = 0x0db6;
  116. shift_sel = 0;
  117. break;
  118. case VID_PLL_DIV_3p5:
  119. shift_val = 0x36cc;
  120. shift_sel = 1;
  121. break;
  122. case VID_PLL_DIV_3p75:
  123. shift_val = 0x6666;
  124. shift_sel = 2;
  125. break;
  126. case VID_PLL_DIV_4:
  127. shift_val = 0x0ccc;
  128. shift_sel = 0;
  129. break;
  130. case VID_PLL_DIV_5:
  131. shift_val = 0x739c;
  132. shift_sel = 2;
  133. break;
  134. case VID_PLL_DIV_6:
  135. shift_val = 0x0e38;
  136. shift_sel = 0;
  137. break;
  138. case VID_PLL_DIV_6p25:
  139. shift_val = 0x0000;
  140. shift_sel = 3;
  141. break;
  142. case VID_PLL_DIV_7:
  143. shift_val = 0x3c78;
  144. shift_sel = 1;
  145. break;
  146. case VID_PLL_DIV_7p5:
  147. shift_val = 0x78f0;
  148. shift_sel = 2;
  149. break;
  150. case VID_PLL_DIV_12:
  151. shift_val = 0x0fc0;
  152. shift_sel = 0;
  153. break;
  154. case VID_PLL_DIV_14:
  155. shift_val = 0x3f80;
  156. shift_sel = 1;
  157. break;
  158. case VID_PLL_DIV_15:
  159. shift_val = 0x7f80;
  160. shift_sel = 2;
  161. break;
  162. }
  163. if (div == VID_PLL_DIV_1) {
  164. /* Enable vid_pll bypass to HDMI pll */
  165. hhi_update_bits(HHI_VID_PLL_CLK_DIV,
  166. VID_PLL_BYPASS, VID_PLL_BYPASS);
  167. } else {
  168. /* Disable Bypass */
  169. hhi_update_bits(HHI_VID_PLL_CLK_DIV,
  170. VID_PLL_BYPASS, 0);
  171. /* Clear sel */
  172. hhi_update_bits(HHI_VID_PLL_CLK_DIV,
  173. 3 << 16, 0);
  174. hhi_update_bits(HHI_VID_PLL_CLK_DIV,
  175. VID_PLL_PRESET, 0);
  176. hhi_update_bits(HHI_VID_PLL_CLK_DIV,
  177. 0x7fff, 0);
  178. /* Setup sel and val */
  179. hhi_update_bits(HHI_VID_PLL_CLK_DIV,
  180. 3 << 16, shift_sel << 16);
  181. hhi_update_bits(HHI_VID_PLL_CLK_DIV,
  182. VID_PLL_PRESET, VID_PLL_PRESET);
  183. hhi_update_bits(HHI_VID_PLL_CLK_DIV,
  184. 0x7fff, shift_val);
  185. hhi_update_bits(HHI_VID_PLL_CLK_DIV,
  186. VID_PLL_PRESET, 0);
  187. }
  188. /* Enable the vid_pll output clock */
  189. hhi_update_bits(HHI_VID_PLL_CLK_DIV,
  190. VID_PLL_EN, VID_PLL_EN);
  191. }
  192. /*
  193. * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
  194. *
  195. * TOFIX: Refactor into table to also handle HDMI frequency and paths
  196. */
  197. static void meson_venci_cvbs_clock_config(struct meson_vpu_priv *priv)
  198. {
  199. unsigned int val;
  200. /* Setup PLL to output 1.485GHz */
  201. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
  202. hhi_write(HHI_HDMI_PLL_CNTL, 0x5800023d);
  203. hhi_write(HHI_HDMI_PLL_CNTL2, 0x00404e00);
  204. hhi_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
  205. hhi_write(HHI_HDMI_PLL_CNTL4, 0x801da72c);
  206. hhi_write(HHI_HDMI_PLL_CNTL5, 0x71486980);
  207. hhi_write(HHI_HDMI_PLL_CNTL6, 0x00000e55);
  208. hhi_write(HHI_HDMI_PLL_CNTL, 0x4800023d);
  209. /* Poll for lock bit */
  210. readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
  211. (val & HDMI_PLL_LOCK), 10);
  212. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  213. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
  214. hhi_write(HHI_HDMI_PLL_CNTL, 0x4000027b);
  215. hhi_write(HHI_HDMI_PLL_CNTL2, 0x800cb300);
  216. hhi_write(HHI_HDMI_PLL_CNTL3, 0xa6212844);
  217. hhi_write(HHI_HDMI_PLL_CNTL4, 0x0c4d000c);
  218. hhi_write(HHI_HDMI_PLL_CNTL5, 0x001fa729);
  219. hhi_write(HHI_HDMI_PLL_CNTL6, 0x01a31500);
  220. /* Reset PLL */
  221. hhi_update_bits(HHI_HDMI_PLL_CNTL,
  222. HDMI_PLL_RESET, HDMI_PLL_RESET);
  223. hhi_update_bits(HHI_HDMI_PLL_CNTL,
  224. HDMI_PLL_RESET, 0);
  225. /* Poll for lock bit */
  226. readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
  227. (val & HDMI_PLL_LOCK), 10);
  228. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  229. hhi_write(HHI_HDMI_PLL_CNTL, 0x1a0504f7);
  230. hhi_write(HHI_HDMI_PLL_CNTL2, 0x00010000);
  231. hhi_write(HHI_HDMI_PLL_CNTL3, 0x00000000);
  232. hhi_write(HHI_HDMI_PLL_CNTL4, 0x6a28dc00);
  233. hhi_write(HHI_HDMI_PLL_CNTL5, 0x65771290);
  234. hhi_write(HHI_HDMI_PLL_CNTL6, 0x39272000);
  235. hhi_write(HHI_HDMI_PLL_CNTL7, 0x56540000);
  236. hhi_write(HHI_HDMI_PLL_CNTL, 0x3a0504f7);
  237. hhi_write(HHI_HDMI_PLL_CNTL, 0x1a0504f7);
  238. /* Poll for lock bit */
  239. readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
  240. ((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
  241. 10);
  242. }
  243. /* Disable VCLK2 */
  244. hhi_update_bits(HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
  245. /* Setup vid_pll to /1 */
  246. meson_vid_pll_set(priv, VID_PLL_DIV_1);
  247. /* Setup the VCLK2 divider value to achieve 27MHz */
  248. hhi_update_bits(HHI_VIID_CLK_DIV,
  249. VCLK2_DIV_MASK, (55 - 1));
  250. /* select vid_pll for vclk2 */
  251. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  252. hhi_update_bits(HHI_VIID_CLK_CNTL,
  253. VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
  254. else
  255. hhi_update_bits(HHI_VIID_CLK_CNTL,
  256. VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
  257. /* enable vclk2 gate */
  258. hhi_update_bits(HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
  259. /* select vclk_div1 for enci */
  260. hhi_update_bits(HHI_VID_CLK_DIV,
  261. CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
  262. /* select vclk_div1 for vdac */
  263. hhi_update_bits(HHI_VIID_CLK_DIV,
  264. CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
  265. /* release vclk2_div_reset and enable vclk2_div */
  266. hhi_update_bits(HHI_VIID_CLK_DIV,
  267. VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
  268. /* enable vclk2_div1 gate */
  269. hhi_update_bits(HHI_VIID_CLK_CNTL,
  270. VCLK2_DIV1_EN, VCLK2_DIV1_EN);
  271. /* reset vclk2 */
  272. hhi_update_bits(HHI_VIID_CLK_CNTL,
  273. VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
  274. hhi_update_bits(HHI_VIID_CLK_CNTL,
  275. VCLK2_SOFT_RESET, 0);
  276. /* enable enci_clk */
  277. hhi_update_bits(HHI_VID_CLK_CNTL2,
  278. CTS_ENCI_EN, CTS_ENCI_EN);
  279. /* enable vdac_clk */
  280. hhi_update_bits(HHI_VID_CLK_CNTL2,
  281. CTS_VDAC_EN, CTS_VDAC_EN);
  282. }
  283. enum {
  284. /* PLL O1 O2 O3 VP DV EN TX */
  285. /* 4320 /4 /4 /1 /5 /1 => /2 /2 */
  286. MESON_VCLK_HDMI_ENCI_54000 = 0,
  287. /* 4320 /4 /4 /1 /5 /1 => /1 /2 */
  288. MESON_VCLK_HDMI_DDR_54000,
  289. /* 2970 /4 /1 /1 /5 /1 => /1 /2 */
  290. MESON_VCLK_HDMI_DDR_148500,
  291. /* 2970 /2 /2 /2 /5 /1 => /1 /1 */
  292. MESON_VCLK_HDMI_74250,
  293. /* 2970 /1 /2 /2 /5 /1 => /1 /1 */
  294. MESON_VCLK_HDMI_148500,
  295. /* 2970 /1 /1 /1 /5 /2 => /1 /1 */
  296. MESON_VCLK_HDMI_297000,
  297. /* 5940 /1 /1 /2 /5 /1 => /1 /1 */
  298. MESON_VCLK_HDMI_594000
  299. };
  300. struct meson_vclk_params {
  301. unsigned int pixel_freq;
  302. unsigned int pll_base_freq;
  303. unsigned int pll_od1;
  304. unsigned int pll_od2;
  305. unsigned int pll_od3;
  306. unsigned int vid_pll_div;
  307. unsigned int vclk_div;
  308. } params[] = {
  309. [MESON_VCLK_HDMI_ENCI_54000] = {
  310. .pixel_freq = 54000,
  311. .pll_base_freq = 4320000,
  312. .pll_od1 = 4,
  313. .pll_od2 = 4,
  314. .pll_od3 = 1,
  315. .vid_pll_div = VID_PLL_DIV_5,
  316. .vclk_div = 1,
  317. },
  318. [MESON_VCLK_HDMI_DDR_54000] = {
  319. .pixel_freq = 54000,
  320. .pll_base_freq = 4320000,
  321. .pll_od1 = 4,
  322. .pll_od2 = 4,
  323. .pll_od3 = 1,
  324. .vid_pll_div = VID_PLL_DIV_5,
  325. .vclk_div = 1,
  326. },
  327. [MESON_VCLK_HDMI_DDR_148500] = {
  328. .pixel_freq = 148500,
  329. .pll_base_freq = 2970000,
  330. .pll_od1 = 4,
  331. .pll_od2 = 1,
  332. .pll_od3 = 1,
  333. .vid_pll_div = VID_PLL_DIV_5,
  334. .vclk_div = 1,
  335. },
  336. [MESON_VCLK_HDMI_74250] = {
  337. .pixel_freq = 74250,
  338. .pll_base_freq = 2970000,
  339. .pll_od1 = 2,
  340. .pll_od2 = 2,
  341. .pll_od3 = 2,
  342. .vid_pll_div = VID_PLL_DIV_5,
  343. .vclk_div = 1,
  344. },
  345. [MESON_VCLK_HDMI_148500] = {
  346. .pixel_freq = 148500,
  347. .pll_base_freq = 2970000,
  348. .pll_od1 = 1,
  349. .pll_od2 = 2,
  350. .pll_od3 = 2,
  351. .vid_pll_div = VID_PLL_DIV_5,
  352. .vclk_div = 1,
  353. },
  354. [MESON_VCLK_HDMI_297000] = {
  355. .pixel_freq = 297000,
  356. .pll_base_freq = 5940000,
  357. .pll_od1 = 2,
  358. .pll_od2 = 1,
  359. .pll_od3 = 1,
  360. .vid_pll_div = VID_PLL_DIV_5,
  361. .vclk_div = 2,
  362. },
  363. [MESON_VCLK_HDMI_594000] = {
  364. .pixel_freq = 594000,
  365. .pll_base_freq = 5940000,
  366. .pll_od1 = 1,
  367. .pll_od2 = 1,
  368. .pll_od3 = 2,
  369. .vid_pll_div = VID_PLL_DIV_5,
  370. .vclk_div = 1,
  371. },
  372. { /* sentinel */ },
  373. };
  374. static inline unsigned int pll_od_to_reg(unsigned int od)
  375. {
  376. switch (od) {
  377. case 1:
  378. return 0;
  379. case 2:
  380. return 1;
  381. case 4:
  382. return 2;
  383. case 8:
  384. return 3;
  385. }
  386. /* Invalid */
  387. return 0;
  388. }
  389. void meson_hdmi_pll_set_params(struct meson_vpu_priv *priv, unsigned int m,
  390. unsigned int frac, unsigned int od1,
  391. unsigned int od2, unsigned int od3)
  392. {
  393. unsigned int val;
  394. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
  395. hhi_write(HHI_HDMI_PLL_CNTL, 0x58000200 | m);
  396. if (frac)
  397. hhi_write(HHI_HDMI_PLL_CNTL2,
  398. 0x00004000 | frac);
  399. else
  400. hhi_write(HHI_HDMI_PLL_CNTL2,
  401. 0x00000000);
  402. hhi_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
  403. hhi_write(HHI_HDMI_PLL_CNTL4, 0x801da72c);
  404. hhi_write(HHI_HDMI_PLL_CNTL5, 0x71486980);
  405. hhi_write(HHI_HDMI_PLL_CNTL6, 0x00000e55);
  406. /* Enable and unreset */
  407. hhi_update_bits(HHI_HDMI_PLL_CNTL,
  408. 0x7 << 28, 0x4 << 28);
  409. /* Poll for lock bit */
  410. readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
  411. (val & HDMI_PLL_LOCK), 10);
  412. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  413. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
  414. hhi_write(HHI_HDMI_PLL_CNTL, 0x40000200 | m);
  415. hhi_write(HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
  416. hhi_write(HHI_HDMI_PLL_CNTL3, 0x860f30c4);
  417. hhi_write(HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
  418. hhi_write(HHI_HDMI_PLL_CNTL5, 0x001fa729);
  419. hhi_write(HHI_HDMI_PLL_CNTL6, 0x01a31500);
  420. /* Reset PLL */
  421. hhi_update_bits(HHI_HDMI_PLL_CNTL,
  422. HDMI_PLL_RESET, HDMI_PLL_RESET);
  423. hhi_update_bits(HHI_HDMI_PLL_CNTL,
  424. HDMI_PLL_RESET, 0);
  425. /* Poll for lock bit */
  426. readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
  427. (val & HDMI_PLL_LOCK), 10);
  428. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  429. hhi_write(HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
  430. /* Enable and reset */
  431. hhi_update_bits(HHI_HDMI_PLL_CNTL, 0x3 << 28, 0x3 << 28);
  432. hhi_write(HHI_HDMI_PLL_CNTL2, frac);
  433. hhi_write(HHI_HDMI_PLL_CNTL3, 0x00000000);
  434. /* G12A HDMI PLL Needs specific parameters for 5.4GHz */
  435. if (m >= 0xf7) {
  436. if (frac < 0x10000) {
  437. hhi_write(HHI_HDMI_PLL_CNTL4, 0x6a685c00);
  438. hhi_write(HHI_HDMI_PLL_CNTL5, 0x11551293);
  439. } else {
  440. hhi_write(HHI_HDMI_PLL_CNTL4, 0xea68dc00);
  441. hhi_write(HHI_HDMI_PLL_CNTL5, 0x65771290);
  442. }
  443. hhi_write(HHI_HDMI_PLL_CNTL6, 0x39272000);
  444. hhi_write(HHI_HDMI_PLL_CNTL7, 0x55540000);
  445. } else {
  446. hhi_write(HHI_HDMI_PLL_CNTL4, 0x0a691c00);
  447. hhi_write(HHI_HDMI_PLL_CNTL5, 0x33771290);
  448. hhi_write(HHI_HDMI_PLL_CNTL6, 0x39270000);
  449. hhi_write(HHI_HDMI_PLL_CNTL7, 0x50540000);
  450. }
  451. do {
  452. /* Reset PLL */
  453. hhi_update_bits(HHI_HDMI_PLL_CNTL,
  454. HDMI_PLL_RESET_G12A,
  455. HDMI_PLL_RESET_G12A);
  456. /* UN-Reset PLL */
  457. hhi_update_bits(HHI_HDMI_PLL_CNTL,
  458. HDMI_PLL_RESET_G12A, 0);
  459. /* Poll for lock bits */
  460. if (!readl_poll_timeout(
  461. priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
  462. ((val & HDMI_PLL_LOCK_G12A)
  463. == HDMI_PLL_LOCK_G12A), 100))
  464. break;
  465. } while (1);
  466. }
  467. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
  468. hhi_update_bits(HHI_HDMI_PLL_CNTL2,
  469. 3 << 16, pll_od_to_reg(od1) << 16);
  470. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  471. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
  472. hhi_update_bits(HHI_HDMI_PLL_CNTL3,
  473. 3 << 21, pll_od_to_reg(od1) << 21);
  474. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  475. hhi_update_bits(HHI_HDMI_PLL_CNTL,
  476. 3 << 16, pll_od_to_reg(od1) << 16);
  477. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
  478. hhi_update_bits(HHI_HDMI_PLL_CNTL2,
  479. 3 << 22, pll_od_to_reg(od2) << 22);
  480. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  481. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
  482. hhi_update_bits(HHI_HDMI_PLL_CNTL3,
  483. 3 << 23, pll_od_to_reg(od2) << 23);
  484. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  485. hhi_update_bits(HHI_HDMI_PLL_CNTL,
  486. 3 << 18, pll_od_to_reg(od2) << 18);
  487. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
  488. hhi_update_bits(HHI_HDMI_PLL_CNTL2,
  489. 3 << 18, pll_od_to_reg(od3) << 18);
  490. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  491. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
  492. hhi_update_bits(HHI_HDMI_PLL_CNTL3,
  493. 3 << 19, pll_od_to_reg(od3) << 19);
  494. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  495. hhi_update_bits(HHI_HDMI_PLL_CNTL,
  496. 3 << 20, pll_od_to_reg(od3) << 20);
  497. }
  498. #define XTAL_FREQ 24000
  499. static unsigned int meson_hdmi_pll_get_m(struct meson_vpu_priv *priv,
  500. unsigned int pll_freq)
  501. {
  502. /* The GXBB PLL has a /2 pre-multiplier */
  503. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
  504. pll_freq /= 2;
  505. return pll_freq / XTAL_FREQ;
  506. }
  507. #define HDMI_FRAC_MAX_GXBB 4096
  508. #define HDMI_FRAC_MAX_GXL 1024
  509. #define HDMI_FRAC_MAX_G12A 131072
  510. static unsigned int meson_hdmi_pll_get_frac(struct meson_vpu_priv *priv,
  511. unsigned int m,
  512. unsigned int pll_freq)
  513. {
  514. unsigned int parent_freq = XTAL_FREQ;
  515. unsigned int frac_max = HDMI_FRAC_MAX_GXL;
  516. unsigned int frac_m;
  517. unsigned int frac;
  518. /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */
  519. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
  520. frac_max = HDMI_FRAC_MAX_GXBB;
  521. parent_freq *= 2;
  522. }
  523. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  524. frac_max = HDMI_FRAC_MAX_G12A;
  525. /* We can have a perfect match !*/
  526. if (pll_freq / m == parent_freq &&
  527. pll_freq % m == 0)
  528. return 0;
  529. frac = div_u64((u64)pll_freq * (u64)frac_max, parent_freq);
  530. frac_m = m * frac_max;
  531. if (frac_m > frac)
  532. return frac_max;
  533. frac -= frac_m;
  534. return min((u16)frac, (u16)(frac_max - 1));
  535. }
  536. static bool meson_hdmi_pll_validate_params(struct meson_vpu_priv *priv,
  537. unsigned int m,
  538. unsigned int frac)
  539. {
  540. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
  541. /* Empiric supported min/max dividers */
  542. if (m < 53 || m > 123)
  543. return false;
  544. if (frac >= HDMI_FRAC_MAX_GXBB)
  545. return false;
  546. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  547. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
  548. /* Empiric supported min/max dividers */
  549. if (m < 106 || m > 247)
  550. return false;
  551. if (frac >= HDMI_FRAC_MAX_GXL)
  552. return false;
  553. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  554. /* Empiric supported min/max dividers */
  555. if (m < 106 || m > 247)
  556. return false;
  557. if (frac >= HDMI_FRAC_MAX_G12A)
  558. return false;
  559. }
  560. return true;
  561. }
  562. static bool meson_hdmi_pll_find_params(struct meson_vpu_priv *priv,
  563. unsigned int freq,
  564. unsigned int *m,
  565. unsigned int *frac,
  566. unsigned int *od)
  567. {
  568. /* Cycle from /16 to /2 */
  569. for (*od = 16 ; *od > 1 ; *od >>= 1) {
  570. *m = meson_hdmi_pll_get_m(priv, freq * *od);
  571. if (!*m)
  572. continue;
  573. *frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);
  574. debug("PLL params for %dkHz: m=%x frac=%x od=%d\n",
  575. freq, *m, *frac, *od);
  576. if (meson_hdmi_pll_validate_params(priv, *m, *frac))
  577. return true;
  578. }
  579. return false;
  580. }
  581. /* pll_freq is the frequency after the OD dividers */
  582. bool meson_vclk_dmt_supported_freq(struct meson_vpu_priv *priv,
  583. unsigned int freq)
  584. {
  585. unsigned int od, m, frac;
  586. /* In DMT mode, path after PLL is always /10 */
  587. freq *= 10;
  588. if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
  589. return true;
  590. return false;
  591. }
  592. /* pll_freq is the frequency after the OD dividers */
  593. static void meson_hdmi_pll_generic_set(struct meson_vpu_priv *priv,
  594. unsigned int pll_freq)
  595. {
  596. unsigned int od, m, frac, od1, od2, od3;
  597. if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
  598. od3 = 1;
  599. if (od < 4) {
  600. od1 = 2;
  601. od2 = 1;
  602. } else {
  603. od2 = od / 4;
  604. od1 = od / od2;
  605. }
  606. debug("PLL params for %dkHz: m=%x frac=%x od=%d/%d/%d\n",
  607. pll_freq, m, frac, od1, od2, od3);
  608. meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
  609. return;
  610. }
  611. printf("Fatal, unable to find parameters for PLL freq %d\n",
  612. pll_freq);
  613. }
  614. static void
  615. meson_vclk_set(struct meson_vpu_priv *priv, unsigned int pll_base_freq,
  616. unsigned int od1, unsigned int od2, unsigned int od3,
  617. unsigned int vid_pll_div, unsigned int vclk_div,
  618. unsigned int hdmi_tx_div, unsigned int venc_div,
  619. bool hdmi_use_enci, bool vic_alternate_clock)
  620. {
  621. unsigned int m = 0, frac = 0;
  622. /* Set HDMI-TX sys clock */
  623. hhi_update_bits(HHI_HDMI_CLK_CNTL,
  624. CTS_HDMI_SYS_SEL_MASK, 0);
  625. hhi_update_bits(HHI_HDMI_CLK_CNTL,
  626. CTS_HDMI_SYS_DIV_MASK, 0);
  627. hhi_update_bits(HHI_HDMI_CLK_CNTL,
  628. CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
  629. /* Set HDMI PLL rate */
  630. if (!od1 && !od2 && !od3) {
  631. meson_hdmi_pll_generic_set(priv, pll_base_freq);
  632. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
  633. switch (pll_base_freq) {
  634. case 2970000:
  635. m = 0x3d;
  636. frac = vic_alternate_clock ? 0xd02 : 0xe00;
  637. break;
  638. case 4320000:
  639. m = vic_alternate_clock ? 0x59 : 0x5a;
  640. frac = vic_alternate_clock ? 0xe8f : 0;
  641. break;
  642. case 5940000:
  643. m = 0x7b;
  644. frac = vic_alternate_clock ? 0xa05 : 0xc00;
  645. break;
  646. }
  647. meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
  648. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  649. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
  650. switch (pll_base_freq) {
  651. case 2970000:
  652. m = 0x7b;
  653. frac = vic_alternate_clock ? 0x281 : 0x300;
  654. break;
  655. case 4320000:
  656. m = vic_alternate_clock ? 0xb3 : 0xb4;
  657. frac = vic_alternate_clock ? 0x347 : 0;
  658. break;
  659. case 5940000:
  660. m = 0xf7;
  661. frac = vic_alternate_clock ? 0x102 : 0x200;
  662. break;
  663. }
  664. meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
  665. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  666. switch (pll_base_freq) {
  667. case 2970000:
  668. m = 0x7b;
  669. frac = vic_alternate_clock ? 0x140b4 : 0x18000;
  670. break;
  671. case 4320000:
  672. m = vic_alternate_clock ? 0xb3 : 0xb4;
  673. frac = vic_alternate_clock ? 0x1a3ee : 0;
  674. break;
  675. case 5940000:
  676. m = 0xf7;
  677. frac = vic_alternate_clock ? 0x8148 : 0x10000;
  678. break;
  679. }
  680. meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
  681. }
  682. /* Setup vid_pll divider */
  683. meson_vid_pll_set(priv, vid_pll_div);
  684. /* Set VCLK div */
  685. hhi_update_bits(HHI_VID_CLK_CNTL,
  686. VCLK_SEL_MASK, 0);
  687. hhi_update_bits(HHI_VID_CLK_DIV,
  688. VCLK_DIV_MASK, vclk_div - 1);
  689. /* Set HDMI-TX source */
  690. switch (hdmi_tx_div) {
  691. case 1:
  692. /* enable vclk_div1 gate */
  693. hhi_update_bits(HHI_VID_CLK_CNTL,
  694. VCLK_DIV1_EN, VCLK_DIV1_EN);
  695. /* select vclk_div1 for HDMI-TX */
  696. hhi_update_bits(HHI_HDMI_CLK_CNTL,
  697. HDMI_TX_PIXEL_SEL_MASK, 0);
  698. break;
  699. case 2:
  700. /* enable vclk_div2 gate */
  701. hhi_update_bits(HHI_VID_CLK_CNTL,
  702. VCLK_DIV2_EN, VCLK_DIV2_EN);
  703. /* select vclk_div2 for HDMI-TX */
  704. hhi_update_bits(HHI_HDMI_CLK_CNTL,
  705. HDMI_TX_PIXEL_SEL_MASK,
  706. 1 << HDMI_TX_PIXEL_SEL_SHIFT);
  707. break;
  708. case 4:
  709. /* enable vclk_div4 gate */
  710. hhi_update_bits(HHI_VID_CLK_CNTL,
  711. VCLK_DIV4_EN, VCLK_DIV4_EN);
  712. /* select vclk_div4 for HDMI-TX */
  713. hhi_update_bits(HHI_HDMI_CLK_CNTL,
  714. HDMI_TX_PIXEL_SEL_MASK,
  715. 2 << HDMI_TX_PIXEL_SEL_SHIFT);
  716. break;
  717. case 6:
  718. /* enable vclk_div6 gate */
  719. hhi_update_bits(HHI_VID_CLK_CNTL,
  720. VCLK_DIV6_EN, VCLK_DIV6_EN);
  721. /* select vclk_div6 for HDMI-TX */
  722. hhi_update_bits(HHI_HDMI_CLK_CNTL,
  723. HDMI_TX_PIXEL_SEL_MASK,
  724. 3 << HDMI_TX_PIXEL_SEL_SHIFT);
  725. break;
  726. case 12:
  727. /* enable vclk_div12 gate */
  728. hhi_update_bits(HHI_VID_CLK_CNTL,
  729. VCLK_DIV12_EN, VCLK_DIV12_EN);
  730. /* select vclk_div12 for HDMI-TX */
  731. hhi_update_bits(HHI_HDMI_CLK_CNTL,
  732. HDMI_TX_PIXEL_SEL_MASK,
  733. 4 << HDMI_TX_PIXEL_SEL_SHIFT);
  734. break;
  735. }
  736. hhi_update_bits(HHI_VID_CLK_CNTL2,
  737. HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
  738. /* Set ENCI/ENCP Source */
  739. switch (venc_div) {
  740. case 1:
  741. /* enable vclk_div1 gate */
  742. hhi_update_bits(HHI_VID_CLK_CNTL,
  743. VCLK_DIV1_EN, VCLK_DIV1_EN);
  744. if (hdmi_use_enci)
  745. /* select vclk_div1 for enci */
  746. hhi_update_bits(HHI_VID_CLK_DIV,
  747. CTS_ENCI_SEL_MASK, 0);
  748. else
  749. /* select vclk_div1 for encp */
  750. hhi_update_bits(HHI_VID_CLK_DIV,
  751. CTS_ENCP_SEL_MASK, 0);
  752. break;
  753. case 2:
  754. /* enable vclk_div2 gate */
  755. hhi_update_bits(HHI_VID_CLK_CNTL,
  756. VCLK_DIV2_EN, VCLK_DIV2_EN);
  757. if (hdmi_use_enci)
  758. /* select vclk_div2 for enci */
  759. hhi_update_bits(HHI_VID_CLK_DIV,
  760. CTS_ENCI_SEL_MASK,
  761. 1 << CTS_ENCI_SEL_SHIFT);
  762. else
  763. /* select vclk_div2 for encp */
  764. hhi_update_bits(HHI_VID_CLK_DIV,
  765. CTS_ENCP_SEL_MASK,
  766. 1 << CTS_ENCP_SEL_SHIFT);
  767. break;
  768. case 4:
  769. /* enable vclk_div4 gate */
  770. hhi_update_bits(HHI_VID_CLK_CNTL,
  771. VCLK_DIV4_EN, VCLK_DIV4_EN);
  772. if (hdmi_use_enci)
  773. /* select vclk_div4 for enci */
  774. hhi_update_bits(HHI_VID_CLK_DIV,
  775. CTS_ENCI_SEL_MASK,
  776. 2 << CTS_ENCI_SEL_SHIFT);
  777. else
  778. /* select vclk_div4 for encp */
  779. hhi_update_bits(HHI_VID_CLK_DIV,
  780. CTS_ENCP_SEL_MASK,
  781. 2 << CTS_ENCP_SEL_SHIFT);
  782. break;
  783. case 6:
  784. /* enable vclk_div6 gate */
  785. hhi_update_bits(HHI_VID_CLK_CNTL,
  786. VCLK_DIV6_EN, VCLK_DIV6_EN);
  787. if (hdmi_use_enci)
  788. /* select vclk_div6 for enci */
  789. hhi_update_bits(HHI_VID_CLK_DIV,
  790. CTS_ENCI_SEL_MASK,
  791. 3 << CTS_ENCI_SEL_SHIFT);
  792. else
  793. /* select vclk_div6 for encp */
  794. hhi_update_bits(HHI_VID_CLK_DIV,
  795. CTS_ENCP_SEL_MASK,
  796. 3 << CTS_ENCP_SEL_SHIFT);
  797. break;
  798. case 12:
  799. /* enable vclk_div12 gate */
  800. hhi_update_bits(HHI_VID_CLK_CNTL,
  801. VCLK_DIV12_EN, VCLK_DIV12_EN);
  802. if (hdmi_use_enci)
  803. /* select vclk_div12 for enci */
  804. hhi_update_bits(HHI_VID_CLK_DIV,
  805. CTS_ENCI_SEL_MASK,
  806. 4 << CTS_ENCI_SEL_SHIFT);
  807. else
  808. /* select vclk_div12 for encp */
  809. hhi_update_bits(HHI_VID_CLK_DIV,
  810. CTS_ENCP_SEL_MASK,
  811. 4 << CTS_ENCP_SEL_SHIFT);
  812. break;
  813. }
  814. if (hdmi_use_enci)
  815. /* Enable ENCI clock gate */
  816. hhi_update_bits(HHI_VID_CLK_CNTL2,
  817. CTS_ENCI_EN, CTS_ENCI_EN);
  818. else
  819. /* Enable ENCP clock gate */
  820. hhi_update_bits(HHI_VID_CLK_CNTL2,
  821. CTS_ENCP_EN, CTS_ENCP_EN);
  822. hhi_update_bits(HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
  823. }
  824. static void meson_vclk_setup(struct meson_vpu_priv *priv, unsigned int target,
  825. unsigned int vclk_freq, unsigned int venc_freq,
  826. unsigned int dac_freq, bool hdmi_use_enci)
  827. {
  828. bool vic_alternate_clock = false;
  829. unsigned int freq;
  830. unsigned int hdmi_tx_div;
  831. unsigned int venc_div;
  832. if (target == MESON_VCLK_TARGET_CVBS) {
  833. meson_venci_cvbs_clock_config(priv);
  834. return;
  835. } else if (target == MESON_VCLK_TARGET_DMT) {
  836. /* The DMT clock path is fixed after the PLL:
  837. * - automatic PLL freq + OD management
  838. * - vid_pll_div = VID_PLL_DIV_5
  839. * - vclk_div = 2
  840. * - hdmi_tx_div = 1
  841. * - venc_div = 1
  842. * - encp encoder
  843. */
  844. meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0,
  845. VID_PLL_DIV_5, 2, 1, 1, false, false);
  846. return;
  847. }
  848. hdmi_tx_div = vclk_freq / dac_freq;
  849. if (hdmi_tx_div == 0) {
  850. printf("Fatal Error, invalid HDMI-TX freq %d\n",
  851. dac_freq);
  852. return;
  853. }
  854. venc_div = vclk_freq / venc_freq;
  855. if (venc_div == 0) {
  856. printf("Fatal Error, invalid HDMI venc freq %d\n",
  857. venc_freq);
  858. return;
  859. }
  860. for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
  861. if (vclk_freq == params[freq].pixel_freq ||
  862. vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) {
  863. if (vclk_freq != params[freq].pixel_freq)
  864. vic_alternate_clock = true;
  865. else
  866. vic_alternate_clock = false;
  867. if (freq == MESON_VCLK_HDMI_ENCI_54000 &&
  868. !hdmi_use_enci)
  869. continue;
  870. if (freq == MESON_VCLK_HDMI_DDR_54000 &&
  871. hdmi_use_enci)
  872. continue;
  873. if (freq == MESON_VCLK_HDMI_DDR_148500 &&
  874. dac_freq == vclk_freq)
  875. continue;
  876. if (freq == MESON_VCLK_HDMI_148500 &&
  877. dac_freq != vclk_freq)
  878. continue;
  879. break;
  880. }
  881. }
  882. if (!params[freq].pixel_freq) {
  883. pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq);
  884. return;
  885. }
  886. meson_vclk_set(priv, params[freq].pll_base_freq,
  887. params[freq].pll_od1, params[freq].pll_od2,
  888. params[freq].pll_od3, params[freq].vid_pll_div,
  889. params[freq].vclk_div, hdmi_tx_div, venc_div,
  890. hdmi_use_enci, vic_alternate_clock);
  891. }
  892. void meson_vpu_setup_vclk(struct udevice *dev,
  893. const struct display_timing *mode, bool is_cvbs)
  894. {
  895. struct meson_vpu_priv *priv = dev_get_priv(dev);
  896. unsigned int vclk_freq;
  897. if (is_cvbs)
  898. return meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS,
  899. 0, 0, 0, false);
  900. vclk_freq = mode->pixelclock.typ / 1000;
  901. return meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT,
  902. vclk_freq, vclk_freq, vclk_freq, false);
  903. }