meson_plane.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic Meson Video Processing Unit driver
  4. *
  5. * Copyright (c) 2018 BayLibre, SAS.
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <asm/io.h>
  11. #include <linux/bitfield.h>
  12. #include "meson_vpu.h"
  13. /* OSDx_BLKx_CFG */
  14. #define OSD_CANVAS_SEL 16
  15. #define OSD_ENDIANNESS_LE BIT(15)
  16. #define OSD_ENDIANNESS_BE (0)
  17. #define OSD_BLK_MODE_422 (0x03 << 8)
  18. #define OSD_BLK_MODE_16 (0x04 << 8)
  19. #define OSD_BLK_MODE_32 (0x05 << 8)
  20. #define OSD_BLK_MODE_24 (0x07 << 8)
  21. #define OSD_OUTPUT_COLOR_RGB BIT(7)
  22. #define OSD_OUTPUT_COLOR_YUV (0)
  23. #define OSD_COLOR_MATRIX_32_RGBA (0x00 << 2)
  24. #define OSD_COLOR_MATRIX_32_ARGB (0x01 << 2)
  25. #define OSD_COLOR_MATRIX_32_ABGR (0x02 << 2)
  26. #define OSD_COLOR_MATRIX_32_BGRA (0x03 << 2)
  27. #define OSD_COLOR_MATRIX_24_RGB (0x00 << 2)
  28. #define OSD_COLOR_MATRIX_16_RGB655 (0x00 << 2)
  29. #define OSD_COLOR_MATRIX_16_RGB565 (0x04 << 2)
  30. #define OSD_INTERLACE_ENABLED BIT(1)
  31. #define OSD_INTERLACE_ODD BIT(0)
  32. #define OSD_INTERLACE_EVEN (0)
  33. /* OSDx_CTRL_STAT */
  34. #define OSD_ENABLE BIT(21)
  35. #define OSD_BLK0_ENABLE BIT(0)
  36. #define OSD_GLOBAL_ALPHA_SHIFT 12
  37. /* OSDx_CTRL_STAT2 */
  38. #define OSD_REPLACE_EN BIT(14)
  39. #define OSD_REPLACE_SHIFT 6
  40. /*
  41. * When the output is interlaced, the OSD must switch between
  42. * each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
  43. * at each vsync.
  44. * But the vertical scaler can provide such funtionnality if
  45. * is configured for 2:1 scaling with interlace options enabled.
  46. */
  47. static void meson_vpp_setup_interlace_vscaler_osd1(struct meson_vpu_priv *priv,
  48. struct video_priv *uc_priv)
  49. {
  50. writel(BIT(3) /* Enable scaler */ |
  51. BIT(2), /* Select OSD1 */
  52. priv->io_base + _REG(VPP_OSD_SC_CTRL0));
  53. writel(((uc_priv->xsize - 1) << 16) | (uc_priv->ysize - 1),
  54. priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
  55. /* 2:1 scaling */
  56. writel((0 << 16) | uc_priv->xsize,
  57. priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
  58. writel(((0 >> 1) << 16) | (uc_priv->ysize >> 1),
  59. priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
  60. /* 2:1 scaling values */
  61. writel(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
  62. writel(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
  63. writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
  64. writel((4 << 0) /* osd_vsc_bank_length */ |
  65. (4 << 3) /* osd_vsc_top_ini_rcv_num0 */ |
  66. (1 << 8) /* osd_vsc_top_rpt_p0_num0 */ |
  67. (6 << 11) /* osd_vsc_bot_ini_rcv_num0 */ |
  68. (2 << 16) /* osd_vsc_bot_rpt_p0_num0 */ |
  69. BIT(23) /* osd_prog_interlace */ |
  70. BIT(24), /* Enable vertical scaler */
  71. priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
  72. }
  73. static void
  74. meson_vpp_disable_interlace_vscaler_osd1(struct meson_vpu_priv *priv)
  75. {
  76. writel(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
  77. writel(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
  78. writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
  79. }
  80. void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced)
  81. {
  82. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  83. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  84. struct meson_vpu_priv *priv = dev_get_priv(dev);
  85. u32 osd1_ctrl_stat;
  86. u32 osd1_blk0_cfg[5];
  87. bool osd1_interlace;
  88. unsigned int src_x1, src_x2, src_y1, src_y2;
  89. unsigned int dest_x1, dest_x2, dest_y1, dest_y2;
  90. dest_x1 = src_x1 = 0;
  91. dest_x2 = src_x2 = uc_priv->xsize;
  92. dest_y1 = src_y1 = 0;
  93. dest_y2 = src_y2 = uc_priv->ysize;
  94. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  95. /* VD1 Preblend vertical start/end */
  96. writel(FIELD_PREP(GENMASK(11, 0), 2303),
  97. priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
  98. /* Setup Blender */
  99. writel(uc_priv->xsize |
  100. uc_priv->ysize << 16,
  101. priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
  102. writel(0 << 16 |
  103. (uc_priv->xsize - 1),
  104. priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE));
  105. writel(0 << 16 |
  106. (uc_priv->ysize - 1),
  107. priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE));
  108. writel(uc_priv->xsize << 16 |
  109. uc_priv->ysize,
  110. priv->io_base + _REG(VPP_OUT_H_V_SIZE));
  111. } else {
  112. /* Enable VPP Postblend */
  113. writel(uc_priv->xsize,
  114. priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
  115. writel_bits(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
  116. priv->io_base + _REG(VPP_MISC));
  117. }
  118. /* uc_plat->base is the framebuffer */
  119. /* Enable OSD and BLK0, set max global alpha */
  120. osd1_ctrl_stat = OSD_ENABLE | (0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
  121. OSD_BLK0_ENABLE;
  122. /* Set up BLK0 to point to the right canvas */
  123. osd1_blk0_cfg[0] = ((MESON_CANVAS_ID_OSD1 << OSD_CANVAS_SEL) |
  124. OSD_ENDIANNESS_LE);
  125. /* On GXBB, Use the old non-HDR RGB2YUV converter */
  126. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
  127. osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
  128. /* For XRGB, replace the pixel's alpha by 0xFF */
  129. writel_bits(OSD_REPLACE_EN, OSD_REPLACE_EN,
  130. priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
  131. osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
  132. OSD_COLOR_MATRIX_32_ARGB;
  133. if (is_interlaced) {
  134. osd1_interlace = true;
  135. dest_y1 /= 2;
  136. dest_y2 /= 2;
  137. } else {
  138. osd1_interlace = false;
  139. }
  140. /*
  141. * The format of these registers is (x2 << 16 | x1),
  142. * where x2 is exclusive.
  143. * e.g. +30x1920 would be (1919 << 16) | 30
  144. */
  145. osd1_blk0_cfg[1] = ((src_x2 - 1) << 16) | src_x1;
  146. osd1_blk0_cfg[2] = ((src_y2 - 1) << 16) | src_y1;
  147. osd1_blk0_cfg[3] = ((dest_x2 - 1) << 16) | dest_x1;
  148. osd1_blk0_cfg[4] = ((dest_y2 - 1) << 16) | dest_y1;
  149. writel(osd1_ctrl_stat, priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
  150. writel(osd1_blk0_cfg[0], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
  151. writel(osd1_blk0_cfg[1], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
  152. writel(osd1_blk0_cfg[2], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
  153. writel(osd1_blk0_cfg[3], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
  154. writel(osd1_blk0_cfg[4], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
  155. /* If output is interlace, make use of the Scaler */
  156. if (osd1_interlace)
  157. meson_vpp_setup_interlace_vscaler_osd1(priv, uc_priv);
  158. else
  159. meson_vpp_disable_interlace_vscaler_osd1(priv);
  160. meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
  161. uc_plat->base, uc_priv->xsize * 4,
  162. uc_priv->ysize, MESON_CANVAS_WRAP_NONE,
  163. MESON_CANVAS_BLKMODE_LINEAR);
  164. /* Enable OSD1 */
  165. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  166. writel(((dest_x2 - 1) << 16) | dest_x1,
  167. priv->io_base + _REG(VIU_OSD_BLEND_DIN0_SCOPE_H));
  168. writel(((dest_y2 - 1) << 16) | dest_y1,
  169. priv->io_base + _REG(VIU_OSD_BLEND_DIN0_SCOPE_V));
  170. writel(uc_priv->xsize << 16 | uc_priv->ysize,
  171. priv->io_base + _REG(VIU_OSD_BLEND_BLEND0_SIZE));
  172. writel(uc_priv->xsize << 16 | uc_priv->ysize,
  173. priv->io_base + _REG(VIU_OSD_BLEND_BLEND1_SIZE));
  174. writel_bits(3 << 8, 3 << 8,
  175. priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
  176. } else
  177. writel_bits(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
  178. priv->io_base + _REG(VPP_MISC));
  179. }