meson_dw_hdmi.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 BayLibre, SAS
  4. * Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <display.h>
  8. #include <dm.h>
  9. #include <edid.h>
  10. #include <asm/io.h>
  11. #include <dw_hdmi.h>
  12. #include <dm/device-internal.h>
  13. #include <dm/uclass-internal.h>
  14. #include <power/regulator.h>
  15. #include <clk.h>
  16. #include <linux/delay.h>
  17. #include <reset.h>
  18. #include <media_bus_format.h>
  19. #include "meson_dw_hdmi.h"
  20. #include "meson_vpu.h"
  21. /* TOP Block Communication Channel */
  22. #define HDMITX_TOP_ADDR_REG 0x0
  23. #define HDMITX_TOP_DATA_REG 0x4
  24. #define HDMITX_TOP_CTRL_REG 0x8
  25. #define HDMITX_TOP_G12A_OFFSET 0x8000
  26. /* Controller Communication Channel */
  27. #define HDMITX_DWC_ADDR_REG 0x10
  28. #define HDMITX_DWC_DATA_REG 0x14
  29. #define HDMITX_DWC_CTRL_REG 0x18
  30. /* HHI Registers */
  31. #define HHI_MEM_PD_REG0 0x100 /* 0x40 */
  32. #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
  33. #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
  34. #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
  35. #define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
  36. #define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
  37. #define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
  38. #define HHI_HDMI_PHY_CNTL5 0x3b4 /* 0xed */
  39. struct meson_dw_hdmi {
  40. struct udevice *dev;
  41. struct dw_hdmi hdmi;
  42. void __iomem *hhi_base;
  43. };
  44. enum hdmi_compatible {
  45. HDMI_COMPATIBLE_GXBB = 0,
  46. HDMI_COMPATIBLE_GXL = 1,
  47. HDMI_COMPATIBLE_GXM = 2,
  48. HDMI_COMPATIBLE_G12A = 3,
  49. };
  50. static inline bool meson_hdmi_is_compatible(struct meson_dw_hdmi *priv,
  51. enum hdmi_compatible family)
  52. {
  53. enum hdmi_compatible compat = dev_get_driver_data(priv->dev);
  54. return compat == family;
  55. }
  56. static unsigned int dw_hdmi_top_read(struct dw_hdmi *hdmi, unsigned int addr)
  57. {
  58. struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
  59. hdmi);
  60. unsigned int data;
  61. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
  62. return readl(hdmi->ioaddr +
  63. HDMITX_TOP_G12A_OFFSET + (addr << 2));
  64. /* ADDR must be written twice */
  65. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  66. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  67. /* Read needs a second DATA read */
  68. data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  69. data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  70. return data;
  71. }
  72. static inline void dw_hdmi_top_write(struct dw_hdmi *hdmi,
  73. unsigned int addr, unsigned int data)
  74. {
  75. struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
  76. hdmi);
  77. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
  78. writel(data, hdmi->ioaddr +
  79. HDMITX_TOP_G12A_OFFSET + (addr << 2));
  80. return;
  81. }
  82. /* ADDR must be written twice */
  83. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  84. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  85. /* Write needs single DATA write */
  86. writel(data, hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  87. }
  88. static inline void dw_hdmi_top_write_bits(struct dw_hdmi *hdmi,
  89. unsigned int addr,
  90. unsigned int mask,
  91. unsigned int val)
  92. {
  93. unsigned int data = dw_hdmi_top_read(hdmi, addr);
  94. data &= ~mask;
  95. data |= val;
  96. dw_hdmi_top_write(hdmi, addr, data);
  97. }
  98. static u8 dw_hdmi_dwc_read(struct dw_hdmi *hdmi, int addr)
  99. {
  100. unsigned int data;
  101. /* ADDR must be written twice */
  102. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  103. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  104. /* Read needs a second DATA read */
  105. data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);
  106. data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);
  107. return data;
  108. }
  109. static inline void dw_hdmi_dwc_write(struct dw_hdmi *hdmi, u8 data, int addr)
  110. {
  111. /* ADDR must be written twice */
  112. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  113. writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
  114. /* Write needs single DATA write */
  115. writel(data, hdmi->ioaddr + HDMITX_DWC_DATA_REG);
  116. }
  117. static inline void dw_hdmi_dwc_write_bits(struct dw_hdmi *hdmi,
  118. unsigned int addr,
  119. unsigned int mask,
  120. unsigned int val)
  121. {
  122. u8 data = dw_hdmi_dwc_read(hdmi, addr);
  123. data &= ~mask;
  124. data |= val;
  125. dw_hdmi_dwc_write(hdmi, data, addr);
  126. }
  127. static inline void dw_hdmi_hhi_write(struct meson_dw_hdmi *priv,
  128. unsigned int addr, unsigned int data)
  129. {
  130. hhi_write(addr, data);
  131. }
  132. __attribute__((unused))
  133. static unsigned int dw_hdmi_hhi_read(struct meson_dw_hdmi *priv,
  134. unsigned int addr)
  135. {
  136. return hhi_read(addr);
  137. }
  138. static inline void dw_hdmi_hhi_update_bits(struct meson_dw_hdmi *priv,
  139. unsigned int addr,
  140. unsigned int mask,
  141. unsigned int val)
  142. {
  143. hhi_update_bits(addr, mask, val);
  144. }
  145. static int meson_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  146. {
  147. #if defined DEBUG
  148. struct display_timing timing;
  149. int panel_bits_per_colour;
  150. #endif
  151. struct meson_dw_hdmi *priv = dev_get_priv(dev);
  152. int ret;
  153. ret = dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
  154. #if defined DEBUG
  155. if (!ret)
  156. return ret;
  157. edid_print_info((struct edid1_info *)buf);
  158. edid_get_timing(buf, ret, &timing, &panel_bits_per_colour);
  159. debug("Display timing:\n");
  160. debug(" hactive %04d, hfrontp %04d, hbackp %04d hsync %04d\n"
  161. " vactive %04d, vfrontp %04d, vbackp %04d vsync %04d\n",
  162. timing.hactive.typ, timing.hfront_porch.typ,
  163. timing.hback_porch.typ, timing.hsync_len.typ,
  164. timing.vactive.typ, timing.vfront_porch.typ,
  165. timing.vback_porch.typ, timing.vsync_len.typ);
  166. debug(" flags: ");
  167. if (timing.flags & DISPLAY_FLAGS_INTERLACED)
  168. debug("interlaced ");
  169. if (timing.flags & DISPLAY_FLAGS_DOUBLESCAN)
  170. debug("doublescan ");
  171. if (timing.flags & DISPLAY_FLAGS_DOUBLECLK)
  172. debug("doubleclk ");
  173. if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
  174. debug("hsync_low ");
  175. if (timing.flags & DISPLAY_FLAGS_HSYNC_HIGH)
  176. debug("hsync_high ");
  177. if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
  178. debug("vsync_low ");
  179. if (timing.flags & DISPLAY_FLAGS_VSYNC_HIGH)
  180. debug("vsync_high ");
  181. debug("\n");
  182. #endif
  183. return ret;
  184. }
  185. static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *priv)
  186. {
  187. /* Enable and software reset */
  188. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xf);
  189. mdelay(2);
  190. /* Enable and unreset */
  191. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xe);
  192. mdelay(2);
  193. }
  194. static void meson_dw_hdmi_phy_setup_mode(struct meson_dw_hdmi *priv,
  195. uint pixel_clock)
  196. {
  197. pixel_clock = pixel_clock / 1000;
  198. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXL) ||
  199. meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXM)) {
  200. if (pixel_clock >= 371250) {
  201. /* 5.94Gbps, 3.7125Gbps */
  202. hhi_write(HHI_HDMI_PHY_CNTL0, 0x333d3282);
  203. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2136315b);
  204. } else if (pixel_clock >= 297000) {
  205. /* 2.97Gbps */
  206. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33303382);
  207. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2036315b);
  208. } else if (pixel_clock >= 148500) {
  209. /* 1.485Gbps */
  210. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33303362);
  211. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2016315b);
  212. } else {
  213. /* 742.5Mbps, and below */
  214. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33604142);
  215. hhi_write(HHI_HDMI_PHY_CNTL3, 0x0016315b);
  216. }
  217. } else if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXBB)) {
  218. if (pixel_clock >= 371250) {
  219. /* 5.94Gbps, 3.7125Gbps */
  220. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33353245);
  221. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2100115b);
  222. } else if (pixel_clock >= 297000) {
  223. /* 2.97Gbps */
  224. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33634283);
  225. hhi_write(HHI_HDMI_PHY_CNTL3, 0xb000115b);
  226. } else {
  227. /* 1.485Gbps, and below */
  228. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33632122);
  229. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2000115b);
  230. }
  231. } else if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
  232. if (pixel_clock >= 371250) {
  233. /* 5.94Gbps, 3.7125Gbps */
  234. hhi_write(HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
  235. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
  236. hhi_write(HHI_HDMI_PHY_CNTL5, 0x0000080b);
  237. } else if (pixel_clock >= 297000) {
  238. /* 2.97Gbps */
  239. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33eb6262);
  240. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
  241. hhi_write(HHI_HDMI_PHY_CNTL5, 0x00000003);
  242. } else {
  243. /* 1.485Gbps, and below */
  244. hhi_write(HHI_HDMI_PHY_CNTL0, 0x33eb4242);
  245. hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
  246. hhi_write(HHI_HDMI_PHY_CNTL5, 0x00000003);
  247. }
  248. }
  249. }
  250. static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock)
  251. {
  252. struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
  253. hdmi);
  254. /* Enable clocks */
  255. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
  256. /* Bring HDMITX MEM output of power down */
  257. dw_hdmi_hhi_update_bits(priv, HHI_MEM_PD_REG0, 0xff << 8, 0);
  258. /* Bring out of reset */
  259. dw_hdmi_top_write(hdmi, HDMITX_TOP_SW_RESET, 0);
  260. /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
  261. dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3, 0x3);
  262. dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3 << 4, 0x3 << 4);
  263. /* Enable normal output to PHY */
  264. dw_hdmi_top_write(hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
  265. /* TMDS pattern setup (TOFIX pattern for 4k2k scrambling) */
  266. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);
  267. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);
  268. /* Load TMDS pattern */
  269. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
  270. mdelay(20);
  271. dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
  272. /* Setup PHY parameters */
  273. meson_dw_hdmi_phy_setup_mode(priv, pixel_clock);
  274. /* Setup PHY */
  275. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
  276. 0xffff << 16, 0x0390 << 16);
  277. /* BIT_INVERT */
  278. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXL) ||
  279. meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXM) ||
  280. meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
  281. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, BIT(17), 0);
  282. else
  283. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
  284. BIT(17), BIT(17));
  285. /* Disable clock, fifo, fifo_wr */
  286. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0);
  287. mdelay(100);
  288. /* Reset PHY 3 times in a row */
  289. meson_dw_hdmi_phy_reset(priv);
  290. meson_dw_hdmi_phy_reset(priv);
  291. meson_dw_hdmi_phy_reset(priv);
  292. return 0;
  293. }
  294. static int meson_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
  295. const struct display_timing *edid)
  296. {
  297. struct meson_dw_hdmi *priv = dev_get_priv(dev);
  298. /* will back into meson_dw_hdmi_phy_init */
  299. return dw_hdmi_enable(&priv->hdmi, edid);
  300. }
  301. static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
  302. {
  303. int i;
  304. /* Poll 1 second for HPD signal */
  305. for (i = 0; i < 10; ++i) {
  306. if (dw_hdmi_top_read(hdmi, HDMITX_TOP_STAT0))
  307. return 0;
  308. mdelay(100);
  309. }
  310. return -ETIMEDOUT;
  311. }
  312. static int meson_dw_hdmi_probe(struct udevice *dev)
  313. {
  314. struct meson_dw_hdmi *priv = dev_get_priv(dev);
  315. struct reset_ctl_bulk resets;
  316. struct clk_bulk clocks;
  317. struct udevice *supply;
  318. int ret;
  319. priv->dev = dev;
  320. priv->hdmi.ioaddr = (ulong)dev_remap_addr_index(dev, 0);
  321. if (!priv->hdmi.ioaddr)
  322. return -EINVAL;
  323. priv->hhi_base = dev_remap_addr_index(dev, 1);
  324. if (!priv->hhi_base)
  325. return -EINVAL;
  326. priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
  327. priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
  328. priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
  329. if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
  330. priv->hdmi.reg_io_width = 1;
  331. else {
  332. priv->hdmi.write_reg = dw_hdmi_dwc_write;
  333. priv->hdmi.read_reg = dw_hdmi_dwc_read;
  334. }
  335. priv->hdmi.i2c_clk_high = 0x67;
  336. priv->hdmi.i2c_clk_low = 0x78;
  337. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  338. ret = device_get_supply_regulator(dev, "hdmi-supply", &supply);
  339. if (ret && ret != -ENOENT) {
  340. pr_err("Failed to get HDMI regulator\n");
  341. return ret;
  342. }
  343. if (!ret) {
  344. ret = regulator_set_enable(supply, true);
  345. if (ret)
  346. return ret;
  347. }
  348. #endif
  349. uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
  350. &priv->hdmi.ddc_bus);
  351. ret = reset_get_bulk(dev, &resets);
  352. if (ret)
  353. return ret;
  354. ret = clk_get_bulk(dev, &clocks);
  355. if (ret)
  356. return ret;
  357. ret = clk_enable_bulk(&clocks);
  358. if (ret)
  359. return ret;
  360. /* Enable clocks */
  361. dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
  362. /* Bring HDMITX MEM output of power down */
  363. dw_hdmi_hhi_update_bits(priv, HHI_MEM_PD_REG0, 0xff << 8, 0);
  364. /* Reset HDMITX APB & TX & PHY: cycle needed for EDID */
  365. ret = reset_deassert_bulk(&resets);
  366. if (ret)
  367. return ret;
  368. ret = reset_assert_bulk(&resets);
  369. if (ret)
  370. return ret;
  371. ret = reset_deassert_bulk(&resets);
  372. if (ret)
  373. return ret;
  374. if (!meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
  375. /* Enable APB3 fail on error */
  376. writel_bits(BIT(15), BIT(15),
  377. priv->hdmi.ioaddr + HDMITX_TOP_CTRL_REG);
  378. writel_bits(BIT(15), BIT(15),
  379. priv->hdmi.ioaddr + HDMITX_DWC_CTRL_REG);
  380. }
  381. /* Bring out of reset */
  382. dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_SW_RESET, 0);
  383. mdelay(20);
  384. dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_CLK_CNTL, 0xff);
  385. dw_hdmi_init(&priv->hdmi);
  386. dw_hdmi_phy_init(&priv->hdmi);
  387. /* wait for connector */
  388. ret = meson_dw_hdmi_wait_hpd(&priv->hdmi);
  389. if (ret)
  390. debug("hdmi can not get hpd signal\n");
  391. return ret;
  392. }
  393. static bool meson_dw_hdmi_mode_valid(struct udevice *dev,
  394. const struct display_timing *timing)
  395. {
  396. return meson_venc_hdmi_supported_mode(timing);
  397. }
  398. static const struct dm_display_ops meson_dw_hdmi_ops = {
  399. .read_edid = meson_dw_hdmi_read_edid,
  400. .enable = meson_dw_hdmi_enable,
  401. .mode_valid = meson_dw_hdmi_mode_valid,
  402. };
  403. static const struct udevice_id meson_dw_hdmi_ids[] = {
  404. { .compatible = "amlogic,meson-gxbb-dw-hdmi",
  405. .data = HDMI_COMPATIBLE_GXBB },
  406. { .compatible = "amlogic,meson-gxl-dw-hdmi",
  407. .data = HDMI_COMPATIBLE_GXL },
  408. { .compatible = "amlogic,meson-gxm-dw-hdmi",
  409. .data = HDMI_COMPATIBLE_GXM },
  410. { .compatible = "amlogic,meson-g12a-dw-hdmi",
  411. .data = HDMI_COMPATIBLE_G12A },
  412. { }
  413. };
  414. U_BOOT_DRIVER(meson_dw_hdmi) = {
  415. .name = "meson_dw_hdmi",
  416. .id = UCLASS_DISPLAY,
  417. .of_match = meson_dw_hdmi_ids,
  418. .ops = &meson_dw_hdmi_ops,
  419. .probe = meson_dw_hdmi_probe,
  420. .priv_auto_alloc_size = sizeof(struct meson_dw_hdmi),
  421. };