atmel_lcdfb.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for AT91/AT32 LCD Controller
  4. *
  5. * Copyright (C) 2007 Atmel Corporation
  6. */
  7. #include <common.h>
  8. #include <atmel_lcd.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <part.h>
  12. #include <video.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/gpio.h>
  15. #include <asm/arch/clk.h>
  16. #include <lcd.h>
  17. #include <bmp_layout.h>
  18. #include <atmel_lcdc.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #ifdef CONFIG_DM_VIDEO
  21. enum {
  22. /* Maximum LCD size we support */
  23. LCD_MAX_WIDTH = 1366,
  24. LCD_MAX_HEIGHT = 768,
  25. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  26. };
  27. #endif
  28. struct atmel_fb_priv {
  29. struct display_timing timing;
  30. };
  31. /* configurable parameters */
  32. #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
  33. #define ATMEL_LCDC_DMA_BURST_LEN 8
  34. #ifndef ATMEL_LCDC_GUARD_TIME
  35. #define ATMEL_LCDC_GUARD_TIME 1
  36. #endif
  37. #if defined(CONFIG_AT91SAM9263)
  38. #define ATMEL_LCDC_FIFO_SIZE 2048
  39. #else
  40. #define ATMEL_LCDC_FIFO_SIZE 512
  41. #endif
  42. #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
  43. #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
  44. #ifndef CONFIG_DM_VIDEO
  45. ushort *configuration_get_cmap(void)
  46. {
  47. return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  48. }
  49. #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
  50. void fb_put_word(uchar **fb, uchar **from)
  51. {
  52. *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
  53. *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
  54. *from += 2;
  55. }
  56. #endif
  57. #ifdef CONFIG_LCD_LOGO
  58. #include <bmp_logo.h>
  59. void lcd_logo_set_cmap(void)
  60. {
  61. int i;
  62. uint lut_entry;
  63. ushort colreg;
  64. uint *cmap = (uint *)configuration_get_cmap();
  65. for (i = 0; i < BMP_LOGO_COLORS; ++i) {
  66. colreg = bmp_logo_palette[i];
  67. #ifdef CONFIG_ATMEL_LCD_BGR555
  68. lut_entry = ((colreg & 0x000F) << 11) |
  69. ((colreg & 0x00F0) << 2) |
  70. ((colreg & 0x0F00) >> 7);
  71. #else
  72. lut_entry = ((colreg & 0x000F) << 1) |
  73. ((colreg & 0x00F0) << 3) |
  74. ((colreg & 0x0F00) << 4);
  75. #endif
  76. *(cmap + BMP_LOGO_OFFSET) = lut_entry;
  77. cmap++;
  78. }
  79. }
  80. #endif
  81. void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  82. {
  83. #if defined(CONFIG_ATMEL_LCD_BGR555)
  84. lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  85. (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
  86. #else
  87. lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  88. (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
  89. #endif
  90. }
  91. void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
  92. {
  93. int i;
  94. for (i = 0; i < colors; ++i) {
  95. struct bmp_color_table_entry cte = bmp->color_table[i];
  96. lcd_setcolreg(i, cte.red, cte.green, cte.blue);
  97. }
  98. }
  99. #endif
  100. static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
  101. bool tft, bool cont_pol_low, ulong lcdbase)
  102. {
  103. unsigned long value;
  104. void *reg = (void *)addr;
  105. /* Turn off the LCD controller and the DMA controller */
  106. lcdc_writel(reg, ATMEL_LCDC_PWRCON,
  107. ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
  108. /* Wait for the LCDC core to become idle */
  109. while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
  110. udelay(10);
  111. lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
  112. /* Reset LCDC DMA */
  113. lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
  114. /* ...set frame size and burst length = 8 words (?) */
  115. value = (timing->hactive.typ * timing->vactive.typ *
  116. (1 << bpix)) / 32;
  117. value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
  118. lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
  119. /* Set pixel clock */
  120. value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
  121. if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
  122. value++;
  123. value = (value / 2) - 1;
  124. if (!value) {
  125. lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
  126. } else
  127. lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
  128. value << ATMEL_LCDC_CLKVAL_OFFSET);
  129. /* Initialize control register 2 */
  130. value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
  131. if (tft)
  132. value |= ATMEL_LCDC_DISTYPE_TFT;
  133. if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
  134. value |= ATMEL_LCDC_INVLINE_INVERTED;
  135. if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
  136. value |= ATMEL_LCDC_INVFRAME_INVERTED;
  137. value |= bpix << 5;
  138. lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
  139. /* Vertical timing */
  140. value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
  141. value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
  142. value |= timing->vfront_porch.typ;
  143. /* Magic! (Datasheet says "Bit 31 must be written to 1") */
  144. value |= 1U << 31;
  145. lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
  146. /* Horizontal timing */
  147. value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
  148. value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
  149. value |= (timing->hback_porch.typ - 1);
  150. lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
  151. /* Display size */
  152. value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
  153. value |= timing->vactive.typ - 1;
  154. lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
  155. /* FIFO Threshold: Use formula from data sheet */
  156. value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
  157. lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
  158. /* Toggle LCD_MODE every frame */
  159. lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
  160. /* Disable all interrupts */
  161. lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
  162. /* Set contrast */
  163. value = ATMEL_LCDC_PS_DIV8 |
  164. ATMEL_LCDC_ENA_PWMENABLE;
  165. if (!cont_pol_low)
  166. value |= ATMEL_LCDC_POL_POSITIVE;
  167. lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
  168. lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
  169. /* Set framebuffer DMA base address and pixel offset */
  170. lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
  171. lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
  172. lcdc_writel(reg, ATMEL_LCDC_PWRCON,
  173. (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
  174. }
  175. #ifndef CONFIG_DM_VIDEO
  176. void lcd_ctrl_init(void *lcdbase)
  177. {
  178. struct display_timing timing;
  179. timing.flags = 0;
  180. if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
  181. timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
  182. if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
  183. timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
  184. timing.pixelclock.typ = panel_info.vl_clk;
  185. timing.hactive.typ = panel_info.vl_col;
  186. timing.hfront_porch.typ = panel_info.vl_right_margin;
  187. timing.hback_porch.typ = panel_info.vl_left_margin;
  188. timing.hsync_len.typ = panel_info.vl_hsync_len;
  189. timing.vactive.typ = panel_info.vl_row;
  190. timing.vfront_porch.typ = panel_info.vl_clk;
  191. timing.vback_porch.typ = panel_info.vl_clk;
  192. timing.vsync_len.typ = panel_info.vl_clk;
  193. atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
  194. panel_info.vl_tft, panel_info.vl_cont_pol_low,
  195. (ulong)lcdbase);
  196. }
  197. ulong calc_fbsize(void)
  198. {
  199. return ((panel_info.vl_col * panel_info.vl_row *
  200. NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
  201. }
  202. #endif
  203. #ifdef CONFIG_DM_VIDEO
  204. static int atmel_fb_lcd_probe(struct udevice *dev)
  205. {
  206. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  207. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  208. struct atmel_fb_priv *priv = dev_get_priv(dev);
  209. struct display_timing *timing = &priv->timing;
  210. /*
  211. * For now some values are hard-coded. We could use the device tree
  212. * bindings in simple-framebuffer.txt to specify the format/bpp and
  213. * some Atmel-specific binding for tft and cont_pol_low.
  214. */
  215. atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
  216. uc_plat->base);
  217. uc_priv->xsize = timing->hactive.typ;
  218. uc_priv->ysize = timing->vactive.typ;
  219. uc_priv->bpix = VIDEO_BPP16;
  220. video_set_flush_dcache(dev, true);
  221. debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
  222. uc_plat->size, uc_priv->xsize, uc_priv->ysize);
  223. return 0;
  224. }
  225. static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
  226. {
  227. struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
  228. struct atmel_fb_priv *priv = dev_get_priv(dev);
  229. struct display_timing *timing = &priv->timing;
  230. const void *blob = gd->fdt_blob;
  231. if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
  232. plat->timing_index, timing)) {
  233. debug("%s: Failed to decode display timing\n", __func__);
  234. return -EINVAL;
  235. }
  236. return 0;
  237. }
  238. static int atmel_fb_lcd_bind(struct udevice *dev)
  239. {
  240. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  241. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  242. (1 << VIDEO_BPP16) / 8;
  243. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  244. return 0;
  245. }
  246. static const struct udevice_id atmel_fb_lcd_ids[] = {
  247. { .compatible = "atmel,at91sam9g45-lcdc" },
  248. { }
  249. };
  250. U_BOOT_DRIVER(atmel_fb) = {
  251. .name = "atmel_fb",
  252. .id = UCLASS_VIDEO,
  253. .of_match = atmel_fb_lcd_ids,
  254. .bind = atmel_fb_lcd_bind,
  255. .ofdata_to_platdata = atmel_fb_ofdata_to_platdata,
  256. .probe = atmel_fb_lcd_probe,
  257. .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
  258. .priv_auto_alloc_size = sizeof(struct atmel_fb_priv),
  259. };
  260. #endif