atmel_hlcdfb.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for AT91/AT32 MULTI LAYER LCD Controller
  4. *
  5. * Copyright (C) 2012 Atmel Corporation
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <malloc.h>
  10. #include <part.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/gpio.h>
  13. #include <asm/arch/clk.h>
  14. #include <clk.h>
  15. #include <dm.h>
  16. #include <fdtdec.h>
  17. #include <lcd.h>
  18. #include <video.h>
  19. #include <wait_bit.h>
  20. #include <atmel_hlcdc.h>
  21. #if defined(CONFIG_LCD_LOGO)
  22. #include <bmp_logo.h>
  23. #endif
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #ifndef CONFIG_DM_VIDEO
  26. /* configurable parameters */
  27. #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
  28. #define ATMEL_LCDC_DMA_BURST_LEN 8
  29. #ifndef ATMEL_LCDC_GUARD_TIME
  30. #define ATMEL_LCDC_GUARD_TIME 1
  31. #endif
  32. #define ATMEL_LCDC_FIFO_SIZE 512
  33. /*
  34. * the CLUT register map as following
  35. * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
  36. */
  37. void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  38. {
  39. writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
  40. ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
  41. | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
  42. | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
  43. }
  44. ushort *configuration_get_cmap(void)
  45. {
  46. #if defined(CONFIG_LCD_LOGO)
  47. return bmp_logo_palette;
  48. #else
  49. return NULL;
  50. #endif
  51. }
  52. void lcd_ctrl_init(void *lcdbase)
  53. {
  54. unsigned long value;
  55. struct lcd_dma_desc *desc;
  56. struct atmel_hlcd_regs *regs;
  57. int ret;
  58. if (!has_lcdc())
  59. return; /* No lcdc */
  60. regs = (struct atmel_hlcd_regs *)panel_info.mmio;
  61. /* Disable DISP signal */
  62. writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  63. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  64. false, 1000, false);
  65. if (ret)
  66. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  67. /* Disable synchronization */
  68. writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  69. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  70. false, 1000, false);
  71. if (ret)
  72. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  73. /* Disable pixel clock */
  74. writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  75. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  76. false, 1000, false);
  77. if (ret)
  78. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  79. /* Disable PWM */
  80. writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  81. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  82. false, 1000, false);
  83. if (ret)
  84. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  85. /* Set pixel clock */
  86. value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
  87. if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
  88. value++;
  89. if (value < 1) {
  90. /* Using system clock as pixel clock */
  91. writel(LCDC_LCDCFG0_CLKDIV(0)
  92. | LCDC_LCDCFG0_CGDISHCR
  93. | LCDC_LCDCFG0_CGDISHEO
  94. | LCDC_LCDCFG0_CGDISOVR1
  95. | LCDC_LCDCFG0_CGDISBASE
  96. | panel_info.vl_clk_pol
  97. | LCDC_LCDCFG0_CLKSEL,
  98. &regs->lcdc_lcdcfg0);
  99. } else {
  100. writel(LCDC_LCDCFG0_CLKDIV(value - 2)
  101. | LCDC_LCDCFG0_CGDISHCR
  102. | LCDC_LCDCFG0_CGDISHEO
  103. | LCDC_LCDCFG0_CGDISOVR1
  104. | LCDC_LCDCFG0_CGDISBASE
  105. | panel_info.vl_clk_pol,
  106. &regs->lcdc_lcdcfg0);
  107. }
  108. /* Initialize control register 5 */
  109. value = 0;
  110. value |= panel_info.vl_sync;
  111. #ifndef LCD_OUTPUT_BPP
  112. /* Output is 24bpp */
  113. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  114. #else
  115. switch (LCD_OUTPUT_BPP) {
  116. case 12:
  117. value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
  118. break;
  119. case 16:
  120. value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
  121. break;
  122. case 18:
  123. value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
  124. break;
  125. case 24:
  126. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  127. break;
  128. default:
  129. BUG();
  130. break;
  131. }
  132. #endif
  133. value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
  134. value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
  135. writel(value, &regs->lcdc_lcdcfg5);
  136. /* Vertical & Horizontal Timing */
  137. value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
  138. value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
  139. writel(value, &regs->lcdc_lcdcfg1);
  140. value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
  141. value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
  142. writel(value, &regs->lcdc_lcdcfg2);
  143. value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
  144. value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
  145. writel(value, &regs->lcdc_lcdcfg3);
  146. /* Display size */
  147. value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
  148. value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
  149. writel(value, &regs->lcdc_lcdcfg4);
  150. writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
  151. &regs->lcdc_basecfg0);
  152. switch (NBITS(panel_info.vl_bpix)) {
  153. case 16:
  154. writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
  155. &regs->lcdc_basecfg1);
  156. break;
  157. case 32:
  158. writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
  159. &regs->lcdc_basecfg1);
  160. break;
  161. default:
  162. BUG();
  163. break;
  164. }
  165. writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
  166. writel(0, &regs->lcdc_basecfg3);
  167. writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
  168. /* Disable all interrupts */
  169. writel(~0UL, &regs->lcdc_lcdidr);
  170. writel(~0UL, &regs->lcdc_baseidr);
  171. /* Setup the DMA descriptor, this descriptor will loop to itself */
  172. desc = (struct lcd_dma_desc *)(lcdbase - 16);
  173. desc->address = (u32)lcdbase;
  174. /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
  175. desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
  176. | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
  177. desc->next = (u32)desc;
  178. /* Flush the DMA descriptor if we enabled dcache */
  179. flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
  180. writel(desc->address, &regs->lcdc_baseaddr);
  181. writel(desc->control, &regs->lcdc_basectrl);
  182. writel(desc->next, &regs->lcdc_basenext);
  183. writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
  184. &regs->lcdc_basecher);
  185. /* Enable LCD */
  186. value = readl(&regs->lcdc_lcden);
  187. writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
  188. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  189. true, 1000, false);
  190. if (ret)
  191. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  192. value = readl(&regs->lcdc_lcden);
  193. writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
  194. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  195. true, 1000, false);
  196. if (ret)
  197. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  198. value = readl(&regs->lcdc_lcden);
  199. writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
  200. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  201. true, 1000, false);
  202. if (ret)
  203. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  204. value = readl(&regs->lcdc_lcden);
  205. writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
  206. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  207. true, 1000, false);
  208. if (ret)
  209. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  210. /* Enable flushing if we enabled dcache */
  211. lcd_set_flush_dcache(1);
  212. }
  213. #else
  214. enum {
  215. LCD_MAX_WIDTH = 1024,
  216. LCD_MAX_HEIGHT = 768,
  217. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  218. };
  219. struct atmel_hlcdc_priv {
  220. struct atmel_hlcd_regs *regs;
  221. struct display_timing timing;
  222. unsigned int vl_bpix;
  223. unsigned int output_mode;
  224. unsigned int guard_time;
  225. ulong clk_rate;
  226. };
  227. static int at91_hlcdc_enable_clk(struct udevice *dev)
  228. {
  229. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  230. struct clk clk;
  231. ulong clk_rate;
  232. int ret;
  233. ret = clk_get_by_index(dev, 0, &clk);
  234. if (ret)
  235. return -EINVAL;
  236. ret = clk_enable(&clk);
  237. if (ret)
  238. return ret;
  239. clk_rate = clk_get_rate(&clk);
  240. if (!clk_rate) {
  241. clk_disable(&clk);
  242. return -ENODEV;
  243. }
  244. priv->clk_rate = clk_rate;
  245. clk_free(&clk);
  246. return 0;
  247. }
  248. static void atmel_hlcdc_init(struct udevice *dev)
  249. {
  250. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  251. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  252. struct atmel_hlcd_regs *regs = priv->regs;
  253. struct display_timing *timing = &priv->timing;
  254. struct lcd_dma_desc *desc;
  255. unsigned long value, vl_clk_pol;
  256. int ret;
  257. /* Disable DISP signal */
  258. writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  259. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  260. false, 1000, false);
  261. if (ret)
  262. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  263. /* Disable synchronization */
  264. writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  265. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  266. false, 1000, false);
  267. if (ret)
  268. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  269. /* Disable pixel clock */
  270. writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  271. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  272. false, 1000, false);
  273. if (ret)
  274. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  275. /* Disable PWM */
  276. writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  277. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  278. false, 1000, false);
  279. if (ret)
  280. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  281. /* Set pixel clock */
  282. value = priv->clk_rate / timing->pixelclock.typ;
  283. if (priv->clk_rate % timing->pixelclock.typ)
  284. value++;
  285. vl_clk_pol = 0;
  286. if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
  287. vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
  288. if (value < 1) {
  289. /* Using system clock as pixel clock */
  290. writel(LCDC_LCDCFG0_CLKDIV(0)
  291. | LCDC_LCDCFG0_CGDISHCR
  292. | LCDC_LCDCFG0_CGDISHEO
  293. | LCDC_LCDCFG0_CGDISOVR1
  294. | LCDC_LCDCFG0_CGDISBASE
  295. | vl_clk_pol
  296. | LCDC_LCDCFG0_CLKSEL,
  297. &regs->lcdc_lcdcfg0);
  298. } else {
  299. writel(LCDC_LCDCFG0_CLKDIV(value - 2)
  300. | LCDC_LCDCFG0_CGDISHCR
  301. | LCDC_LCDCFG0_CGDISHEO
  302. | LCDC_LCDCFG0_CGDISOVR1
  303. | LCDC_LCDCFG0_CGDISBASE
  304. | vl_clk_pol,
  305. &regs->lcdc_lcdcfg0);
  306. }
  307. /* Initialize control register 5 */
  308. value = 0;
  309. if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
  310. value |= LCDC_LCDCFG5_HSPOL;
  311. if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
  312. value |= LCDC_LCDCFG5_VSPOL;
  313. switch (priv->output_mode) {
  314. case 12:
  315. value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
  316. break;
  317. case 16:
  318. value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
  319. break;
  320. case 18:
  321. value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
  322. break;
  323. case 24:
  324. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  325. break;
  326. default:
  327. BUG();
  328. break;
  329. }
  330. value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
  331. value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
  332. writel(value, &regs->lcdc_lcdcfg5);
  333. /* Vertical & Horizontal Timing */
  334. value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
  335. value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
  336. writel(value, &regs->lcdc_lcdcfg1);
  337. value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
  338. value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
  339. writel(value, &regs->lcdc_lcdcfg2);
  340. value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
  341. value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
  342. writel(value, &regs->lcdc_lcdcfg3);
  343. /* Display size */
  344. value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
  345. value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
  346. writel(value, &regs->lcdc_lcdcfg4);
  347. writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
  348. &regs->lcdc_basecfg0);
  349. switch (VNBITS(priv->vl_bpix)) {
  350. case 16:
  351. writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
  352. &regs->lcdc_basecfg1);
  353. break;
  354. case 32:
  355. writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
  356. &regs->lcdc_basecfg1);
  357. break;
  358. default:
  359. BUG();
  360. break;
  361. }
  362. writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
  363. writel(0, &regs->lcdc_basecfg3);
  364. writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
  365. /* Disable all interrupts */
  366. writel(~0UL, &regs->lcdc_lcdidr);
  367. writel(~0UL, &regs->lcdc_baseidr);
  368. /* Setup the DMA descriptor, this descriptor will loop to itself */
  369. desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
  370. if (!desc)
  371. return;
  372. desc->address = (u32)uc_plat->base;
  373. /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
  374. desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
  375. | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
  376. desc->next = (u32)desc;
  377. /* Flush the DMA descriptor if we enabled dcache */
  378. flush_dcache_range((u32)desc,
  379. ALIGN(((u32)desc + sizeof(*desc)),
  380. CONFIG_SYS_CACHELINE_SIZE));
  381. writel(desc->address, &regs->lcdc_baseaddr);
  382. writel(desc->control, &regs->lcdc_basectrl);
  383. writel(desc->next, &regs->lcdc_basenext);
  384. writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
  385. &regs->lcdc_basecher);
  386. /* Enable LCD */
  387. value = readl(&regs->lcdc_lcden);
  388. writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
  389. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  390. true, 1000, false);
  391. if (ret)
  392. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  393. value = readl(&regs->lcdc_lcden);
  394. writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
  395. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  396. true, 1000, false);
  397. if (ret)
  398. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  399. value = readl(&regs->lcdc_lcden);
  400. writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
  401. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  402. true, 1000, false);
  403. if (ret)
  404. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  405. value = readl(&regs->lcdc_lcden);
  406. writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
  407. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  408. true, 1000, false);
  409. if (ret)
  410. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  411. }
  412. static int atmel_hlcdc_probe(struct udevice *dev)
  413. {
  414. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  415. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  416. int ret;
  417. ret = at91_hlcdc_enable_clk(dev);
  418. if (ret)
  419. return ret;
  420. atmel_hlcdc_init(dev);
  421. uc_priv->xsize = priv->timing.hactive.typ;
  422. uc_priv->ysize = priv->timing.vactive.typ;
  423. uc_priv->bpix = priv->vl_bpix;
  424. /* Enable flushing if we enabled dcache */
  425. video_set_flush_dcache(dev, true);
  426. return 0;
  427. }
  428. static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
  429. {
  430. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  431. const void *blob = gd->fdt_blob;
  432. int node = dev_of_offset(dev);
  433. priv->regs = (struct atmel_hlcd_regs *)devfdt_get_addr(dev);
  434. if (!priv->regs) {
  435. debug("%s: No display controller address\n", __func__);
  436. return -EINVAL;
  437. }
  438. if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
  439. 0, &priv->timing)) {
  440. debug("%s: Failed to decode display timing\n", __func__);
  441. return -EINVAL;
  442. }
  443. if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
  444. priv->timing.hactive.typ = LCD_MAX_WIDTH;
  445. if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
  446. priv->timing.vactive.typ = LCD_MAX_HEIGHT;
  447. priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
  448. if (!priv->vl_bpix) {
  449. debug("%s: Failed to get bits per pixel\n", __func__);
  450. return -EINVAL;
  451. }
  452. priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
  453. priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
  454. return 0;
  455. }
  456. static int atmel_hlcdc_bind(struct udevice *dev)
  457. {
  458. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  459. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  460. (1 << LCD_MAX_LOG2_BPP) / 8;
  461. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  462. return 0;
  463. }
  464. static const struct udevice_id atmel_hlcdc_ids[] = {
  465. { .compatible = "atmel,sama5d2-hlcdc" },
  466. { .compatible = "atmel,at91sam9x5-hlcdc" },
  467. { }
  468. };
  469. U_BOOT_DRIVER(atmel_hlcdfb) = {
  470. .name = "atmel_hlcdfb",
  471. .id = UCLASS_VIDEO,
  472. .of_match = atmel_hlcdc_ids,
  473. .bind = atmel_hlcdc_bind,
  474. .probe = atmel_hlcdc_probe,
  475. .ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata,
  476. .priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv),
  477. };
  478. #endif