dwc2_udc_otg.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/usb/gadget/dwc2_udc_otg.c
  4. * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
  5. *
  6. * Copyright (C) 2008 for Samsung Electronics
  7. *
  8. * BSP Support for Samsung's UDC driver
  9. * available at:
  10. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  11. *
  12. * State machine bugfixes:
  13. * Marek Szyprowski <m.szyprowski@samsung.com>
  14. *
  15. * Ported to u-boot:
  16. * Marek Szyprowski <m.szyprowski@samsung.com>
  17. * Lukasz Majewski <l.majewski@samsumg.com>
  18. */
  19. #undef DEBUG
  20. #include <common.h>
  21. #include <clk.h>
  22. #include <dm.h>
  23. #include <generic-phy.h>
  24. #include <malloc.h>
  25. #include <reset.h>
  26. #include <dm/device_compat.h>
  27. #include <dm/devres.h>
  28. #include <linux/errno.h>
  29. #include <linux/list.h>
  30. #include <linux/usb/ch9.h>
  31. #include <linux/usb/otg.h>
  32. #include <linux/usb/gadget.h>
  33. #include <phys2bus.h>
  34. #include <asm/byteorder.h>
  35. #include <asm/unaligned.h>
  36. #include <asm/io.h>
  37. #include <asm/mach-types.h>
  38. #include <power/regulator.h>
  39. #include "dwc2_udc_otg_regs.h"
  40. #include "dwc2_udc_otg_priv.h"
  41. /***********************************************************/
  42. #define OTG_DMA_MODE 1
  43. #define DEBUG_SETUP 0
  44. #define DEBUG_EP0 0
  45. #define DEBUG_ISR 0
  46. #define DEBUG_OUT_EP 0
  47. #define DEBUG_IN_EP 0
  48. #include <usb/dwc2_udc.h>
  49. #define EP0_CON 0
  50. #define EP_MASK 0xF
  51. static char *state_names[] = {
  52. "WAIT_FOR_SETUP",
  53. "DATA_STATE_XMIT",
  54. "DATA_STATE_NEED_ZLP",
  55. "WAIT_FOR_OUT_STATUS",
  56. "DATA_STATE_RECV",
  57. "WAIT_FOR_COMPLETE",
  58. "WAIT_FOR_OUT_COMPLETE",
  59. "WAIT_FOR_IN_COMPLETE",
  60. "WAIT_FOR_NULL_COMPLETE",
  61. };
  62. #define DRIVER_VERSION "15 March 2009"
  63. struct dwc2_udc *the_controller;
  64. static const char driver_name[] = "dwc2-udc";
  65. static const char ep0name[] = "ep0-control";
  66. /* Max packet size*/
  67. static unsigned int ep0_fifo_size = 64;
  68. static unsigned int ep_fifo_size = 512;
  69. static unsigned int ep_fifo_size2 = 1024;
  70. static int reset_available = 1;
  71. static struct usb_ctrlrequest *usb_ctrl;
  72. static dma_addr_t usb_ctrl_dma_addr;
  73. /*
  74. Local declarations.
  75. */
  76. static int dwc2_ep_enable(struct usb_ep *ep,
  77. const struct usb_endpoint_descriptor *);
  78. static int dwc2_ep_disable(struct usb_ep *ep);
  79. static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
  80. gfp_t gfp_flags);
  81. static void dwc2_free_request(struct usb_ep *ep, struct usb_request *);
  82. static int dwc2_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
  83. static int dwc2_dequeue(struct usb_ep *ep, struct usb_request *);
  84. static int dwc2_fifo_status(struct usb_ep *ep);
  85. static void dwc2_fifo_flush(struct usb_ep *ep);
  86. static void dwc2_ep0_read(struct dwc2_udc *dev);
  87. static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep);
  88. static void dwc2_handle_ep0(struct dwc2_udc *dev);
  89. static int dwc2_ep0_write(struct dwc2_udc *dev);
  90. static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req);
  91. static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status);
  92. static void stop_activity(struct dwc2_udc *dev,
  93. struct usb_gadget_driver *driver);
  94. static int udc_enable(struct dwc2_udc *dev);
  95. static void udc_set_address(struct dwc2_udc *dev, unsigned char address);
  96. static void reconfig_usbd(struct dwc2_udc *dev);
  97. static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed);
  98. static void nuke(struct dwc2_ep *ep, int status);
  99. static int dwc2_udc_set_halt(struct usb_ep *_ep, int value);
  100. static void dwc2_udc_set_nak(struct dwc2_ep *ep);
  101. void set_udc_gadget_private_data(void *p)
  102. {
  103. debug_cond(DEBUG_SETUP != 0,
  104. "%s: the_controller: 0x%p, p: 0x%p\n", __func__,
  105. the_controller, p);
  106. the_controller->gadget.dev.device_data = p;
  107. }
  108. void *get_udc_gadget_private_data(struct usb_gadget *gadget)
  109. {
  110. return gadget->dev.device_data;
  111. }
  112. static struct usb_ep_ops dwc2_ep_ops = {
  113. .enable = dwc2_ep_enable,
  114. .disable = dwc2_ep_disable,
  115. .alloc_request = dwc2_alloc_request,
  116. .free_request = dwc2_free_request,
  117. .queue = dwc2_queue,
  118. .dequeue = dwc2_dequeue,
  119. .set_halt = dwc2_udc_set_halt,
  120. .fifo_status = dwc2_fifo_status,
  121. .fifo_flush = dwc2_fifo_flush,
  122. };
  123. #define create_proc_files() do {} while (0)
  124. #define remove_proc_files() do {} while (0)
  125. /***********************************************************/
  126. struct dwc2_usbotg_reg *reg;
  127. bool dfu_usb_get_reset(void)
  128. {
  129. return !!(readl(&reg->gintsts) & INT_RESET);
  130. }
  131. __weak void otg_phy_init(struct dwc2_udc *dev) {}
  132. __weak void otg_phy_off(struct dwc2_udc *dev) {}
  133. /***********************************************************/
  134. #include "dwc2_udc_otg_xfer_dma.c"
  135. /*
  136. * udc_disable - disable USB device controller
  137. */
  138. static void udc_disable(struct dwc2_udc *dev)
  139. {
  140. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  141. udc_set_address(dev, 0);
  142. dev->ep0state = WAIT_FOR_SETUP;
  143. dev->gadget.speed = USB_SPEED_UNKNOWN;
  144. dev->usb_address = 0;
  145. otg_phy_off(dev);
  146. }
  147. /*
  148. * udc_reinit - initialize software state
  149. */
  150. static void udc_reinit(struct dwc2_udc *dev)
  151. {
  152. unsigned int i;
  153. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  154. /* device/ep0 records init */
  155. INIT_LIST_HEAD(&dev->gadget.ep_list);
  156. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  157. dev->ep0state = WAIT_FOR_SETUP;
  158. /* basic endpoint records init */
  159. for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
  160. struct dwc2_ep *ep = &dev->ep[i];
  161. if (i != 0)
  162. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  163. ep->desc = 0;
  164. ep->stopped = 0;
  165. INIT_LIST_HEAD(&ep->queue);
  166. ep->pio_irqs = 0;
  167. }
  168. /* the rest was statically initialized, and is read-only */
  169. }
  170. #define BYTES2MAXP(x) (x / 8)
  171. #define MAXP2BYTES(x) (x * 8)
  172. /* until it's enabled, this UDC should be completely invisible
  173. * to any USB host.
  174. */
  175. static int udc_enable(struct dwc2_udc *dev)
  176. {
  177. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  178. otg_phy_init(dev);
  179. reconfig_usbd(dev);
  180. debug_cond(DEBUG_SETUP != 0,
  181. "DWC2 USB 2.0 OTG Controller Core Initialized : 0x%x\n",
  182. readl(&reg->gintmsk));
  183. dev->gadget.speed = USB_SPEED_UNKNOWN;
  184. return 0;
  185. }
  186. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  187. /*
  188. Register entry point for the peripheral controller driver.
  189. */
  190. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  191. {
  192. struct dwc2_udc *dev = the_controller;
  193. int retval = 0;
  194. unsigned long flags = 0;
  195. debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
  196. if (!driver
  197. || (driver->speed != USB_SPEED_FULL
  198. && driver->speed != USB_SPEED_HIGH)
  199. || !driver->bind || !driver->disconnect || !driver->setup)
  200. return -EINVAL;
  201. if (!dev)
  202. return -ENODEV;
  203. if (dev->driver)
  204. return -EBUSY;
  205. spin_lock_irqsave(&dev->lock, flags);
  206. /* first hook up the driver ... */
  207. dev->driver = driver;
  208. spin_unlock_irqrestore(&dev->lock, flags);
  209. if (retval) { /* TODO */
  210. printf("target device_add failed, error %d\n", retval);
  211. return retval;
  212. }
  213. retval = driver->bind(&dev->gadget);
  214. if (retval) {
  215. debug_cond(DEBUG_SETUP != 0,
  216. "%s: bind to driver --> error %d\n",
  217. dev->gadget.name, retval);
  218. dev->driver = 0;
  219. return retval;
  220. }
  221. enable_irq(IRQ_OTG);
  222. debug_cond(DEBUG_SETUP != 0,
  223. "Registered gadget driver %s\n", dev->gadget.name);
  224. udc_enable(dev);
  225. return 0;
  226. }
  227. /*
  228. * Unregister entry point for the peripheral controller driver.
  229. */
  230. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  231. {
  232. struct dwc2_udc *dev = the_controller;
  233. unsigned long flags = 0;
  234. if (!dev)
  235. return -ENODEV;
  236. if (!driver || driver != dev->driver)
  237. return -EINVAL;
  238. spin_lock_irqsave(&dev->lock, flags);
  239. dev->driver = 0;
  240. stop_activity(dev, driver);
  241. spin_unlock_irqrestore(&dev->lock, flags);
  242. driver->unbind(&dev->gadget);
  243. disable_irq(IRQ_OTG);
  244. udc_disable(dev);
  245. return 0;
  246. }
  247. #else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  248. static int dwc2_gadget_start(struct usb_gadget *g,
  249. struct usb_gadget_driver *driver)
  250. {
  251. struct dwc2_udc *dev = the_controller;
  252. debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
  253. if (!driver ||
  254. (driver->speed != USB_SPEED_FULL &&
  255. driver->speed != USB_SPEED_HIGH) ||
  256. !driver->bind || !driver->disconnect || !driver->setup)
  257. return -EINVAL;
  258. if (!dev)
  259. return -ENODEV;
  260. if (dev->driver)
  261. return -EBUSY;
  262. /* first hook up the driver ... */
  263. dev->driver = driver;
  264. debug_cond(DEBUG_SETUP != 0,
  265. "Registered gadget driver %s\n", dev->gadget.name);
  266. return udc_enable(dev);
  267. }
  268. static int dwc2_gadget_stop(struct usb_gadget *g)
  269. {
  270. struct dwc2_udc *dev = the_controller;
  271. if (!dev)
  272. return -ENODEV;
  273. if (!dev->driver)
  274. return -EINVAL;
  275. dev->driver = 0;
  276. stop_activity(dev, dev->driver);
  277. udc_disable(dev);
  278. return 0;
  279. }
  280. #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
  281. /*
  282. * done - retire a request; caller blocked irqs
  283. */
  284. static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status)
  285. {
  286. unsigned int stopped = ep->stopped;
  287. debug("%s: %s %p, req = %p, stopped = %d\n",
  288. __func__, ep->ep.name, ep, &req->req, stopped);
  289. list_del_init(&req->queue);
  290. if (likely(req->req.status == -EINPROGRESS))
  291. req->req.status = status;
  292. else
  293. status = req->req.status;
  294. if (status && status != -ESHUTDOWN) {
  295. debug("complete %s req %p stat %d len %u/%u\n",
  296. ep->ep.name, &req->req, status,
  297. req->req.actual, req->req.length);
  298. }
  299. /* don't modify queue heads during completion callback */
  300. ep->stopped = 1;
  301. #ifdef DEBUG
  302. printf("calling complete callback\n");
  303. {
  304. int i, len = req->req.length;
  305. printf("pkt[%d] = ", req->req.length);
  306. if (len > 64)
  307. len = 64;
  308. for (i = 0; i < len; i++) {
  309. printf("%02x", ((u8 *)req->req.buf)[i]);
  310. if ((i & 7) == 7)
  311. printf(" ");
  312. }
  313. printf("\n");
  314. }
  315. #endif
  316. spin_unlock(&ep->dev->lock);
  317. req->req.complete(&ep->ep, &req->req);
  318. spin_lock(&ep->dev->lock);
  319. debug("callback completed\n");
  320. ep->stopped = stopped;
  321. }
  322. /*
  323. * nuke - dequeue ALL requests
  324. */
  325. static void nuke(struct dwc2_ep *ep, int status)
  326. {
  327. struct dwc2_request *req;
  328. debug("%s: %s %p\n", __func__, ep->ep.name, ep);
  329. /* called with irqs blocked */
  330. while (!list_empty(&ep->queue)) {
  331. req = list_entry(ep->queue.next, struct dwc2_request, queue);
  332. done(ep, req, status);
  333. }
  334. }
  335. static void stop_activity(struct dwc2_udc *dev,
  336. struct usb_gadget_driver *driver)
  337. {
  338. int i;
  339. /* don't disconnect drivers more than once */
  340. if (dev->gadget.speed == USB_SPEED_UNKNOWN)
  341. driver = 0;
  342. dev->gadget.speed = USB_SPEED_UNKNOWN;
  343. /* prevent new request submissions, kill any outstanding requests */
  344. for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
  345. struct dwc2_ep *ep = &dev->ep[i];
  346. ep->stopped = 1;
  347. nuke(ep, -ESHUTDOWN);
  348. }
  349. /* report disconnect; the driver is already quiesced */
  350. if (driver) {
  351. spin_unlock(&dev->lock);
  352. driver->disconnect(&dev->gadget);
  353. spin_lock(&dev->lock);
  354. }
  355. /* re-init driver-visible data structures */
  356. udc_reinit(dev);
  357. }
  358. static void reconfig_usbd(struct dwc2_udc *dev)
  359. {
  360. /* 2. Soft-reset OTG Core and then unreset again. */
  361. int i;
  362. unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
  363. uint32_t dflt_gusbcfg;
  364. uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
  365. u32 max_hw_ep;
  366. int pdata_hw_ep;
  367. debug("Reseting OTG controller\n");
  368. dflt_gusbcfg =
  369. 0<<15 /* PHY Low Power Clock sel*/
  370. |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
  371. |0x5<<10 /* Turnaround time*/
  372. |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
  373. /* 1:SRP enable] H1= 1,1*/
  374. |0<<7 /* Ulpi DDR sel*/
  375. |0<<6 /* 0: high speed utmi+, 1: full speed serial*/
  376. |0<<4 /* 0: utmi+, 1:ulpi*/
  377. #ifdef CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
  378. |0<<3 /* phy i/f 0:8bit, 1:16bit*/
  379. #else
  380. |1<<3 /* phy i/f 0:8bit, 1:16bit*/
  381. #endif
  382. |0x7<<0; /* HS/FS Timeout**/
  383. if (dev->pdata->usb_gusbcfg)
  384. dflt_gusbcfg = dev->pdata->usb_gusbcfg;
  385. writel(dflt_gusbcfg, &reg->gusbcfg);
  386. /* 3. Put the OTG device core in the disconnected state.*/
  387. uTemp = readl(&reg->dctl);
  388. uTemp |= SOFT_DISCONNECT;
  389. writel(uTemp, &reg->dctl);
  390. udelay(20);
  391. /* 4. Make the OTG device core exit from the disconnected state.*/
  392. uTemp = readl(&reg->dctl);
  393. uTemp = uTemp & ~SOFT_DISCONNECT;
  394. writel(uTemp, &reg->dctl);
  395. /* 5. Configure OTG Core to initial settings of device mode.*/
  396. /* [][1: full speed(30Mhz) 0:high speed]*/
  397. writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->dcfg);
  398. mdelay(1);
  399. /* 6. Unmask the core interrupts*/
  400. writel(GINTMSK_INIT, &reg->gintmsk);
  401. /* 7. Set NAK bit of EP0, EP1, EP2*/
  402. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
  403. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
  404. for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) {
  405. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
  406. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
  407. }
  408. /* 8. Unmask EPO interrupts*/
  409. writel(((1 << EP0_CON) << DAINT_OUT_BIT)
  410. | (1 << EP0_CON), &reg->daintmsk);
  411. /* 9. Unmask device OUT EP common interrupts*/
  412. writel(DOEPMSK_INIT, &reg->doepmsk);
  413. /* 10. Unmask device IN EP common interrupts*/
  414. writel(DIEPMSK_INIT, &reg->diepmsk);
  415. rx_fifo_sz = RX_FIFO_SIZE;
  416. np_tx_fifo_sz = NPTX_FIFO_SIZE;
  417. tx_fifo_sz = PTX_FIFO_SIZE;
  418. if (dev->pdata->rx_fifo_sz)
  419. rx_fifo_sz = dev->pdata->rx_fifo_sz;
  420. if (dev->pdata->np_tx_fifo_sz)
  421. np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz;
  422. if (dev->pdata->tx_fifo_sz)
  423. tx_fifo_sz = dev->pdata->tx_fifo_sz;
  424. /* 11. Set Rx FIFO Size (in 32-bit words) */
  425. writel(rx_fifo_sz, &reg->grxfsiz);
  426. /* 12. Set Non Periodic Tx FIFO Size */
  427. writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
  428. &reg->gnptxfsiz);
  429. /* retrieve the number of IN Endpoints (excluding ep0) */
  430. max_hw_ep = (readl(&reg->ghwcfg4) & GHWCFG4_NUM_IN_EPS_MASK) >>
  431. GHWCFG4_NUM_IN_EPS_SHIFT;
  432. pdata_hw_ep = dev->pdata->tx_fifo_sz_nb;
  433. /* tx_fifo_sz_nb should equal to number of IN Endpoint */
  434. if (pdata_hw_ep && max_hw_ep != pdata_hw_ep)
  435. pr_warn("Got %d hw endpoint but %d tx-fifo-size in array !!\n",
  436. max_hw_ep, pdata_hw_ep);
  437. for (i = 0; i < max_hw_ep; i++) {
  438. if (pdata_hw_ep)
  439. tx_fifo_sz = dev->pdata->tx_fifo_sz_array[i];
  440. writel((rx_fifo_sz + np_tx_fifo_sz + (tx_fifo_sz * i)) |
  441. tx_fifo_sz << 16, &reg->dieptxf[i]);
  442. }
  443. /* Flush the RX FIFO */
  444. writel(RX_FIFO_FLUSH, &reg->grstctl);
  445. while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
  446. debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
  447. /* Flush all the Tx FIFO's */
  448. writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
  449. writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
  450. while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
  451. debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
  452. /* 13. Clear NAK bit of EP0, EP1, EP2*/
  453. /* For Slave mode*/
  454. /* EP0: Control OUT */
  455. writel(DEPCTL_EPDIS | DEPCTL_CNAK,
  456. &reg->out_endp[EP0_CON].doepctl);
  457. /* 14. Initialize OTG Link Core.*/
  458. writel(GAHBCFG_INIT, &reg->gahbcfg);
  459. }
  460. static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed)
  461. {
  462. unsigned int ep_ctrl;
  463. int i;
  464. if (speed == USB_SPEED_HIGH) {
  465. ep0_fifo_size = 64;
  466. ep_fifo_size = 512;
  467. ep_fifo_size2 = 1024;
  468. dev->gadget.speed = USB_SPEED_HIGH;
  469. } else {
  470. ep0_fifo_size = 64;
  471. ep_fifo_size = 64;
  472. ep_fifo_size2 = 64;
  473. dev->gadget.speed = USB_SPEED_FULL;
  474. }
  475. dev->ep[0].ep.maxpacket = ep0_fifo_size;
  476. for (i = 1; i < DWC2_MAX_ENDPOINTS; i++)
  477. dev->ep[i].ep.maxpacket = ep_fifo_size;
  478. /* EP0 - Control IN (64 bytes)*/
  479. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  480. writel(ep_ctrl|(0<<0), &reg->in_endp[EP0_CON].diepctl);
  481. /* EP0 - Control OUT (64 bytes)*/
  482. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  483. writel(ep_ctrl|(0<<0), &reg->out_endp[EP0_CON].doepctl);
  484. }
  485. static int dwc2_ep_enable(struct usb_ep *_ep,
  486. const struct usb_endpoint_descriptor *desc)
  487. {
  488. struct dwc2_ep *ep;
  489. struct dwc2_udc *dev;
  490. unsigned long flags = 0;
  491. debug("%s: %p\n", __func__, _ep);
  492. ep = container_of(_ep, struct dwc2_ep, ep);
  493. if (!_ep || !desc || ep->desc || _ep->name == ep0name
  494. || desc->bDescriptorType != USB_DT_ENDPOINT
  495. || ep->bEndpointAddress != desc->bEndpointAddress
  496. || ep_maxpacket(ep) <
  497. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
  498. debug("%s: bad ep or descriptor\n", __func__);
  499. return -EINVAL;
  500. }
  501. /* xfer types must match, except that interrupt ~= bulk */
  502. if (ep->bmAttributes != desc->bmAttributes
  503. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  504. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  505. debug("%s: %s type mismatch\n", __func__, _ep->name);
  506. return -EINVAL;
  507. }
  508. /* hardware _could_ do smaller, but driver doesn't */
  509. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK &&
  510. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) >
  511. ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
  512. debug("%s: bad %s maxpacket\n", __func__, _ep->name);
  513. return -ERANGE;
  514. }
  515. dev = ep->dev;
  516. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
  517. debug("%s: bogus device state\n", __func__);
  518. return -ESHUTDOWN;
  519. }
  520. ep->stopped = 0;
  521. ep->desc = desc;
  522. ep->pio_irqs = 0;
  523. ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
  524. /* Reset halt state */
  525. dwc2_udc_set_nak(ep);
  526. dwc2_udc_set_halt(_ep, 0);
  527. spin_lock_irqsave(&ep->dev->lock, flags);
  528. dwc2_udc_ep_activate(ep);
  529. spin_unlock_irqrestore(&ep->dev->lock, flags);
  530. debug("%s: enabled %s, stopped = %d, maxpacket = %d\n",
  531. __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
  532. return 0;
  533. }
  534. /*
  535. * Disable EP
  536. */
  537. static int dwc2_ep_disable(struct usb_ep *_ep)
  538. {
  539. struct dwc2_ep *ep;
  540. unsigned long flags = 0;
  541. debug("%s: %p\n", __func__, _ep);
  542. ep = container_of(_ep, struct dwc2_ep, ep);
  543. if (!_ep || !ep->desc) {
  544. debug("%s: %s not enabled\n", __func__,
  545. _ep ? ep->ep.name : NULL);
  546. return -EINVAL;
  547. }
  548. spin_lock_irqsave(&ep->dev->lock, flags);
  549. /* Nuke all pending requests */
  550. nuke(ep, -ESHUTDOWN);
  551. ep->desc = 0;
  552. ep->stopped = 1;
  553. spin_unlock_irqrestore(&ep->dev->lock, flags);
  554. debug("%s: disabled %s\n", __func__, _ep->name);
  555. return 0;
  556. }
  557. static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
  558. gfp_t gfp_flags)
  559. {
  560. struct dwc2_request *req;
  561. debug("%s: %s %p\n", __func__, ep->name, ep);
  562. req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req));
  563. if (!req)
  564. return 0;
  565. memset(req, 0, sizeof *req);
  566. INIT_LIST_HEAD(&req->queue);
  567. return &req->req;
  568. }
  569. static void dwc2_free_request(struct usb_ep *ep, struct usb_request *_req)
  570. {
  571. struct dwc2_request *req;
  572. debug("%s: %p\n", __func__, ep);
  573. req = container_of(_req, struct dwc2_request, req);
  574. WARN_ON(!list_empty(&req->queue));
  575. kfree(req);
  576. }
  577. /* dequeue JUST ONE request */
  578. static int dwc2_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  579. {
  580. struct dwc2_ep *ep;
  581. struct dwc2_request *req;
  582. unsigned long flags = 0;
  583. debug("%s: %p\n", __func__, _ep);
  584. ep = container_of(_ep, struct dwc2_ep, ep);
  585. if (!_ep || ep->ep.name == ep0name)
  586. return -EINVAL;
  587. spin_lock_irqsave(&ep->dev->lock, flags);
  588. /* make sure it's actually queued on this endpoint */
  589. list_for_each_entry(req, &ep->queue, queue) {
  590. if (&req->req == _req)
  591. break;
  592. }
  593. if (&req->req != _req) {
  594. spin_unlock_irqrestore(&ep->dev->lock, flags);
  595. return -EINVAL;
  596. }
  597. done(ep, req, -ECONNRESET);
  598. spin_unlock_irqrestore(&ep->dev->lock, flags);
  599. return 0;
  600. }
  601. /*
  602. * Return bytes in EP FIFO
  603. */
  604. static int dwc2_fifo_status(struct usb_ep *_ep)
  605. {
  606. int count = 0;
  607. struct dwc2_ep *ep;
  608. ep = container_of(_ep, struct dwc2_ep, ep);
  609. if (!_ep) {
  610. debug("%s: bad ep\n", __func__);
  611. return -ENODEV;
  612. }
  613. debug("%s: %d\n", __func__, ep_index(ep));
  614. /* LPD can't report unclaimed bytes from IN fifos */
  615. if (ep_is_in(ep))
  616. return -EOPNOTSUPP;
  617. return count;
  618. }
  619. /*
  620. * Flush EP FIFO
  621. */
  622. static void dwc2_fifo_flush(struct usb_ep *_ep)
  623. {
  624. struct dwc2_ep *ep;
  625. ep = container_of(_ep, struct dwc2_ep, ep);
  626. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  627. debug("%s: bad ep\n", __func__);
  628. return;
  629. }
  630. debug("%s: %d\n", __func__, ep_index(ep));
  631. }
  632. static const struct usb_gadget_ops dwc2_udc_ops = {
  633. /* current versions must always be self-powered */
  634. #if CONFIG_IS_ENABLED(DM_USB_GADGET)
  635. .udc_start = dwc2_gadget_start,
  636. .udc_stop = dwc2_gadget_stop,
  637. #endif
  638. };
  639. static struct dwc2_udc memory = {
  640. .usb_address = 0,
  641. .gadget = {
  642. .ops = &dwc2_udc_ops,
  643. .ep0 = &memory.ep[0].ep,
  644. .name = driver_name,
  645. },
  646. /* control endpoint */
  647. .ep[0] = {
  648. .ep = {
  649. .name = ep0name,
  650. .ops = &dwc2_ep_ops,
  651. .maxpacket = EP0_FIFO_SIZE,
  652. },
  653. .dev = &memory,
  654. .bEndpointAddress = 0,
  655. .bmAttributes = 0,
  656. .ep_type = ep_control,
  657. },
  658. /* first group of endpoints */
  659. .ep[1] = {
  660. .ep = {
  661. .name = "ep1in-bulk",
  662. .ops = &dwc2_ep_ops,
  663. .maxpacket = EP_FIFO_SIZE,
  664. },
  665. .dev = &memory,
  666. .bEndpointAddress = USB_DIR_IN | 1,
  667. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  668. .ep_type = ep_bulk_out,
  669. .fifo_num = 1,
  670. },
  671. .ep[2] = {
  672. .ep = {
  673. .name = "ep2out-bulk",
  674. .ops = &dwc2_ep_ops,
  675. .maxpacket = EP_FIFO_SIZE,
  676. },
  677. .dev = &memory,
  678. .bEndpointAddress = USB_DIR_OUT | 2,
  679. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  680. .ep_type = ep_bulk_in,
  681. .fifo_num = 2,
  682. },
  683. .ep[3] = {
  684. .ep = {
  685. .name = "ep3in-int",
  686. .ops = &dwc2_ep_ops,
  687. .maxpacket = EP_FIFO_SIZE,
  688. },
  689. .dev = &memory,
  690. .bEndpointAddress = USB_DIR_IN | 3,
  691. .bmAttributes = USB_ENDPOINT_XFER_INT,
  692. .ep_type = ep_interrupt,
  693. .fifo_num = 3,
  694. },
  695. };
  696. /*
  697. * probe - binds to the platform device
  698. */
  699. int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata)
  700. {
  701. struct dwc2_udc *dev = &memory;
  702. int retval = 0;
  703. debug("%s: %p\n", __func__, pdata);
  704. dev->pdata = pdata;
  705. reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
  706. dev->gadget.is_dualspeed = 1; /* Hack only*/
  707. dev->gadget.is_otg = 0;
  708. dev->gadget.is_a_peripheral = 0;
  709. dev->gadget.b_hnp_enable = 0;
  710. dev->gadget.a_hnp_support = 0;
  711. dev->gadget.a_alt_hnp_support = 0;
  712. the_controller = dev;
  713. usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE,
  714. ROUND(sizeof(struct usb_ctrlrequest),
  715. CONFIG_SYS_CACHELINE_SIZE));
  716. if (!usb_ctrl) {
  717. pr_err("No memory available for UDC!\n");
  718. return -ENOMEM;
  719. }
  720. usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl;
  721. udc_reinit(dev);
  722. return retval;
  723. }
  724. int dwc2_udc_handle_interrupt(void)
  725. {
  726. u32 intr_status = readl(&reg->gintsts);
  727. u32 gintmsk = readl(&reg->gintmsk);
  728. if (intr_status & gintmsk)
  729. return dwc2_udc_irq(1, (void *)the_controller);
  730. return 0;
  731. }
  732. #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
  733. int usb_gadget_handle_interrupts(int index)
  734. {
  735. return dwc2_udc_handle_interrupt();
  736. }
  737. #else /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
  738. struct dwc2_priv_data {
  739. struct clk_bulk clks;
  740. struct reset_ctl_bulk resets;
  741. struct phy_bulk phys;
  742. struct udevice *usb33d_supply;
  743. };
  744. int dm_usb_gadget_handle_interrupts(struct udevice *dev)
  745. {
  746. return dwc2_udc_handle_interrupt();
  747. }
  748. static int dwc2_phy_setup(struct udevice *dev, struct phy_bulk *phys)
  749. {
  750. int ret;
  751. ret = generic_phy_get_bulk(dev, phys);
  752. if (ret)
  753. return ret;
  754. ret = generic_phy_init_bulk(phys);
  755. if (ret)
  756. return ret;
  757. ret = generic_phy_power_on_bulk(phys);
  758. if (ret)
  759. generic_phy_exit_bulk(phys);
  760. return ret;
  761. }
  762. static void dwc2_phy_shutdown(struct udevice *dev, struct phy_bulk *phys)
  763. {
  764. generic_phy_power_off_bulk(phys);
  765. generic_phy_exit_bulk(phys);
  766. }
  767. static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev)
  768. {
  769. struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
  770. ulong drvdata;
  771. void (*set_params)(struct dwc2_plat_otg_data *data);
  772. int ret;
  773. if (usb_get_dr_mode(dev->node) != USB_DR_MODE_PERIPHERAL &&
  774. usb_get_dr_mode(dev->node) != USB_DR_MODE_OTG) {
  775. dev_dbg(dev, "Invalid mode\n");
  776. return -ENODEV;
  777. }
  778. platdata->regs_otg = dev_read_addr(dev);
  779. platdata->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0);
  780. platdata->np_tx_fifo_sz = dev_read_u32_default(dev,
  781. "g-np-tx-fifo-size", 0);
  782. platdata->tx_fifo_sz_nb =
  783. dev_read_size(dev, "g-tx-fifo-size") / sizeof(u32);
  784. if (platdata->tx_fifo_sz_nb > DWC2_MAX_HW_ENDPOINTS)
  785. platdata->tx_fifo_sz_nb = DWC2_MAX_HW_ENDPOINTS;
  786. if (platdata->tx_fifo_sz_nb) {
  787. ret = dev_read_u32_array(dev, "g-tx-fifo-size",
  788. platdata->tx_fifo_sz_array,
  789. platdata->tx_fifo_sz_nb);
  790. if (ret)
  791. return ret;
  792. }
  793. platdata->force_b_session_valid =
  794. dev_read_bool(dev, "u-boot,force-b-session-valid");
  795. /* force platdata according compatible */
  796. drvdata = dev_get_driver_data(dev);
  797. if (drvdata) {
  798. set_params = (void *)drvdata;
  799. set_params(platdata);
  800. }
  801. return 0;
  802. }
  803. static void dwc2_set_stm32mp1_hsotg_params(struct dwc2_plat_otg_data *p)
  804. {
  805. p->activate_stm_id_vb_detection = true;
  806. p->usb_gusbcfg =
  807. 0 << 15 /* PHY Low Power Clock sel*/
  808. | 0x9 << 10 /* USB Turnaround time (0x9 for HS phy) */
  809. | 0 << 9 /* [0:HNP disable,1:HNP enable]*/
  810. | 0 << 8 /* [0:SRP disable 1:SRP enable]*/
  811. | 0 << 6 /* 0: high speed utmi+, 1: full speed serial*/
  812. | 0x7 << 0; /* FS timeout calibration**/
  813. if (p->force_b_session_valid)
  814. p->usb_gusbcfg |= 1 << 30; /* FDMOD: Force device mode */
  815. }
  816. static int dwc2_udc_otg_reset_init(struct udevice *dev,
  817. struct reset_ctl_bulk *resets)
  818. {
  819. int ret;
  820. ret = reset_get_bulk(dev, resets);
  821. if (ret == -ENOTSUPP)
  822. return 0;
  823. if (ret)
  824. return ret;
  825. ret = reset_assert_bulk(resets);
  826. if (!ret) {
  827. udelay(2);
  828. ret = reset_deassert_bulk(resets);
  829. }
  830. if (ret) {
  831. reset_release_bulk(resets);
  832. return ret;
  833. }
  834. return 0;
  835. }
  836. static int dwc2_udc_otg_clk_init(struct udevice *dev,
  837. struct clk_bulk *clks)
  838. {
  839. int ret;
  840. ret = clk_get_bulk(dev, clks);
  841. if (ret == -ENOSYS)
  842. return 0;
  843. if (ret)
  844. return ret;
  845. ret = clk_enable_bulk(clks);
  846. if (ret) {
  847. clk_release_bulk(clks);
  848. return ret;
  849. }
  850. return 0;
  851. }
  852. static int dwc2_udc_otg_probe(struct udevice *dev)
  853. {
  854. struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
  855. struct dwc2_priv_data *priv = dev_get_priv(dev);
  856. struct dwc2_usbotg_reg *usbotg_reg =
  857. (struct dwc2_usbotg_reg *)platdata->regs_otg;
  858. int ret;
  859. ret = dwc2_udc_otg_clk_init(dev, &priv->clks);
  860. if (ret)
  861. return ret;
  862. ret = dwc2_udc_otg_reset_init(dev, &priv->resets);
  863. if (ret)
  864. return ret;
  865. ret = dwc2_phy_setup(dev, &priv->phys);
  866. if (ret)
  867. return ret;
  868. if (CONFIG_IS_ENABLED(DM_REGULATOR) &&
  869. platdata->activate_stm_id_vb_detection &&
  870. !platdata->force_b_session_valid) {
  871. ret = device_get_supply_regulator(dev, "usb33d-supply",
  872. &priv->usb33d_supply);
  873. if (ret) {
  874. dev_err(dev, "can't get voltage level detector supply\n");
  875. return ret;
  876. }
  877. ret = regulator_set_enable(priv->usb33d_supply, true);
  878. if (ret) {
  879. dev_err(dev, "can't enable voltage level detector supply\n");
  880. return ret;
  881. }
  882. /* Enable vbus sensing */
  883. setbits_le32(&usbotg_reg->ggpio,
  884. GGPIO_STM32_OTG_GCCFG_VBDEN |
  885. GGPIO_STM32_OTG_GCCFG_IDEN);
  886. }
  887. if (platdata->force_b_session_valid)
  888. /* Override B session bits : value and enable */
  889. setbits_le32(&usbotg_reg->gotgctl,
  890. A_VALOEN | A_VALOVAL | B_VALOEN | B_VALOVAL);
  891. ret = dwc2_udc_probe(platdata);
  892. if (ret)
  893. return ret;
  894. the_controller->driver = 0;
  895. ret = usb_add_gadget_udc((struct device *)dev, &the_controller->gadget);
  896. return ret;
  897. }
  898. static int dwc2_udc_otg_remove(struct udevice *dev)
  899. {
  900. struct dwc2_priv_data *priv = dev_get_priv(dev);
  901. usb_del_gadget_udc(&the_controller->gadget);
  902. reset_release_bulk(&priv->resets);
  903. clk_release_bulk(&priv->clks);
  904. dwc2_phy_shutdown(dev, &priv->phys);
  905. return dm_scan_fdt_dev(dev);
  906. }
  907. static const struct udevice_id dwc2_udc_otg_ids[] = {
  908. { .compatible = "snps,dwc2" },
  909. { .compatible = "brcm,bcm2835-usb" },
  910. { .compatible = "st,stm32mp1-hsotg",
  911. .data = (ulong)dwc2_set_stm32mp1_hsotg_params },
  912. {},
  913. };
  914. U_BOOT_DRIVER(dwc2_udc_otg) = {
  915. .name = "dwc2-udc-otg",
  916. .id = UCLASS_USB_GADGET_GENERIC,
  917. .of_match = dwc2_udc_otg_ids,
  918. .ofdata_to_platdata = dwc2_udc_otg_ofdata_to_platdata,
  919. .probe = dwc2_udc_otg_probe,
  920. .remove = dwc2_udc_otg_remove,
  921. .platdata_auto_alloc_size = sizeof(struct dwc2_plat_otg_data),
  922. .priv_auto_alloc_size = sizeof(struct dwc2_priv_data),
  923. };
  924. int dwc2_udc_B_session_valid(struct udevice *dev)
  925. {
  926. struct dwc2_plat_otg_data *platdata = dev_get_platdata(dev);
  927. struct dwc2_usbotg_reg *usbotg_reg =
  928. (struct dwc2_usbotg_reg *)platdata->regs_otg;
  929. return readl(&usbotg_reg->gotgctl) & B_SESSION_VALID;
  930. }
  931. #endif /* CONFIG_IS_ENABLED(DM_USB_GADGET) */