designware_udc.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Based on drivers/usb/gadget/omap1510_udc.c
  4. * TI OMAP1510 USB bus interface driver
  5. *
  6. * (C) Copyright 2009
  7. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  8. */
  9. #include <common.h>
  10. #include <serial.h>
  11. #include <asm/io.h>
  12. #include <env.h>
  13. #include <usbdevice.h>
  14. #include "ep0.h"
  15. #include <usb/designware_udc.h>
  16. #include <usb/udc.h>
  17. #include <asm/arch/hardware.h>
  18. #define UDC_INIT_MDELAY 80 /* Device settle delay */
  19. /* Some kind of debugging output... */
  20. #ifndef DEBUG_DWUSBTTY
  21. #define UDCDBG(str)
  22. #define UDCDBGA(fmt, args...)
  23. #else
  24. #define UDCDBG(str) serial_printf(str "\n")
  25. #define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args)
  26. #endif
  27. static struct urb *ep0_urb;
  28. static struct usb_device_instance *udc_device;
  29. static struct plug_regs *const plug_regs_p =
  30. (struct plug_regs * const)CONFIG_SYS_PLUG_BASE;
  31. static struct udc_regs *const udc_regs_p =
  32. (struct udc_regs * const)CONFIG_SYS_USBD_BASE;
  33. static struct udc_endp_regs *const outep_regs_p =
  34. &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0];
  35. static struct udc_endp_regs *const inep_regs_p =
  36. &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0];
  37. /*
  38. * udc_state_transition - Write the next packet to TxFIFO.
  39. * @initial: Initial state.
  40. * @final: Final state.
  41. *
  42. * Helper function to implement device state changes. The device states and
  43. * the events that transition between them are:
  44. *
  45. * STATE_ATTACHED
  46. * || /\
  47. * \/ ||
  48. * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET
  49. * || /\
  50. * \/ ||
  51. * STATE_POWERED
  52. * || /\
  53. * \/ ||
  54. * DEVICE_RESET DEVICE_POWER_INTERRUPTION
  55. * || /\
  56. * \/ ||
  57. * STATE_DEFAULT
  58. * || /\
  59. * \/ ||
  60. * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET
  61. * || /\
  62. * \/ ||
  63. * STATE_ADDRESSED
  64. * || /\
  65. * \/ ||
  66. * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED
  67. * || /\
  68. * \/ ||
  69. * STATE_CONFIGURED
  70. *
  71. * udc_state_transition transitions up (in the direction from STATE_ATTACHED
  72. * to STATE_CONFIGURED) from the specified initial state to the specified final
  73. * state, passing through each intermediate state on the way. If the initial
  74. * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
  75. * no state transitions will take place.
  76. *
  77. * udc_state_transition also transitions down (in the direction from
  78. * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
  79. * specified final state, passing through each intermediate state on the way.
  80. * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
  81. * state, then no state transitions will take place.
  82. *
  83. * This function must only be called with interrupts disabled.
  84. */
  85. static void udc_state_transition(usb_device_state_t initial,
  86. usb_device_state_t final)
  87. {
  88. if (initial < final) {
  89. switch (initial) {
  90. case STATE_ATTACHED:
  91. usbd_device_event_irq(udc_device,
  92. DEVICE_HUB_CONFIGURED, 0);
  93. if (final == STATE_POWERED)
  94. break;
  95. case STATE_POWERED:
  96. usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
  97. if (final == STATE_DEFAULT)
  98. break;
  99. case STATE_DEFAULT:
  100. usbd_device_event_irq(udc_device,
  101. DEVICE_ADDRESS_ASSIGNED, 0);
  102. if (final == STATE_ADDRESSED)
  103. break;
  104. case STATE_ADDRESSED:
  105. usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
  106. case STATE_CONFIGURED:
  107. break;
  108. default:
  109. break;
  110. }
  111. } else if (initial > final) {
  112. switch (initial) {
  113. case STATE_CONFIGURED:
  114. usbd_device_event_irq(udc_device,
  115. DEVICE_DE_CONFIGURED, 0);
  116. if (final == STATE_ADDRESSED)
  117. break;
  118. case STATE_ADDRESSED:
  119. usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
  120. if (final == STATE_DEFAULT)
  121. break;
  122. case STATE_DEFAULT:
  123. usbd_device_event_irq(udc_device,
  124. DEVICE_POWER_INTERRUPTION, 0);
  125. if (final == STATE_POWERED)
  126. break;
  127. case STATE_POWERED:
  128. usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0);
  129. case STATE_ATTACHED:
  130. break;
  131. default:
  132. break;
  133. }
  134. }
  135. }
  136. /* Stall endpoint */
  137. static void udc_stall_ep(u32 ep_num)
  138. {
  139. writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
  140. &inep_regs_p[ep_num].endp_cntl);
  141. writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
  142. &outep_regs_p[ep_num].endp_cntl);
  143. }
  144. static void *get_fifo(int ep_num, int in)
  145. {
  146. u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE;
  147. switch (ep_num) {
  148. case UDC_EP3:
  149. fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn);
  150. /* break intentionally left out */
  151. case UDC_EP1:
  152. fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn);
  153. /* break intentionally left out */
  154. case UDC_EP0:
  155. default:
  156. if (in) {
  157. fifo_ptr +=
  158. readl(&outep_regs_p[2].endp_maxpacksize) >> 16;
  159. /* break intentionally left out */
  160. } else {
  161. break;
  162. }
  163. case UDC_EP2:
  164. fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16;
  165. /* break intentionally left out */
  166. }
  167. return (void *)fifo_ptr;
  168. }
  169. static int usbgetpckfromfifo(int epNum, u8 *bufp, u32 len)
  170. {
  171. u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0);
  172. u32 i, nw, nb;
  173. u32 *wrdp;
  174. u8 *bytp;
  175. u32 tmp[128];
  176. if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY)
  177. return -1;
  178. nw = len / sizeof(u32);
  179. nb = len % sizeof(u32);
  180. /* use tmp buf if bufp is not word aligned */
  181. if ((int)bufp & 0x3)
  182. wrdp = (u32 *)&tmp[0];
  183. else
  184. wrdp = (u32 *)bufp;
  185. for (i = 0; i < nw; i++) {
  186. writel(readl(fifo_ptr), wrdp);
  187. wrdp++;
  188. }
  189. bytp = (u8 *)wrdp;
  190. for (i = 0; i < nb; i++) {
  191. writeb(readb(fifo_ptr), bytp);
  192. fifo_ptr++;
  193. bytp++;
  194. }
  195. readl(&outep_regs_p[epNum].write_done);
  196. /* copy back tmp buffer to bufp if bufp is not word aligned */
  197. if ((int)bufp & 0x3)
  198. memcpy(bufp, tmp, len);
  199. return 0;
  200. }
  201. static void usbputpcktofifo(int epNum, u8 *bufp, u32 len)
  202. {
  203. u32 i, nw, nb;
  204. u32 *wrdp;
  205. u8 *bytp;
  206. u8 *fifo_ptr = get_fifo(epNum, 1);
  207. nw = len / sizeof(int);
  208. nb = len % sizeof(int);
  209. wrdp = (u32 *)bufp;
  210. for (i = 0; i < nw; i++) {
  211. writel(*wrdp, fifo_ptr);
  212. wrdp++;
  213. }
  214. bytp = (u8 *)wrdp;
  215. for (i = 0; i < nb; i++) {
  216. writeb(*bytp, fifo_ptr);
  217. fifo_ptr++;
  218. bytp++;
  219. }
  220. }
  221. /*
  222. * dw_write_noniso_tx_fifo - Write the next packet to TxFIFO.
  223. * @endpoint: Endpoint pointer.
  224. *
  225. * If the endpoint has an active tx_urb, then the next packet of data from the
  226. * URB is written to the tx FIFO. The total amount of data in the urb is given
  227. * by urb->actual_length. The maximum amount of data that can be sent in any
  228. * one packet is given by endpoint->tx_packetSize. The number of data bytes
  229. * from this URB that have already been transmitted is given by endpoint->sent.
  230. * endpoint->last is updated by this routine with the number of data bytes
  231. * transmitted in this packet.
  232. *
  233. */
  234. static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance
  235. *endpoint)
  236. {
  237. struct urb *urb = endpoint->tx_urb;
  238. int align;
  239. if (urb) {
  240. u32 last;
  241. UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
  242. urb->buffer, urb->buffer_length, urb->actual_length);
  243. last = min_t(u32, urb->actual_length - endpoint->sent,
  244. endpoint->tx_packetSize);
  245. if (last) {
  246. u8 *cp = urb->buffer + endpoint->sent;
  247. /*
  248. * This ensures that USBD packet fifo is accessed
  249. * - through word aligned pointer or
  250. * - through non word aligned pointer but only
  251. * with a max length to make the next packet
  252. * word aligned
  253. */
  254. align = ((ulong)cp % sizeof(int));
  255. if (align)
  256. last = min(last, sizeof(int) - align);
  257. UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
  258. endpoint->sent, endpoint->tx_packetSize, last);
  259. usbputpcktofifo(endpoint->endpoint_address &
  260. USB_ENDPOINT_NUMBER_MASK, cp, last);
  261. }
  262. endpoint->last = last;
  263. }
  264. }
  265. /*
  266. * Handle SETUP USB interrupt.
  267. * This function implements TRM Figure 14-14.
  268. */
  269. static void dw_udc_setup(struct usb_endpoint_instance *endpoint)
  270. {
  271. u8 *datap = (u8 *)&ep0_urb->device_request;
  272. int ep_addr = endpoint->endpoint_address;
  273. UDCDBG("-> Entering device setup");
  274. usbgetpckfromfifo(ep_addr, datap, 8);
  275. /* Try to process setup packet */
  276. if (ep0_recv_setup(ep0_urb)) {
  277. /* Not a setup packet, stall next EP0 transaction */
  278. udc_stall_ep(0);
  279. UDCDBG("can't parse setup packet, still waiting for setup");
  280. return;
  281. }
  282. /* Check direction */
  283. if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK)
  284. == USB_REQ_HOST2DEVICE) {
  285. UDCDBG("control write on EP0");
  286. if (le16_to_cpu(ep0_urb->device_request.wLength)) {
  287. /* Stall this request */
  288. UDCDBG("Stalling unsupported EP0 control write data "
  289. "stage.");
  290. udc_stall_ep(0);
  291. }
  292. } else {
  293. UDCDBG("control read on EP0");
  294. /*
  295. * The ep0_recv_setup function has already placed our response
  296. * packet data in ep0_urb->buffer and the packet length in
  297. * ep0_urb->actual_length.
  298. */
  299. endpoint->tx_urb = ep0_urb;
  300. endpoint->sent = 0;
  301. /*
  302. * Write packet data to the FIFO. dw_write_noniso_tx_fifo
  303. * will update endpoint->last with the number of bytes written
  304. * to the FIFO.
  305. */
  306. dw_write_noniso_tx_fifo(endpoint);
  307. writel(0x0, &inep_regs_p[ep_addr].write_done);
  308. }
  309. udc_unset_nak(endpoint->endpoint_address);
  310. UDCDBG("<- Leaving device setup");
  311. }
  312. /*
  313. * Handle endpoint 0 RX interrupt
  314. */
  315. static void dw_udc_ep0_rx(struct usb_endpoint_instance *endpoint)
  316. {
  317. u8 dummy[64];
  318. UDCDBG("RX on EP0");
  319. /* Check direction */
  320. if ((ep0_urb->device_request.bmRequestType
  321. & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) {
  322. /*
  323. * This rx interrupt must be for a control write data
  324. * stage packet.
  325. *
  326. * We don't support control write data stages.
  327. * We should never end up here.
  328. */
  329. UDCDBG("Stalling unexpected EP0 control write "
  330. "data stage packet");
  331. udc_stall_ep(0);
  332. } else {
  333. /*
  334. * This rx interrupt must be for a control read status
  335. * stage packet.
  336. */
  337. UDCDBG("ACK on EP0 control read status stage packet");
  338. u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff;
  339. usbgetpckfromfifo(0, dummy, len);
  340. }
  341. }
  342. /*
  343. * Handle endpoint 0 TX interrupt
  344. */
  345. static void dw_udc_ep0_tx(struct usb_endpoint_instance *endpoint)
  346. {
  347. struct usb_device_request *request = &ep0_urb->device_request;
  348. int ep_addr;
  349. UDCDBG("TX on EP0");
  350. /* Check direction */
  351. if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) ==
  352. USB_REQ_HOST2DEVICE) {
  353. /*
  354. * This tx interrupt must be for a control write status
  355. * stage packet.
  356. */
  357. UDCDBG("ACK on EP0 control write status stage packet");
  358. } else {
  359. /*
  360. * This tx interrupt must be for a control read data
  361. * stage packet.
  362. */
  363. int wLength = le16_to_cpu(request->wLength);
  364. /*
  365. * Update our count of bytes sent so far in this
  366. * transfer.
  367. */
  368. endpoint->sent += endpoint->last;
  369. /*
  370. * We are finished with this transfer if we have sent
  371. * all of the bytes in our tx urb (urb->actual_length)
  372. * unless we need a zero-length terminating packet. We
  373. * need a zero-length terminating packet if we returned
  374. * fewer bytes than were requested (wLength) by the host,
  375. * and the number of bytes we returned is an exact
  376. * multiple of the packet size endpoint->tx_packetSize.
  377. */
  378. if ((endpoint->sent == ep0_urb->actual_length) &&
  379. ((ep0_urb->actual_length == wLength) ||
  380. (endpoint->last != endpoint->tx_packetSize))) {
  381. /* Done with control read data stage. */
  382. UDCDBG("control read data stage complete");
  383. } else {
  384. /*
  385. * We still have another packet of data to send
  386. * in this control read data stage or else we
  387. * need a zero-length terminating packet.
  388. */
  389. UDCDBG("ACK control read data stage packet");
  390. dw_write_noniso_tx_fifo(endpoint);
  391. ep_addr = endpoint->endpoint_address;
  392. writel(0x0, &inep_regs_p[ep_addr].write_done);
  393. }
  394. }
  395. }
  396. static struct usb_endpoint_instance *dw_find_ep(int ep)
  397. {
  398. int i;
  399. for (i = 0; i < udc_device->bus->max_endpoints; i++) {
  400. if ((udc_device->bus->endpoint_array[i].endpoint_address &
  401. USB_ENDPOINT_NUMBER_MASK) == ep)
  402. return &udc_device->bus->endpoint_array[i];
  403. }
  404. return NULL;
  405. }
  406. /*
  407. * Handle RX transaction on non-ISO endpoint.
  408. * The ep argument is a physical endpoint number for a non-ISO IN endpoint
  409. * in the range 1 to 15.
  410. */
  411. static void dw_udc_epn_rx(int ep)
  412. {
  413. int nbytes = 0;
  414. struct urb *urb;
  415. struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
  416. if (endpoint) {
  417. urb = endpoint->rcv_urb;
  418. if (urb) {
  419. u8 *cp = urb->buffer + urb->actual_length;
  420. nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) &
  421. 0xfff;
  422. usbgetpckfromfifo(ep, cp, nbytes);
  423. usbd_rcv_complete(endpoint, nbytes, 0);
  424. }
  425. }
  426. }
  427. /*
  428. * Handle TX transaction on non-ISO endpoint.
  429. * The ep argument is a physical endpoint number for a non-ISO IN endpoint
  430. * in the range 16 to 30.
  431. */
  432. static void dw_udc_epn_tx(int ep)
  433. {
  434. struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
  435. if (!endpoint)
  436. return;
  437. /*
  438. * We need to transmit a terminating zero-length packet now if
  439. * we have sent all of the data in this URB and the transfer
  440. * size was an exact multiple of the packet size.
  441. */
  442. if (endpoint->tx_urb &&
  443. (endpoint->last == endpoint->tx_packetSize) &&
  444. (endpoint->tx_urb->actual_length - endpoint->sent -
  445. endpoint->last == 0)) {
  446. /* handle zero length packet here */
  447. writel(0x0, &inep_regs_p[ep].write_done);
  448. }
  449. if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
  450. /* retire the data that was just sent */
  451. usbd_tx_complete(endpoint);
  452. /*
  453. * Check to see if we have more data ready to transmit
  454. * now.
  455. */
  456. if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
  457. /* write data to FIFO */
  458. dw_write_noniso_tx_fifo(endpoint);
  459. writel(0x0, &inep_regs_p[ep].write_done);
  460. } else if (endpoint->tx_urb
  461. && (endpoint->tx_urb->actual_length == 0)) {
  462. /* udc_set_nak(ep); */
  463. }
  464. }
  465. }
  466. /*
  467. * Start of public functions.
  468. */
  469. /* Called to start packet transmission. */
  470. int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
  471. {
  472. udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK);
  473. return 0;
  474. }
  475. /* Start to initialize h/w stuff */
  476. int udc_init(void)
  477. {
  478. int i;
  479. u32 plug_st;
  480. udc_device = NULL;
  481. UDCDBG("starting");
  482. readl(&plug_regs_p->plug_pending);
  483. for (i = 0; i < UDC_INIT_MDELAY; i++)
  484. udelay(1000);
  485. plug_st = readl(&plug_regs_p->plug_state);
  486. writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state);
  487. writel(~0x0, &udc_regs_p->endp_int);
  488. writel(~0x0, &udc_regs_p->dev_int_mask);
  489. writel(~0x0, &udc_regs_p->endp_int_mask);
  490. #ifndef CONFIG_USBD_HS
  491. writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
  492. DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
  493. #else
  494. writel(DEV_CONF_HS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
  495. DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
  496. #endif
  497. writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);
  498. /* Clear all interrupts pending */
  499. writel(DEV_INT_MSK, &udc_regs_p->dev_int);
  500. return 0;
  501. }
  502. int is_usbd_high_speed(void)
  503. {
  504. return (readl(&udc_regs_p->dev_stat) & DEV_STAT_ENUM) ? 0 : 1;
  505. }
  506. /*
  507. * udc_setup_ep - setup endpoint
  508. * Associate a physical endpoint with endpoint_instance
  509. */
  510. void udc_setup_ep(struct usb_device_instance *device,
  511. u32 ep, struct usb_endpoint_instance *endpoint)
  512. {
  513. UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address);
  514. int ep_addr;
  515. int ep_num, ep_type;
  516. int packet_size;
  517. int buffer_size;
  518. int attributes;
  519. char *tt;
  520. u32 endp_intmask;
  521. if ((ep != 0) && (udc_device->device_state < STATE_ADDRESSED))
  522. return;
  523. tt = env_get("usbtty");
  524. if (!tt)
  525. tt = "generic";
  526. ep_addr = endpoint->endpoint_address;
  527. ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
  528. if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
  529. /* IN endpoint */
  530. packet_size = endpoint->tx_packetSize;
  531. buffer_size = packet_size * 2;
  532. attributes = endpoint->tx_attributes;
  533. } else {
  534. /* OUT endpoint */
  535. packet_size = endpoint->rcv_packetSize;
  536. buffer_size = packet_size * 2;
  537. attributes = endpoint->rcv_attributes;
  538. }
  539. switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) {
  540. case USB_ENDPOINT_XFER_CONTROL:
  541. ep_type = ENDP_EPTYPE_CNTL;
  542. break;
  543. case USB_ENDPOINT_XFER_BULK:
  544. default:
  545. ep_type = ENDP_EPTYPE_BULK;
  546. break;
  547. case USB_ENDPOINT_XFER_INT:
  548. ep_type = ENDP_EPTYPE_INT;
  549. break;
  550. case USB_ENDPOINT_XFER_ISOC:
  551. ep_type = ENDP_EPTYPE_ISO;
  552. break;
  553. }
  554. struct udc_endp_regs *out_p = &outep_regs_p[ep_num];
  555. struct udc_endp_regs *in_p = &inep_regs_p[ep_num];
  556. if (!ep_addr) {
  557. /* Setup endpoint 0 */
  558. buffer_size = packet_size;
  559. writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK,
  560. &in_p->endp_cntl);
  561. writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK,
  562. &out_p->endp_cntl);
  563. writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl);
  564. writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
  565. writel(packet_size, &in_p->endp_maxpacksize);
  566. writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl);
  567. writel(packet_size | ((buffer_size / sizeof(int)) << 16),
  568. &out_p->endp_maxpacksize);
  569. } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
  570. /* Setup the IN endpoint */
  571. writel(0x0, &in_p->endp_status);
  572. writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl);
  573. writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
  574. writel(packet_size, &in_p->endp_maxpacksize);
  575. if (!strcmp(tt, "cdc_acm")) {
  576. if (ep_type == ENDP_EPTYPE_INT) {
  577. /* Conf no. 1 Interface no. 0 */
  578. writel((packet_size << 19) |
  579. ENDP_EPDIR_IN | (1 << 7) |
  580. (0 << 11) | (ep_type << 5) | ep_num,
  581. &udc_regs_p->udc_endp_reg[ep_num]);
  582. } else {
  583. /* Conf no. 1 Interface no. 1 */
  584. writel((packet_size << 19) |
  585. ENDP_EPDIR_IN | (1 << 7) |
  586. (1 << 11) | (ep_type << 5) | ep_num,
  587. &udc_regs_p->udc_endp_reg[ep_num]);
  588. }
  589. } else {
  590. /* Conf no. 1 Interface no. 0 */
  591. writel((packet_size << 19) |
  592. ENDP_EPDIR_IN | (1 << 7) |
  593. (0 << 11) | (ep_type << 5) | ep_num,
  594. &udc_regs_p->udc_endp_reg[ep_num]);
  595. }
  596. } else {
  597. /* Setup the OUT endpoint */
  598. writel(0x0, &out_p->endp_status);
  599. writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl);
  600. writel(packet_size | ((buffer_size / sizeof(int)) << 16),
  601. &out_p->endp_maxpacksize);
  602. if (!strcmp(tt, "cdc_acm")) {
  603. writel((packet_size << 19) |
  604. ENDP_EPDIR_OUT | (1 << 7) |
  605. (1 << 11) | (ep_type << 5) | ep_num,
  606. &udc_regs_p->udc_endp_reg[ep_num]);
  607. } else {
  608. writel((packet_size << 19) |
  609. ENDP_EPDIR_OUT | (1 << 7) |
  610. (0 << 11) | (ep_type << 5) | ep_num,
  611. &udc_regs_p->udc_endp_reg[ep_num]);
  612. }
  613. }
  614. endp_intmask = readl(&udc_regs_p->endp_int_mask);
  615. endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num);
  616. writel(endp_intmask, &udc_regs_p->endp_int_mask);
  617. }
  618. /* Turn on the USB connection by enabling the pullup resistor */
  619. void udc_connect(void)
  620. {
  621. u32 plug_st, dev_cntl;
  622. dev_cntl = readl(&udc_regs_p->dev_cntl);
  623. dev_cntl |= DEV_CNTL_SOFTDISCONNECT;
  624. writel(dev_cntl, &udc_regs_p->dev_cntl);
  625. udelay(1000);
  626. dev_cntl = readl(&udc_regs_p->dev_cntl);
  627. dev_cntl &= ~DEV_CNTL_SOFTDISCONNECT;
  628. writel(dev_cntl, &udc_regs_p->dev_cntl);
  629. plug_st = readl(&plug_regs_p->plug_state);
  630. plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
  631. writel(plug_st, &plug_regs_p->plug_state);
  632. }
  633. /* Turn off the USB connection by disabling the pullup resistor */
  634. void udc_disconnect(void)
  635. {
  636. u32 plug_st;
  637. writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);
  638. plug_st = readl(&plug_regs_p->plug_state);
  639. plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
  640. writel(plug_st, &plug_regs_p->plug_state);
  641. }
  642. /* Switch on the UDC */
  643. void udc_enable(struct usb_device_instance *device)
  644. {
  645. UDCDBGA("enable device %p, status %d", device, device->status);
  646. /* Save the device structure pointer */
  647. udc_device = device;
  648. /* Setup ep0 urb */
  649. if (!ep0_urb) {
  650. ep0_urb =
  651. usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array);
  652. } else {
  653. serial_printf("udc_enable: ep0_urb already allocated %p\n",
  654. ep0_urb);
  655. }
  656. writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
  657. }
  658. /**
  659. * udc_startup - allow udc code to do any additional startup
  660. */
  661. void udc_startup_events(struct usb_device_instance *device)
  662. {
  663. /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
  664. usbd_device_event_irq(device, DEVICE_INIT, 0);
  665. /*
  666. * The DEVICE_CREATE event puts the USB device in the state
  667. * STATE_ATTACHED.
  668. */
  669. usbd_device_event_irq(device, DEVICE_CREATE, 0);
  670. /*
  671. * Some USB controller driver implementations signal
  672. * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
  673. * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
  674. * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
  675. * The DW USB client controller has the capability to detect when the
  676. * USB cable is connected to a powered USB bus, so we will defer the
  677. * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
  678. */
  679. udc_enable(device);
  680. }
  681. /*
  682. * Plug detection interrupt handling
  683. */
  684. static void dw_udc_plug_irq(void)
  685. {
  686. if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) {
  687. /*
  688. * USB cable attached
  689. * Turn off PHY reset bit (PLUG detect).
  690. * Switch PHY opmode to normal operation (PLUG detect).
  691. */
  692. udc_connect();
  693. writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
  694. UDCDBG("device attached and powered");
  695. udc_state_transition(udc_device->device_state, STATE_POWERED);
  696. } else {
  697. writel(~0x0, &udc_regs_p->dev_int_mask);
  698. UDCDBG("device detached or unpowered");
  699. udc_state_transition(udc_device->device_state, STATE_ATTACHED);
  700. }
  701. }
  702. /*
  703. * Device interrupt handling
  704. */
  705. static void dw_udc_dev_irq(void)
  706. {
  707. if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) {
  708. writel(~0x0, &udc_regs_p->endp_int_mask);
  709. writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH,
  710. &inep_regs_p[0].endp_cntl);
  711. writel(DEV_INT_USBRESET, &udc_regs_p->dev_int);
  712. /*
  713. * This endpoint0 specific register can be programmed only
  714. * after the phy clock is initialized
  715. */
  716. writel((EP0_MAX_PACKET_SIZE << 19) | ENDP_EPTYPE_CNTL,
  717. &udc_regs_p->udc_endp_reg[0]);
  718. UDCDBG("device reset in progess");
  719. udc_state_transition(udc_device->device_state, STATE_DEFAULT);
  720. }
  721. /* Device Enumeration completed */
  722. if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) {
  723. writel(DEV_INT_ENUM, &udc_regs_p->dev_int);
  724. /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */
  725. writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001,
  726. &udc_regs_p->endp_int_mask);
  727. UDCDBG("default -> addressed");
  728. udc_state_transition(udc_device->device_state, STATE_ADDRESSED);
  729. }
  730. /* The USB will be in SUSPEND in 3 ms */
  731. if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) {
  732. writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int);
  733. UDCDBG("entering inactive state");
  734. /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */
  735. }
  736. /* SetConfiguration command received */
  737. if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) {
  738. writel(DEV_INT_SETCFG, &udc_regs_p->dev_int);
  739. UDCDBG("entering configured state");
  740. udc_state_transition(udc_device->device_state,
  741. STATE_CONFIGURED);
  742. }
  743. /* SetInterface command received */
  744. if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF)
  745. writel(DEV_INT_SETINTF, &udc_regs_p->dev_int);
  746. /* USB Suspend detected on cable */
  747. if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) {
  748. writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int);
  749. UDCDBG("entering suspended state");
  750. usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0);
  751. }
  752. /* USB Start-Of-Frame detected on cable */
  753. if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF)
  754. writel(DEV_INT_SOF, &udc_regs_p->dev_int);
  755. }
  756. /*
  757. * Endpoint interrupt handling
  758. */
  759. static void dw_udc_endpoint_irq(void)
  760. {
  761. while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) {
  762. writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int);
  763. if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK)
  764. == ENDP_STATUS_OUT_SETUP) {
  765. dw_udc_setup(udc_device->bus->endpoint_array + 0);
  766. writel(ENDP_STATUS_OUT_SETUP,
  767. &outep_regs_p[0].endp_status);
  768. } else if ((readl(&outep_regs_p[0].endp_status) &
  769. ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
  770. dw_udc_ep0_rx(udc_device->bus->endpoint_array + 0);
  771. writel(ENDP_STATUS_OUT_DATA,
  772. &outep_regs_p[0].endp_status);
  773. } else if ((readl(&outep_regs_p[0].endp_status) &
  774. ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
  775. /* NONE received */
  776. }
  777. writel(0x0, &outep_regs_p[0].endp_status);
  778. }
  779. if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) {
  780. dw_udc_ep0_tx(udc_device->bus->endpoint_array + 0);
  781. writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status);
  782. writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int);
  783. }
  784. if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) {
  785. u32 epnum = 0;
  786. u32 ep_int = readl(&udc_regs_p->endp_int) &
  787. ENDP_INT_NONISOOUT_MSK;
  788. ep_int >>= 16;
  789. while (0x0 == (ep_int & 0x1)) {
  790. ep_int >>= 1;
  791. epnum++;
  792. }
  793. writel((1 << 16) << epnum, &udc_regs_p->endp_int);
  794. if ((readl(&outep_regs_p[epnum].endp_status) &
  795. ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
  796. dw_udc_epn_rx(epnum);
  797. writel(ENDP_STATUS_OUT_DATA,
  798. &outep_regs_p[epnum].endp_status);
  799. } else if ((readl(&outep_regs_p[epnum].endp_status) &
  800. ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
  801. writel(0x0, &outep_regs_p[epnum].endp_status);
  802. }
  803. }
  804. if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) {
  805. u32 epnum = 0;
  806. u32 ep_int = readl(&udc_regs_p->endp_int) &
  807. ENDP_INT_NONISOIN_MSK;
  808. while (0x0 == (ep_int & 0x1)) {
  809. ep_int >>= 1;
  810. epnum++;
  811. }
  812. if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) {
  813. writel(ENDP_STATUS_IN,
  814. &outep_regs_p[epnum].endp_status);
  815. dw_udc_epn_tx(epnum);
  816. writel(ENDP_STATUS_IN,
  817. &outep_regs_p[epnum].endp_status);
  818. }
  819. writel((1 << epnum), &udc_regs_p->endp_int);
  820. }
  821. }
  822. /*
  823. * UDC interrupts
  824. */
  825. void udc_irq(void)
  826. {
  827. /*
  828. * Loop while we have interrupts.
  829. * If we don't do this, the input chain
  830. * polling delay is likely to miss
  831. * host requests.
  832. */
  833. while (readl(&plug_regs_p->plug_pending))
  834. dw_udc_plug_irq();
  835. while (readl(&udc_regs_p->dev_int))
  836. dw_udc_dev_irq();
  837. if (readl(&udc_regs_p->endp_int))
  838. dw_udc_endpoint_irq();
  839. }
  840. /* Flow control */
  841. void udc_set_nak(int epid)
  842. {
  843. writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
  844. &inep_regs_p[epid].endp_cntl);
  845. writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
  846. &outep_regs_p[epid].endp_cntl);
  847. }
  848. void udc_unset_nak(int epid)
  849. {
  850. u32 val;
  851. val = readl(&inep_regs_p[epid].endp_cntl);
  852. val &= ~ENDP_CNTL_SNAK;
  853. val |= ENDP_CNTL_CNAK;
  854. writel(val, &inep_regs_p[epid].endp_cntl);
  855. val = readl(&outep_regs_p[epid].endp_cntl);
  856. val &= ~ENDP_CNTL_SNAK;
  857. val |= ENDP_CNTL_CNAK;
  858. writel(val, &outep_regs_p[epid].endp_cntl);
  859. }