eth.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. * Dave Liu <daveliu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <part.h>
  9. #include <asm/io.h>
  10. #ifdef CONFIG_DM_ETH
  11. #include <dm.h>
  12. #include <dm/ofnode.h>
  13. #include <linux/compat.h>
  14. #include <phy_interface.h>
  15. #endif
  16. #include <malloc.h>
  17. #include <net.h>
  18. #include <hwconfig.h>
  19. #include <fm_eth.h>
  20. #include <fsl_mdio.h>
  21. #include <miiphy.h>
  22. #include <phy.h>
  23. #include <fsl_dtsec.h>
  24. #include <fsl_tgec.h>
  25. #include <fsl_memac.h>
  26. #include "fm.h"
  27. #ifndef CONFIG_DM_ETH
  28. static struct eth_device *devlist[NUM_FM_PORTS];
  29. static int num_controllers;
  30. #endif
  31. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
  32. #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
  33. TBIANA_FULL_DUPLEX)
  34. #define TBIANA_SGMII_ACK 0x4001
  35. #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
  36. TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
  37. /* Configure the TBI for SGMII operation */
  38. static void dtsec_configure_serdes(struct fm_eth *priv)
  39. {
  40. #ifdef CONFIG_SYS_FMAN_V3
  41. u32 value;
  42. struct mii_dev bus;
  43. bool sgmii_2500 = (priv->enet_if ==
  44. PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
  45. int i = 0, j;
  46. #ifndef CONFIG_DM_ETH
  47. bus.priv = priv->mac->phyregs;
  48. #else
  49. bus.priv = priv->pcs_mdio;
  50. #endif
  51. bus.read = memac_mdio_read;
  52. bus.write = memac_mdio_write;
  53. bus.reset = memac_mdio_reset;
  54. qsgmii_loop:
  55. /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
  56. if (sgmii_2500)
  57. value = PHY_SGMII_CR_PHY_RESET |
  58. PHY_SGMII_IF_SPEED_GIGABIT |
  59. PHY_SGMII_IF_MODE_SGMII;
  60. else
  61. value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
  62. for (j = 0; j <= 3; j++)
  63. debug("dump PCS reg %#x: %#x\n", j,
  64. memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
  65. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
  66. /* Dev ability according to SGMII specification */
  67. value = PHY_SGMII_DEV_ABILITY_SGMII;
  68. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
  69. if (sgmii_2500) {
  70. /* Adjust link timer for 2.5G SGMII,
  71. * 1.6 ms in units of 3.2 ns:
  72. * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
  73. */
  74. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
  75. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
  76. } else {
  77. /* Adjust link timer for SGMII,
  78. * 1.6 ms in units of 8 ns:
  79. * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
  80. */
  81. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
  82. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
  83. }
  84. /* Restart AN */
  85. value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
  86. memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
  87. if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
  88. i++;
  89. goto qsgmii_loop;
  90. }
  91. #else
  92. struct dtsec *regs = priv->mac->base;
  93. struct tsec_mii_mng *phyregs = priv->mac->phyregs;
  94. /*
  95. * Access TBI PHY registers at given TSEC register offset as
  96. * opposed to the register offset used for external PHY accesses
  97. */
  98. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
  99. TBICON_CLK_SELECT);
  100. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
  101. TBIANA_SGMII_ACK);
  102. tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
  103. TBI_CR, TBICR_SETTINGS);
  104. #endif
  105. }
  106. static void dtsec_init_phy(struct fm_eth *fm_eth)
  107. {
  108. #ifndef CONFIG_SYS_FMAN_V3
  109. struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
  110. /* Assign a Physical address to the TBI */
  111. out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
  112. #endif
  113. if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
  114. fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
  115. fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
  116. dtsec_configure_serdes(fm_eth);
  117. }
  118. #ifndef CONFIG_DM_ETH
  119. #ifdef CONFIG_PHYLIB
  120. static int tgec_is_fibre(struct fm_eth *fm)
  121. {
  122. char phyopt[20];
  123. sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
  124. return hwconfig_arg_cmp(phyopt, "xfi");
  125. }
  126. #endif
  127. #endif /* CONFIG_DM_ETH */
  128. #endif
  129. static u16 muram_readw(u16 *addr)
  130. {
  131. ulong base = (ulong)addr & ~0x3UL;
  132. u32 val32 = in_be32((void *)base);
  133. int byte_pos;
  134. u16 ret;
  135. byte_pos = (ulong)addr & 0x3UL;
  136. if (byte_pos)
  137. ret = (u16)(val32 & 0x0000ffff);
  138. else
  139. ret = (u16)((val32 & 0xffff0000) >> 16);
  140. return ret;
  141. }
  142. static void muram_writew(u16 *addr, u16 val)
  143. {
  144. ulong base = (ulong)addr & ~0x3UL;
  145. u32 org32 = in_be32((void *)base);
  146. u32 val32;
  147. int byte_pos;
  148. byte_pos = (ulong)addr & 0x3UL;
  149. if (byte_pos)
  150. val32 = (org32 & 0xffff0000) | val;
  151. else
  152. val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
  153. out_be32((void *)base, val32);
  154. }
  155. static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
  156. {
  157. int timeout = 1000000;
  158. clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
  159. /* wait until the rx port is not busy */
  160. while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
  161. ;
  162. if (!timeout)
  163. printf("%s - timeout\n", __func__);
  164. }
  165. static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
  166. {
  167. /* set BMI to independent mode, Rx port disable */
  168. out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
  169. /* clear FOF in IM case */
  170. out_be32(&rx_port->fmbm_rim, 0);
  171. /* Rx frame next engine -RISC */
  172. out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
  173. /* Rx command attribute - no order, MR[3] = 1 */
  174. clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
  175. setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
  176. /* enable Rx statistic counters */
  177. out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
  178. /* disable Rx performance counters */
  179. out_be32(&rx_port->fmbm_rpc, 0);
  180. }
  181. static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
  182. {
  183. int timeout = 1000000;
  184. clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
  185. /* wait until the tx port is not busy */
  186. while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
  187. ;
  188. if (!timeout)
  189. printf("%s - timeout\n", __func__);
  190. }
  191. static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
  192. {
  193. /* set BMI to independent mode, Tx port disable */
  194. out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
  195. /* Tx frame next engine -RISC */
  196. out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
  197. out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
  198. /* Tx command attribute - no order, MR[3] = 1 */
  199. clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
  200. setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
  201. /* enable Tx statistic counters */
  202. out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
  203. /* disable Tx performance counters */
  204. out_be32(&tx_port->fmbm_tpc, 0);
  205. }
  206. static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
  207. {
  208. struct fm_port_global_pram *pram;
  209. u32 pram_page_offset;
  210. void *rx_bd_ring_base;
  211. void *rx_buf_pool;
  212. u32 bd_ring_base_lo, bd_ring_base_hi;
  213. u32 buf_lo, buf_hi;
  214. struct fm_port_bd *rxbd;
  215. struct fm_port_qd *rxqd;
  216. struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
  217. int i;
  218. /* alloc global parameter ram at MURAM */
  219. pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
  220. FM_PRAM_SIZE, FM_PRAM_ALIGN);
  221. if (!pram) {
  222. printf("%s: No muram for Rx global parameter\n", __func__);
  223. return -ENOMEM;
  224. }
  225. fm_eth->rx_pram = pram;
  226. /* parameter page offset to MURAM */
  227. pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
  228. /* enable global mode- snooping data buffers and BDs */
  229. out_be32(&pram->mode, PRAM_MODE_GLOBAL);
  230. /* init the Rx queue descriptor pionter */
  231. out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
  232. /* set the max receive buffer length, power of 2 */
  233. muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
  234. /* alloc Rx buffer descriptors from main memory */
  235. rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
  236. * RX_BD_RING_SIZE);
  237. if (!rx_bd_ring_base)
  238. return -ENOMEM;
  239. memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
  240. * RX_BD_RING_SIZE);
  241. /* alloc Rx buffer from main memory */
  242. rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
  243. if (!rx_buf_pool)
  244. return -ENOMEM;
  245. memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
  246. debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
  247. /* save them to fm_eth */
  248. fm_eth->rx_bd_ring = rx_bd_ring_base;
  249. fm_eth->cur_rxbd = rx_bd_ring_base;
  250. fm_eth->rx_buf = rx_buf_pool;
  251. /* init Rx BDs ring */
  252. rxbd = (struct fm_port_bd *)rx_bd_ring_base;
  253. for (i = 0; i < RX_BD_RING_SIZE; i++) {
  254. muram_writew(&rxbd->status, RxBD_EMPTY);
  255. muram_writew(&rxbd->len, 0);
  256. buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
  257. i * MAX_RXBUF_LEN));
  258. buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
  259. i * MAX_RXBUF_LEN));
  260. muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
  261. out_be32(&rxbd->buf_ptr_lo, buf_lo);
  262. rxbd++;
  263. }
  264. /* set the Rx queue descriptor */
  265. rxqd = &pram->rxqd;
  266. muram_writew(&rxqd->gen, 0);
  267. bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
  268. bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
  269. muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
  270. out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
  271. muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
  272. * RX_BD_RING_SIZE);
  273. muram_writew(&rxqd->offset_in, 0);
  274. muram_writew(&rxqd->offset_out, 0);
  275. /* set IM parameter ram pointer to Rx Frame Queue ID */
  276. out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
  277. return 0;
  278. }
  279. static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
  280. {
  281. struct fm_port_global_pram *pram;
  282. u32 pram_page_offset;
  283. void *tx_bd_ring_base;
  284. u32 bd_ring_base_lo, bd_ring_base_hi;
  285. struct fm_port_bd *txbd;
  286. struct fm_port_qd *txqd;
  287. struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
  288. int i;
  289. /* alloc global parameter ram at MURAM */
  290. pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
  291. FM_PRAM_SIZE, FM_PRAM_ALIGN);
  292. if (!pram) {
  293. printf("%s: No muram for Tx global parameter\n", __func__);
  294. return -ENOMEM;
  295. }
  296. fm_eth->tx_pram = pram;
  297. /* parameter page offset to MURAM */
  298. pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
  299. /* enable global mode- snooping data buffers and BDs */
  300. out_be32(&pram->mode, PRAM_MODE_GLOBAL);
  301. /* init the Tx queue descriptor pionter */
  302. out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
  303. /* alloc Tx buffer descriptors from main memory */
  304. tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
  305. * TX_BD_RING_SIZE);
  306. if (!tx_bd_ring_base)
  307. return -ENOMEM;
  308. memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
  309. * TX_BD_RING_SIZE);
  310. /* save it to fm_eth */
  311. fm_eth->tx_bd_ring = tx_bd_ring_base;
  312. fm_eth->cur_txbd = tx_bd_ring_base;
  313. /* init Tx BDs ring */
  314. txbd = (struct fm_port_bd *)tx_bd_ring_base;
  315. for (i = 0; i < TX_BD_RING_SIZE; i++) {
  316. muram_writew(&txbd->status, TxBD_LAST);
  317. muram_writew(&txbd->len, 0);
  318. muram_writew(&txbd->buf_ptr_hi, 0);
  319. out_be32(&txbd->buf_ptr_lo, 0);
  320. txbd++;
  321. }
  322. /* set the Tx queue decriptor */
  323. txqd = &pram->txqd;
  324. bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
  325. bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
  326. muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
  327. out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
  328. muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
  329. * TX_BD_RING_SIZE);
  330. muram_writew(&txqd->offset_in, 0);
  331. muram_writew(&txqd->offset_out, 0);
  332. /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
  333. out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
  334. return 0;
  335. }
  336. static int fm_eth_init(struct fm_eth *fm_eth)
  337. {
  338. int ret;
  339. ret = fm_eth_rx_port_parameter_init(fm_eth);
  340. if (ret)
  341. return ret;
  342. ret = fm_eth_tx_port_parameter_init(fm_eth);
  343. if (ret)
  344. return ret;
  345. return 0;
  346. }
  347. static int fm_eth_startup(struct fm_eth *fm_eth)
  348. {
  349. struct fsl_enet_mac *mac;
  350. int ret;
  351. mac = fm_eth->mac;
  352. /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
  353. ret = fm_eth_init(fm_eth);
  354. if (ret)
  355. return ret;
  356. /* setup the MAC controller */
  357. mac->init_mac(mac);
  358. /* For some reason we need to set SPEED_100 */
  359. if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
  360. (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
  361. (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
  362. mac->set_if_mode)
  363. mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
  364. /* init bmi rx port, IM mode and disable */
  365. bmi_rx_port_init(fm_eth->rx_port);
  366. /* init bmi tx port, IM mode and disable */
  367. bmi_tx_port_init(fm_eth->tx_port);
  368. return 0;
  369. }
  370. static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
  371. {
  372. struct fm_port_global_pram *pram;
  373. pram = fm_eth->tx_pram;
  374. /* graceful stop transmission of frames */
  375. setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
  376. sync();
  377. }
  378. static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
  379. {
  380. struct fm_port_global_pram *pram;
  381. pram = fm_eth->tx_pram;
  382. /* re-enable transmission of frames */
  383. clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
  384. sync();
  385. }
  386. #ifndef CONFIG_DM_ETH
  387. static int fm_eth_open(struct eth_device *dev, bd_t *bd)
  388. #else
  389. static int fm_eth_open(struct udevice *dev)
  390. #endif
  391. {
  392. #ifndef CONFIG_DM_ETH
  393. struct fm_eth *fm_eth = dev->priv;
  394. #else
  395. struct eth_pdata *pdata = dev_get_platdata(dev);
  396. struct fm_eth *fm_eth = dev_get_priv(dev);
  397. #endif
  398. unsigned char *enetaddr;
  399. struct fsl_enet_mac *mac;
  400. #ifdef CONFIG_PHYLIB
  401. int ret;
  402. #endif
  403. mac = fm_eth->mac;
  404. #ifndef CONFIG_DM_ETH
  405. enetaddr = &dev->enetaddr[0];
  406. #else
  407. enetaddr = pdata->enetaddr;
  408. #endif
  409. /* setup the MAC address */
  410. if (enetaddr[0] & 0x01) {
  411. printf("%s: MacAddress is multicast address\n", __func__);
  412. enetaddr[0] = 0;
  413. enetaddr[5] = fm_eth->num;
  414. }
  415. mac->set_mac_addr(mac, enetaddr);
  416. /* enable bmi Rx port */
  417. setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
  418. /* enable MAC rx/tx port */
  419. mac->enable_mac(mac);
  420. /* enable bmi Tx port */
  421. setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
  422. /* re-enable transmission of frame */
  423. fmc_tx_port_graceful_stop_disable(fm_eth);
  424. #ifdef CONFIG_PHYLIB
  425. if (fm_eth->phydev) {
  426. ret = phy_startup(fm_eth->phydev);
  427. if (ret) {
  428. #ifndef CONFIG_DM_ETH
  429. printf("%s: Could not initialize\n",
  430. fm_eth->phydev->dev->name);
  431. #else
  432. printf("%s: Could not initialize\n", dev->name);
  433. #endif
  434. return ret;
  435. }
  436. } else {
  437. return 0;
  438. }
  439. #else
  440. fm_eth->phydev->speed = SPEED_1000;
  441. fm_eth->phydev->link = 1;
  442. fm_eth->phydev->duplex = DUPLEX_FULL;
  443. #endif
  444. /* set the MAC-PHY mode */
  445. mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
  446. debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
  447. fm_eth->phydev->speed, fm_eth->phydev->link);
  448. if (!fm_eth->phydev->link)
  449. printf("%s: No link.\n", fm_eth->phydev->dev->name);
  450. return fm_eth->phydev->link ? 0 : -1;
  451. }
  452. #ifndef CONFIG_DM_ETH
  453. static void fm_eth_halt(struct eth_device *dev)
  454. #else
  455. static void fm_eth_halt(struct udevice *dev)
  456. #endif
  457. {
  458. struct fm_eth *fm_eth;
  459. struct fsl_enet_mac *mac;
  460. fm_eth = (struct fm_eth *)dev->priv;
  461. mac = fm_eth->mac;
  462. /* graceful stop the transmission of frames */
  463. fmc_tx_port_graceful_stop_enable(fm_eth);
  464. /* disable bmi Tx port */
  465. bmi_tx_port_disable(fm_eth->tx_port);
  466. /* disable MAC rx/tx port */
  467. mac->disable_mac(mac);
  468. /* disable bmi Rx port */
  469. bmi_rx_port_disable(fm_eth->rx_port);
  470. #ifdef CONFIG_PHYLIB
  471. if (fm_eth->phydev)
  472. phy_shutdown(fm_eth->phydev);
  473. #endif
  474. }
  475. #ifndef CONFIG_DM_ETH
  476. static int fm_eth_send(struct eth_device *dev, void *buf, int len)
  477. #else
  478. static int fm_eth_send(struct udevice *dev, void *buf, int len)
  479. #endif
  480. {
  481. struct fm_eth *fm_eth;
  482. struct fm_port_global_pram *pram;
  483. struct fm_port_bd *txbd, *txbd_base;
  484. u16 offset_in;
  485. int i;
  486. fm_eth = (struct fm_eth *)dev->priv;
  487. pram = fm_eth->tx_pram;
  488. txbd = fm_eth->cur_txbd;
  489. /* find one empty TxBD */
  490. for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
  491. udelay(100);
  492. if (i > 0x1000) {
  493. printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
  494. dev->name, muram_readw(&txbd->status));
  495. return 0;
  496. }
  497. }
  498. /* setup TxBD */
  499. muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
  500. out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
  501. muram_writew(&txbd->len, len);
  502. sync();
  503. muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
  504. sync();
  505. /* update TxQD, let RISC to send the packet */
  506. offset_in = muram_readw(&pram->txqd.offset_in);
  507. offset_in += sizeof(struct fm_port_bd);
  508. if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
  509. offset_in = 0;
  510. muram_writew(&pram->txqd.offset_in, offset_in);
  511. sync();
  512. /* wait for buffer to be transmitted */
  513. for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
  514. udelay(100);
  515. if (i > 0x10000) {
  516. printf("%s: Tx error, txbd->status = 0x%x\n",
  517. dev->name, muram_readw(&txbd->status));
  518. return 0;
  519. }
  520. }
  521. /* advance the TxBD */
  522. txbd++;
  523. txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
  524. if (txbd >= (txbd_base + TX_BD_RING_SIZE))
  525. txbd = txbd_base;
  526. /* update current txbd */
  527. fm_eth->cur_txbd = (void *)txbd;
  528. return 1;
  529. }
  530. static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
  531. struct fm_port_bd *rxbd)
  532. {
  533. struct fm_port_global_pram *pram;
  534. struct fm_port_bd *rxbd_base;
  535. u16 offset_out;
  536. pram = fm_eth->rx_pram;
  537. /* clear the RxBDs */
  538. muram_writew(&rxbd->status, RxBD_EMPTY);
  539. muram_writew(&rxbd->len, 0);
  540. sync();
  541. /* advance RxBD */
  542. rxbd++;
  543. rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
  544. if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
  545. rxbd = rxbd_base;
  546. /* update RxQD */
  547. offset_out = muram_readw(&pram->rxqd.offset_out);
  548. offset_out += sizeof(struct fm_port_bd);
  549. if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
  550. offset_out = 0;
  551. muram_writew(&pram->rxqd.offset_out, offset_out);
  552. sync();
  553. return rxbd;
  554. }
  555. #ifndef CONFIG_DM_ETH
  556. static int fm_eth_recv(struct eth_device *dev)
  557. #else
  558. static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  559. #endif
  560. {
  561. struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
  562. struct fm_port_bd *rxbd = fm_eth->cur_rxbd;
  563. u32 buf_lo, buf_hi;
  564. u16 status, len;
  565. int ret = -1;
  566. u8 *data;
  567. status = muram_readw(&rxbd->status);
  568. while (!(status & RxBD_EMPTY)) {
  569. if (!(status & RxBD_ERROR)) {
  570. buf_hi = muram_readw(&rxbd->buf_ptr_hi);
  571. buf_lo = in_be32(&rxbd->buf_ptr_lo);
  572. data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
  573. len = muram_readw(&rxbd->len);
  574. #ifndef CONFIG_DM_ETH
  575. net_process_received_packet(data, len);
  576. #else
  577. *packetp = data;
  578. return len;
  579. #endif
  580. } else {
  581. printf("%s: Rx error\n", dev->name);
  582. ret = 0;
  583. }
  584. /* free current bd, advance to next one */
  585. rxbd = fm_eth_free_one(fm_eth, rxbd);
  586. /* read next status */
  587. status = muram_readw(&rxbd->status);
  588. }
  589. fm_eth->cur_rxbd = (void *)rxbd;
  590. return ret;
  591. }
  592. #ifdef CONFIG_DM_ETH
  593. static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  594. {
  595. struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
  596. fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
  597. return 0;
  598. }
  599. #endif /* CONFIG_DM_ETH */
  600. #ifndef CONFIG_DM_ETH
  601. static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
  602. {
  603. struct fsl_enet_mac *mac;
  604. int num;
  605. void *base, *phyregs = NULL;
  606. num = fm_eth->num;
  607. #ifdef CONFIG_SYS_FMAN_V3
  608. #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  609. if (fm_eth->type == FM_ETH_10G_E) {
  610. /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
  611. * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
  612. * 10GEC1 uses mEMAC1 on T1024.
  613. * so it needs to change the num.
  614. */
  615. if (fm_eth->num >= 2)
  616. num -= 2;
  617. else
  618. num += 8;
  619. }
  620. #endif
  621. base = &reg->memac[num].fm_memac;
  622. phyregs = &reg->memac[num].fm_memac_mdio;
  623. #else
  624. /* Get the mac registers base address */
  625. if (fm_eth->type == FM_ETH_1G_E) {
  626. base = &reg->mac_1g[num].fm_dtesc;
  627. phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
  628. } else {
  629. base = &reg->mac_10g[num].fm_10gec;
  630. phyregs = &reg->mac_10g[num].fm_10gec_mdio;
  631. }
  632. #endif
  633. /* alloc mac controller */
  634. mac = malloc(sizeof(struct fsl_enet_mac));
  635. if (!mac)
  636. return -ENOMEM;
  637. memset(mac, 0, sizeof(struct fsl_enet_mac));
  638. /* save the mac to fm_eth struct */
  639. fm_eth->mac = mac;
  640. #ifdef CONFIG_SYS_FMAN_V3
  641. init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
  642. #else
  643. if (fm_eth->type == FM_ETH_1G_E)
  644. init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
  645. else
  646. init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
  647. #endif
  648. return 0;
  649. }
  650. #else /* CONFIG_DM_ETH */
  651. static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
  652. {
  653. #ifndef CONFIG_SYS_FMAN_V3
  654. void *mdio;
  655. #endif
  656. fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
  657. if (!fm_eth->mac)
  658. return -ENOMEM;
  659. #ifndef CONFIG_SYS_FMAN_V3
  660. mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
  661. debug("MDIO %d @ %p\n", fm_eth->num, mdio);
  662. #endif
  663. switch (fm_eth->mac_type) {
  664. #ifdef CONFIG_SYS_FMAN_V3
  665. case FM_MEMAC:
  666. init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
  667. break;
  668. #else
  669. case FM_DTSEC:
  670. init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
  671. break;
  672. case FM_TGEC:
  673. init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
  674. break;
  675. #endif
  676. }
  677. return 0;
  678. }
  679. #endif /* CONFIG_DM_ETH */
  680. static int init_phy(struct fm_eth *fm_eth)
  681. {
  682. #ifdef CONFIG_PHYLIB
  683. u32 supported = PHY_GBIT_FEATURES;
  684. #ifndef CONFIG_DM_ETH
  685. struct phy_device *phydev = NULL;
  686. #endif
  687. if (fm_eth->type == FM_ETH_10G_E)
  688. supported = PHY_10G_FEATURES;
  689. if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
  690. supported |= SUPPORTED_2500baseX_Full;
  691. #endif
  692. if (fm_eth->type == FM_ETH_1G_E)
  693. dtsec_init_phy(fm_eth);
  694. #ifdef CONFIG_DM_ETH
  695. #ifdef CONFIG_PHYLIB
  696. #ifdef CONFIG_DM_MDIO
  697. fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
  698. if (!fm_eth->phydev)
  699. return -ENODEV;
  700. #endif
  701. fm_eth->phydev->advertising &= supported;
  702. fm_eth->phydev->supported &= supported;
  703. phy_config(fm_eth->phydev);
  704. #endif
  705. #else /* CONFIG_DM_ETH */
  706. #ifdef CONFIG_PHYLIB
  707. if (fm_eth->bus) {
  708. phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
  709. fm_eth->enet_if);
  710. if (!phydev) {
  711. printf("Failed to connect\n");
  712. return -1;
  713. }
  714. } else {
  715. return 0;
  716. }
  717. if (fm_eth->type == FM_ETH_1G_E) {
  718. supported = (SUPPORTED_10baseT_Half |
  719. SUPPORTED_10baseT_Full |
  720. SUPPORTED_100baseT_Half |
  721. SUPPORTED_100baseT_Full |
  722. SUPPORTED_1000baseT_Full);
  723. } else {
  724. supported = SUPPORTED_10000baseT_Full;
  725. if (tgec_is_fibre(fm_eth))
  726. phydev->port = PORT_FIBRE;
  727. }
  728. phydev->supported &= supported;
  729. phydev->advertising = phydev->supported;
  730. fm_eth->phydev = phydev;
  731. phy_config(phydev);
  732. #endif
  733. #endif /* CONFIG_DM_ETH */
  734. return 0;
  735. }
  736. #ifndef CONFIG_DM_ETH
  737. int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
  738. {
  739. struct eth_device *dev;
  740. struct fm_eth *fm_eth;
  741. int i, num = info->num;
  742. int ret;
  743. /* alloc eth device */
  744. dev = (struct eth_device *)malloc(sizeof(struct eth_device));
  745. if (!dev)
  746. return -ENOMEM;
  747. memset(dev, 0, sizeof(struct eth_device));
  748. /* alloc the FMan ethernet private struct */
  749. fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
  750. if (!fm_eth)
  751. return -ENOMEM;
  752. memset(fm_eth, 0, sizeof(struct fm_eth));
  753. /* save off some things we need from the info struct */
  754. fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
  755. fm_eth->num = num;
  756. fm_eth->type = info->type;
  757. fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
  758. fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
  759. /* set the ethernet max receive length */
  760. fm_eth->max_rx_len = MAX_RXBUF_LEN;
  761. /* init global mac structure */
  762. ret = fm_eth_init_mac(fm_eth, reg);
  763. if (ret)
  764. return ret;
  765. /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
  766. if (fm_eth->type == FM_ETH_1G_E)
  767. sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
  768. else
  769. sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
  770. devlist[num_controllers++] = dev;
  771. dev->iobase = 0;
  772. dev->priv = (void *)fm_eth;
  773. dev->init = fm_eth_open;
  774. dev->halt = fm_eth_halt;
  775. dev->send = fm_eth_send;
  776. dev->recv = fm_eth_recv;
  777. fm_eth->dev = dev;
  778. fm_eth->bus = info->bus;
  779. fm_eth->phyaddr = info->phy_addr;
  780. fm_eth->enet_if = info->enet_if;
  781. /* startup the FM im */
  782. ret = fm_eth_startup(fm_eth);
  783. if (ret)
  784. return ret;
  785. init_phy(fm_eth);
  786. /* clear the ethernet address */
  787. for (i = 0; i < 6; i++)
  788. dev->enetaddr[i] = 0;
  789. eth_register(dev);
  790. return 0;
  791. }
  792. #else /* CONFIG_DM_ETH */
  793. #ifdef CONFIG_PHYLIB
  794. phy_interface_t fman_read_sys_if(struct udevice *dev)
  795. {
  796. const char *if_str;
  797. if_str = ofnode_read_string(dev->node, "phy-connection-type");
  798. debug("MAC system interface mode %s\n", if_str);
  799. return phy_get_interface_by_name(if_str);
  800. }
  801. #endif
  802. static int fm_eth_bind(struct udevice *dev)
  803. {
  804. char mac_name[11];
  805. u32 fm, num;
  806. if (ofnode_read_u32(ofnode_get_parent(dev->node), "cell-index", &fm)) {
  807. printf("FMan node property cell-index missing\n");
  808. return -EINVAL;
  809. }
  810. if (dev && dev_read_u32(dev, "cell-index", &num)) {
  811. printf("FMan MAC node property cell-index missing\n");
  812. return -EINVAL;
  813. }
  814. sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
  815. device_set_name(dev, mac_name);
  816. debug("%s - binding %s\n", __func__, mac_name);
  817. return 0;
  818. }
  819. static struct udevice *fm_get_internal_mdio(struct udevice *dev)
  820. {
  821. struct ofnode_phandle_args phandle = {.node = ofnode_null()};
  822. struct udevice *mdiodev;
  823. if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
  824. 0, 0, &phandle) ||
  825. !ofnode_valid(phandle.node)) {
  826. if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
  827. 0, 0, &phandle) ||
  828. !ofnode_valid(phandle.node)) {
  829. printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
  830. dev->name);
  831. return NULL;
  832. }
  833. }
  834. if (uclass_get_device_by_ofnode(UCLASS_MDIO,
  835. ofnode_get_parent(phandle.node),
  836. &mdiodev)) {
  837. printf("can't find MDIO bus for node %s\n",
  838. ofnode_get_name(ofnode_get_parent(phandle.node)));
  839. return NULL;
  840. }
  841. debug("Found internal MDIO bus %p\n", mdiodev);
  842. return mdiodev;
  843. }
  844. static int fm_eth_probe(struct udevice *dev)
  845. {
  846. struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
  847. struct ofnode_phandle_args args;
  848. void *reg;
  849. int ret, index;
  850. debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
  851. (dev) ? dev->name : "-");
  852. if (fm_eth->dev) {
  853. printf("%s already probed, exit\n", (dev) ? dev->name : "-");
  854. return 0;
  855. }
  856. fm_eth->dev = dev;
  857. fm_eth->fm_index = fman_id(dev->parent);
  858. reg = (void *)(uintptr_t)dev_read_addr(dev);
  859. fm_eth->mac_type = dev_get_driver_data(dev);
  860. #ifdef CONFIG_PHYLIB
  861. fm_eth->enet_if = fman_read_sys_if(dev);
  862. #else
  863. fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
  864. printf("%s: warning - unable to determine interface type\n", __func__);
  865. #endif
  866. switch (fm_eth->mac_type) {
  867. #ifndef CONFIG_SYS_FMAN_V3
  868. case FM_TGEC:
  869. fm_eth->type = FM_ETH_10G_E;
  870. break;
  871. case FM_DTSEC:
  872. #else
  873. case FM_MEMAC:
  874. /* default to 1G, 10G is indicated by port property in dts */
  875. #endif
  876. fm_eth->type = FM_ETH_1G_E;
  877. break;
  878. }
  879. if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
  880. printf("FMan MAC node property cell-index missing\n");
  881. return -EINVAL;
  882. }
  883. if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
  884. 0, 0, &args))
  885. goto ports_ref_failure;
  886. index = ofnode_read_u32_default(args.node, "cell-index", 0);
  887. if (index <= 0)
  888. goto ports_ref_failure;
  889. fm_eth->rx_port = fman_port(dev->parent, index);
  890. if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
  891. fm_eth->type = FM_ETH_10G_E;
  892. if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
  893. 0, 1, &args))
  894. goto ports_ref_failure;
  895. index = ofnode_read_u32_default(args.node, "cell-index", 0);
  896. if (index <= 0)
  897. goto ports_ref_failure;
  898. fm_eth->tx_port = fman_port(dev->parent, index);
  899. /* set the ethernet max receive length */
  900. fm_eth->max_rx_len = MAX_RXBUF_LEN;
  901. switch (fm_eth->enet_if) {
  902. case PHY_INTERFACE_MODE_QSGMII:
  903. /* all PCS blocks are accessed on one controller */
  904. if (fm_eth->num != 0)
  905. break;
  906. case PHY_INTERFACE_MODE_SGMII:
  907. case PHY_INTERFACE_MODE_SGMII_2500:
  908. fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
  909. break;
  910. default:
  911. break;
  912. }
  913. /* init global mac structure */
  914. ret = fm_eth_init_mac(fm_eth, reg);
  915. if (ret)
  916. return ret;
  917. /* startup the FM im */
  918. ret = fm_eth_startup(fm_eth);
  919. if (!ret)
  920. ret = init_phy(fm_eth);
  921. return ret;
  922. ports_ref_failure:
  923. printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
  924. return -ENOENT;
  925. }
  926. static int fm_eth_remove(struct udevice *dev)
  927. {
  928. return 0;
  929. }
  930. static const struct eth_ops fm_eth_ops = {
  931. .start = fm_eth_open,
  932. .send = fm_eth_send,
  933. .recv = fm_eth_recv,
  934. .free_pkt = fm_eth_free_pkt,
  935. .stop = fm_eth_halt,
  936. };
  937. static const struct udevice_id fm_eth_ids[] = {
  938. #ifdef CONFIG_SYS_FMAN_V3
  939. { .compatible = "fsl,fman-memac", .data = FM_MEMAC },
  940. #else
  941. { .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
  942. { .compatible = "fsl,fman-xgec", .data = FM_TGEC },
  943. #endif
  944. {}
  945. };
  946. U_BOOT_DRIVER(eth_fman) = {
  947. .name = "eth_fman",
  948. .id = UCLASS_ETH,
  949. .of_match = fm_eth_ids,
  950. .bind = fm_eth_bind,
  951. .probe = fm_eth_probe,
  952. .remove = fm_eth_remove,
  953. .ops = &fm_eth_ops,
  954. .priv_auto_alloc_size = sizeof(struct fm_eth),
  955. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  956. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  957. };
  958. #endif /* CONFIG_DM_ETH */