b4860.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Freescale Semiconductor, Inc.
  4. * Roy Zang <tie-fei.zang@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <phy.h>
  9. #include <fm_eth.h>
  10. #include <asm/io.h>
  11. #include <asm/immap_85xx.h>
  12. #include <asm/fsl_serdes.h>
  13. #include <hwconfig.h>
  14. u32 port_to_devdisr[] = {
  15. [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  16. [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  17. [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  18. [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  19. [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
  20. [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
  21. [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
  22. [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
  23. };
  24. static int is_device_disabled(enum fm_port port)
  25. {
  26. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  27. u32 devdisr2 = in_be32(&gur->devdisr2);
  28. return port_to_devdisr[port] & devdisr2;
  29. }
  30. void fman_disable_port(enum fm_port port)
  31. {
  32. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  33. setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  34. }
  35. void fman_enable_port(enum fm_port port)
  36. {
  37. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  38. clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  39. }
  40. phy_interface_t fman_port_enet_if(enum fm_port port)
  41. {
  42. #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
  43. u32 serdes2_prtcl;
  44. char buffer[HWCONFIG_BUFFER_SIZE];
  45. char *buf = NULL;
  46. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  47. #endif
  48. if (is_device_disabled(port))
  49. return PHY_INTERFACE_MODE_NONE;
  50. /*B4860 has two 10Gig Mac*/
  51. if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
  52. ((is_serdes_configured(XAUI_FM1_MAC9)) ||
  53. #if (!defined(CONFIG_TARGET_B4860QDS) && \
  54. !defined(CONFIG_TARGET_B4R420QDS))
  55. (is_serdes_configured(XFI_FM1_MAC9)) ||
  56. (is_serdes_configured(XFI_FM1_MAC10)) ||
  57. #endif
  58. (is_serdes_configured(XAUI_FM1_MAC10))
  59. ))
  60. return PHY_INTERFACE_MODE_XGMII;
  61. #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
  62. serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
  63. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  64. if (serdes2_prtcl) {
  65. serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  66. switch (serdes2_prtcl) {
  67. case 0x80:
  68. case 0x81:
  69. case 0x82:
  70. case 0x83:
  71. case 0x84:
  72. case 0x85:
  73. case 0x86:
  74. case 0x87:
  75. case 0x88:
  76. case 0x89:
  77. case 0x8a:
  78. case 0x8b:
  79. case 0x8c:
  80. case 0x8d:
  81. case 0x8e:
  82. case 0xb1:
  83. case 0xb2:
  84. /*
  85. * Extract hwconfig from environment since environment
  86. * is not setup yet
  87. */
  88. env_get_f("hwconfig", buffer, sizeof(buffer));
  89. buf = buffer;
  90. /* check if XFI interface enable in hwconfig for 10g */
  91. if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
  92. "sfp_amc", "sfp", buf)) {
  93. if ((port == FM1_10GEC1 ||
  94. port == FM1_10GEC2) &&
  95. ((is_serdes_configured(XFI_FM1_MAC9)) ||
  96. (is_serdes_configured(XFI_FM1_MAC10))))
  97. return PHY_INTERFACE_MODE_XGMII;
  98. else if ((port == FM1_DTSEC1) ||
  99. (port == FM1_DTSEC2) ||
  100. (port == FM1_DTSEC3) ||
  101. (port == FM1_DTSEC4))
  102. return PHY_INTERFACE_MODE_NONE;
  103. }
  104. }
  105. }
  106. #endif
  107. /* Fix me need to handle RGMII here first */
  108. switch (port) {
  109. case FM1_DTSEC1:
  110. case FM1_DTSEC2:
  111. case FM1_DTSEC3:
  112. case FM1_DTSEC4:
  113. case FM1_DTSEC5:
  114. case FM1_DTSEC6:
  115. if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  116. return PHY_INTERFACE_MODE_SGMII;
  117. break;
  118. default:
  119. return PHY_INTERFACE_MODE_NONE;
  120. }
  121. return PHY_INTERFACE_MODE_NONE;
  122. }