st_smi.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
  5. */
  6. #include <common.h>
  7. #include <flash.h>
  8. #include <linux/err.h>
  9. #include <linux/mtd/st_smi.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/hardware.h>
  12. #if defined(CONFIG_MTD_NOR_FLASH)
  13. static struct smi_regs *const smicntl =
  14. (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
  15. static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] =
  16. CONFIG_SYS_FLASH_ADDR_BASE;
  17. flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  18. /* data structure to maintain flash ids from different vendors */
  19. struct flash_device {
  20. char *name;
  21. u8 erase_cmd;
  22. u32 device_id;
  23. u32 pagesize;
  24. unsigned long sectorsize;
  25. unsigned long size_in_bytes;
  26. };
  27. #define FLASH_ID(n, es, id, psize, ssize, size) \
  28. { \
  29. .name = n, \
  30. .erase_cmd = es, \
  31. .device_id = id, \
  32. .pagesize = psize, \
  33. .sectorsize = ssize, \
  34. .size_in_bytes = size \
  35. }
  36. /*
  37. * List of supported flash devices.
  38. * Currently the erase_cmd field is not used in this driver.
  39. */
  40. static struct flash_device flash_devices[] = {
  41. FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
  42. FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
  43. FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
  44. FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
  45. FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000),
  46. FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000),
  47. FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
  48. FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
  49. FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
  50. FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
  51. FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
  52. FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
  53. FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
  54. FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
  55. FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
  56. FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
  57. FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
  58. FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
  59. FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000),
  60. FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000),
  61. FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000),
  62. FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
  63. FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
  64. FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000),
  65. FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000),
  66. FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000),
  67. FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
  68. FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
  69. FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000),
  70. FLASH_ID("wbd w25q128" , 0xd8, 0x001840EF, 0x100, 0x10000, 0x1000000),
  71. };
  72. /*
  73. * smi_wait_xfer_finish - Wait until TFF is set in status register
  74. * @timeout: timeout in milliseconds
  75. *
  76. * Wait until TFF is set in status register
  77. */
  78. static int smi_wait_xfer_finish(int timeout)
  79. {
  80. ulong start = get_timer(0);
  81. while (get_timer(start) < timeout) {
  82. if (readl(&smicntl->smi_sr) & TFF)
  83. return 0;
  84. /* Try after 10 ms */
  85. udelay(10);
  86. };
  87. return -1;
  88. }
  89. /*
  90. * smi_read_id - Read flash id
  91. * @info: flash_info structure pointer
  92. * @banknum: bank number
  93. *
  94. * Read the flash id present at bank #banknum
  95. */
  96. static unsigned int smi_read_id(flash_info_t *info, int banknum)
  97. {
  98. unsigned int value;
  99. writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
  100. writel(READ_ID, &smicntl->smi_tr);
  101. writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
  102. &smicntl->smi_cr2);
  103. if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
  104. return -EIO;
  105. value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
  106. writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr);
  107. writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
  108. return value;
  109. }
  110. /*
  111. * flash_get_size - Detect the SMI flash by reading the ID.
  112. * @base: Base address of the flash area bank #banknum
  113. * @banknum: Bank number
  114. *
  115. * Detect the SMI flash by reading the ID. Initializes the flash_info structure
  116. * with size, sector count etc.
  117. */
  118. static ulong flash_get_size(ulong base, int banknum)
  119. {
  120. flash_info_t *info = &flash_info[banknum];
  121. int value;
  122. int i;
  123. value = smi_read_id(info, banknum);
  124. if (value < 0) {
  125. printf("Flash id could not be read\n");
  126. return 0;
  127. }
  128. /* Matches chip-id to entire list of 'serial-nor flash' ids */
  129. for (i = 0; i < ARRAY_SIZE(flash_devices); i++) {
  130. if (flash_devices[i].device_id == value) {
  131. info->size = flash_devices[i].size_in_bytes;
  132. info->flash_id = value;
  133. info->start[0] = base;
  134. info->sector_count =
  135. info->size/flash_devices[i].sectorsize;
  136. return info->size;
  137. }
  138. }
  139. return 0;
  140. }
  141. /*
  142. * smi_read_sr - Read status register of SMI
  143. * @bank: bank number
  144. *
  145. * This routine will get the status register of the flash chip present at the
  146. * given bank
  147. */
  148. static int smi_read_sr(int bank)
  149. {
  150. u32 ctrlreg1, val;
  151. /* store the CTRL REG1 state */
  152. ctrlreg1 = readl(&smicntl->smi_cr1);
  153. /* Program SMI in HW Mode */
  154. writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE),
  155. &smicntl->smi_cr1);
  156. /* Performing a RSR instruction in HW mode */
  157. writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
  158. if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
  159. return -1;
  160. val = readl(&smicntl->smi_sr);
  161. /* Restore the CTRL REG1 state */
  162. writel(ctrlreg1, &smicntl->smi_cr1);
  163. return val;
  164. }
  165. /*
  166. * smi_wait_till_ready - Wait till last operation is over.
  167. * @bank: bank number shifted.
  168. * @timeout: timeout in milliseconds.
  169. *
  170. * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0)
  171. * The routine checks for #timeout loops, each at interval of 1 milli-second.
  172. * If successful the routine returns 0.
  173. */
  174. static int smi_wait_till_ready(int bank, int timeout)
  175. {
  176. int sr;
  177. ulong start = get_timer(0);
  178. /* One chip guarantees max 5 msec wait here after page writes,
  179. but potentially three seconds (!) after page erase. */
  180. while (get_timer(start) < timeout) {
  181. sr = smi_read_sr(bank);
  182. if ((sr >= 0) && (!(sr & WIP_BIT)))
  183. return 0;
  184. /* Try again after 10 usec */
  185. udelay(10);
  186. } while (timeout--);
  187. printf("SMI controller is still in wait, timeout=%d\n", timeout);
  188. return -EIO;
  189. }
  190. /*
  191. * smi_write_enable - Enable the flash to do write operation
  192. * @bank: bank number
  193. *
  194. * Set write enable latch with Write Enable command.
  195. * Returns negative if error occurred.
  196. */
  197. static int smi_write_enable(int bank)
  198. {
  199. u32 ctrlreg1;
  200. u32 start;
  201. int timeout = WMODE_TOUT;
  202. int sr;
  203. /* Store the CTRL REG1 state */
  204. ctrlreg1 = readl(&smicntl->smi_cr1);
  205. /* Program SMI in H/W Mode */
  206. writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
  207. /* Give the Flash, Write Enable command */
  208. writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
  209. if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
  210. return -1;
  211. /* Restore the CTRL REG1 state */
  212. writel(ctrlreg1, &smicntl->smi_cr1);
  213. start = get_timer(0);
  214. while (get_timer(start) < timeout) {
  215. sr = smi_read_sr(bank);
  216. if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT))))
  217. return 0;
  218. /* Try again after 10 usec */
  219. udelay(10);
  220. };
  221. return -1;
  222. }
  223. /*
  224. * smi_init - SMI initialization routine
  225. *
  226. * SMI initialization routine. Sets SMI control register1.
  227. */
  228. void smi_init(void)
  229. {
  230. /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
  231. writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
  232. &smicntl->smi_cr1);
  233. }
  234. /*
  235. * smi_sector_erase - Erase flash sector
  236. * @info: flash_info structure pointer
  237. * @sector: sector number
  238. *
  239. * Set write enable latch with Write Enable command.
  240. * Returns negative if error occurred.
  241. */
  242. static int smi_sector_erase(flash_info_t *info, unsigned int sector)
  243. {
  244. int bank;
  245. unsigned int sect_add;
  246. unsigned int instruction;
  247. switch (info->start[0]) {
  248. case SMIBANK0_BASE:
  249. bank = BANK0;
  250. break;
  251. case SMIBANK1_BASE:
  252. bank = BANK1;
  253. break;
  254. case SMIBANK2_BASE:
  255. bank = BANK2;
  256. break;
  257. case SMIBANK3_BASE:
  258. bank = BANK3;
  259. break;
  260. default:
  261. return -1;
  262. }
  263. sect_add = sector * (info->size / info->sector_count);
  264. instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE;
  265. writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
  266. /* Wait until finished previous write command. */
  267. if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
  268. return -EBUSY;
  269. /* Send write enable, before erase commands. */
  270. if (smi_write_enable(bank))
  271. return -EIO;
  272. /* Put SMI in SW mode */
  273. writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
  274. /* Send Sector Erase command in SW Mode */
  275. writel(instruction, &smicntl->smi_tr);
  276. writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
  277. &smicntl->smi_cr2);
  278. if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
  279. return -EIO;
  280. if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
  281. return -EBUSY;
  282. /* Put SMI in HW mode */
  283. writel(readl(&smicntl->smi_cr1) & ~SW_MODE,
  284. &smicntl->smi_cr1);
  285. return 0;
  286. }
  287. /*
  288. * smi_write - Write to SMI flash
  289. * @src_addr: source buffer
  290. * @dst_addr: destination buffer
  291. * @length: length to write in bytes
  292. * @bank: bank base address
  293. *
  294. * Write to SMI flash
  295. */
  296. static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
  297. unsigned int length, ulong bank_addr)
  298. {
  299. u8 *src_addr8 = (u8 *)src_addr;
  300. u8 *dst_addr8 = (u8 *)dst_addr;
  301. int banknum;
  302. int i;
  303. switch (bank_addr) {
  304. case SMIBANK0_BASE:
  305. banknum = BANK0;
  306. break;
  307. case SMIBANK1_BASE:
  308. banknum = BANK1;
  309. break;
  310. case SMIBANK2_BASE:
  311. banknum = BANK2;
  312. break;
  313. case SMIBANK3_BASE:
  314. banknum = BANK3;
  315. break;
  316. default:
  317. return -1;
  318. }
  319. if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
  320. return -EBUSY;
  321. /* Set SMI in Hardware Mode */
  322. writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
  323. if (smi_write_enable(banknum))
  324. return -EIO;
  325. /* Perform the write command */
  326. for (i = 0; i < length; i += 4) {
  327. if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
  328. if (smi_wait_till_ready(banknum,
  329. CONFIG_SYS_FLASH_WRITE_TOUT))
  330. return -EBUSY;
  331. if (smi_write_enable(banknum))
  332. return -EIO;
  333. }
  334. if (length < 4) {
  335. int k;
  336. /*
  337. * Handle special case, where length < 4 (redundant env)
  338. */
  339. for (k = 0; k < length; k++)
  340. *dst_addr8++ = *src_addr8++;
  341. } else {
  342. /* Normal 32bit write */
  343. *dst_addr++ = *src_addr++;
  344. }
  345. if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))
  346. return -EIO;
  347. }
  348. if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
  349. return -EBUSY;
  350. writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr);
  351. return 0;
  352. }
  353. /*
  354. * write_buff - Write to SMI flash
  355. * @info: flash info structure
  356. * @src: source buffer
  357. * @dest_addr: destination buffer
  358. * @length: length to write in words
  359. *
  360. * Write to SMI flash
  361. */
  362. int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
  363. {
  364. return smi_write((unsigned int *)src, (unsigned int *)dest_addr,
  365. length, info->start[0]);
  366. }
  367. /*
  368. * flash_init - SMI flash initialization
  369. *
  370. * SMI flash initialization
  371. */
  372. unsigned long flash_init(void)
  373. {
  374. unsigned long size = 0;
  375. int i, j;
  376. smi_init();
  377. for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
  378. flash_info[i].flash_id = FLASH_UNKNOWN;
  379. size += flash_info[i].size = flash_get_size(bank_base[i], i);
  380. }
  381. for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
  382. for (i = 1; i < flash_info[j].sector_count; i++)
  383. flash_info[j].start[i] =
  384. flash_info[j].start[i - 1] +
  385. flash_info->size / flash_info->sector_count;
  386. }
  387. return size;
  388. }
  389. /*
  390. * flash_print_info - Print SMI flash information
  391. *
  392. * Print SMI flash information
  393. */
  394. void flash_print_info(flash_info_t *info)
  395. {
  396. int i;
  397. if (info->flash_id == FLASH_UNKNOWN) {
  398. puts("missing or unknown FLASH type\n");
  399. return;
  400. }
  401. if (info->size >= 0x100000)
  402. printf(" Size: %ld MB in %d Sectors\n",
  403. info->size >> 20, info->sector_count);
  404. else
  405. printf(" Size: %ld KB in %d Sectors\n",
  406. info->size >> 10, info->sector_count);
  407. puts(" Sector Start Addresses:");
  408. for (i = 0; i < info->sector_count; ++i) {
  409. #ifdef CONFIG_SYS_FLASH_EMPTY_INFO
  410. int size;
  411. int erased;
  412. u32 *flash;
  413. /*
  414. * Check if whole sector is erased
  415. */
  416. size = (info->size) / (info->sector_count);
  417. flash = (u32 *) info->start[i];
  418. size = size / sizeof(int);
  419. while ((size--) && (*flash++ == ~0))
  420. ;
  421. size++;
  422. if (size)
  423. erased = 0;
  424. else
  425. erased = 1;
  426. if ((i % 5) == 0)
  427. printf("\n");
  428. printf(" %08lX%s%s",
  429. info->start[i],
  430. erased ? " E" : " ", info->protect[i] ? "RO " : " ");
  431. #else
  432. if ((i % 5) == 0)
  433. printf("\n ");
  434. printf(" %08lX%s",
  435. info->start[i], info->protect[i] ? " (RO) " : " ");
  436. #endif
  437. }
  438. putc('\n');
  439. return;
  440. }
  441. /*
  442. * flash_erase - Erase SMI flash
  443. *
  444. * Erase SMI flash
  445. */
  446. int flash_erase(flash_info_t *info, int s_first, int s_last)
  447. {
  448. int rcode = 0;
  449. int prot = 0;
  450. flash_sect_t sect;
  451. if ((s_first < 0) || (s_first > s_last)) {
  452. puts("- no sectors to erase\n");
  453. return 1;
  454. }
  455. for (sect = s_first; sect <= s_last; ++sect) {
  456. if (info->protect[sect])
  457. prot++;
  458. }
  459. if (prot) {
  460. printf("- Warning: %d protected sectors will not be erased!\n",
  461. prot);
  462. } else {
  463. putc('\n');
  464. }
  465. for (sect = s_first; sect <= s_last; sect++) {
  466. if (info->protect[sect] == 0) {
  467. if (smi_sector_erase(info, sect))
  468. rcode = 1;
  469. else
  470. putc('.');
  471. }
  472. }
  473. puts(" done\n");
  474. return rcode;
  475. }
  476. #endif