spi-nor-core.c 68 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
  4. * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
  5. *
  6. * Copyright (C) 2005, Intec Automation Inc.
  7. * Copyright (C) 2014, Freescale Semiconductor, Inc.
  8. *
  9. * Synced from Linux v4.19
  10. */
  11. #include <common.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/devres.h>
  14. #include <linux/err.h>
  15. #include <linux/errno.h>
  16. #include <linux/log2.h>
  17. #include <linux/math64.h>
  18. #include <linux/sizes.h>
  19. #include <linux/mtd/mtd.h>
  20. #include <linux/mtd/spi-nor.h>
  21. #include <spi-mem.h>
  22. #include <spi.h>
  23. #include "sf_internal.h"
  24. /* Define max times to check status register before we give up. */
  25. /*
  26. * For everything but full-chip erase; probably could be much smaller, but kept
  27. * around for safety for now
  28. */
  29. #define HZ CONFIG_SYS_HZ
  30. #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
  31. static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
  32. *op, void *buf)
  33. {
  34. if (op->data.dir == SPI_MEM_DATA_IN)
  35. op->data.buf.in = buf;
  36. else
  37. op->data.buf.out = buf;
  38. return spi_mem_exec_op(nor->spi, op);
  39. }
  40. static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
  41. {
  42. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
  43. SPI_MEM_OP_NO_ADDR,
  44. SPI_MEM_OP_NO_DUMMY,
  45. SPI_MEM_OP_DATA_IN(len, NULL, 1));
  46. int ret;
  47. ret = spi_nor_read_write_reg(nor, &op, val);
  48. if (ret < 0)
  49. dev_dbg(nor->dev, "error %d reading %x\n", ret, code);
  50. return ret;
  51. }
  52. static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  53. {
  54. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
  55. SPI_MEM_OP_NO_ADDR,
  56. SPI_MEM_OP_NO_DUMMY,
  57. SPI_MEM_OP_DATA_OUT(len, NULL, 1));
  58. return spi_nor_read_write_reg(nor, &op, buf);
  59. }
  60. static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
  61. u_char *buf)
  62. {
  63. struct spi_mem_op op =
  64. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
  65. SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
  66. SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
  67. SPI_MEM_OP_DATA_IN(len, buf, 1));
  68. size_t remaining = len;
  69. int ret;
  70. /* get transfer protocols. */
  71. op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
  72. op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
  73. op.dummy.buswidth = op.addr.buswidth;
  74. op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
  75. /* convert the dummy cycles to the number of bytes */
  76. op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
  77. while (remaining) {
  78. op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
  79. ret = spi_mem_adjust_op_size(nor->spi, &op);
  80. if (ret)
  81. return ret;
  82. ret = spi_mem_exec_op(nor->spi, &op);
  83. if (ret)
  84. return ret;
  85. op.addr.val += op.data.nbytes;
  86. remaining -= op.data.nbytes;
  87. op.data.buf.in += op.data.nbytes;
  88. }
  89. return len;
  90. }
  91. static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
  92. const u_char *buf)
  93. {
  94. struct spi_mem_op op =
  95. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
  96. SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
  97. SPI_MEM_OP_NO_DUMMY,
  98. SPI_MEM_OP_DATA_OUT(len, buf, 1));
  99. int ret;
  100. /* get transfer protocols. */
  101. op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
  102. op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
  103. op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
  104. if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
  105. op.addr.nbytes = 0;
  106. ret = spi_mem_adjust_op_size(nor->spi, &op);
  107. if (ret)
  108. return ret;
  109. op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
  110. ret = spi_mem_exec_op(nor->spi, &op);
  111. if (ret)
  112. return ret;
  113. return op.data.nbytes;
  114. }
  115. /*
  116. * Read the status register, returning its value in the location
  117. * Return the status register value.
  118. * Returns negative if error occurred.
  119. */
  120. static int read_sr(struct spi_nor *nor)
  121. {
  122. int ret;
  123. u8 val;
  124. ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
  125. if (ret < 0) {
  126. pr_debug("error %d reading SR\n", (int)ret);
  127. return ret;
  128. }
  129. return val;
  130. }
  131. /*
  132. * Read the flag status register, returning its value in the location
  133. * Return the status register value.
  134. * Returns negative if error occurred.
  135. */
  136. static int read_fsr(struct spi_nor *nor)
  137. {
  138. int ret;
  139. u8 val;
  140. ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
  141. if (ret < 0) {
  142. pr_debug("error %d reading FSR\n", ret);
  143. return ret;
  144. }
  145. return val;
  146. }
  147. /*
  148. * Read configuration register, returning its value in the
  149. * location. Return the configuration register value.
  150. * Returns negative if error occurred.
  151. */
  152. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  153. static int read_cr(struct spi_nor *nor)
  154. {
  155. int ret;
  156. u8 val;
  157. ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
  158. if (ret < 0) {
  159. dev_dbg(nor->dev, "error %d reading CR\n", ret);
  160. return ret;
  161. }
  162. return val;
  163. }
  164. #endif
  165. /*
  166. * Write status register 1 byte
  167. * Returns negative if error occurred.
  168. */
  169. static int write_sr(struct spi_nor *nor, u8 val)
  170. {
  171. nor->cmd_buf[0] = val;
  172. return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
  173. }
  174. /*
  175. * Set write enable latch with Write Enable command.
  176. * Returns negative if error occurred.
  177. */
  178. static int write_enable(struct spi_nor *nor)
  179. {
  180. return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
  181. }
  182. /*
  183. * Send write disable instruction to the chip.
  184. */
  185. static int write_disable(struct spi_nor *nor)
  186. {
  187. return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
  188. }
  189. static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
  190. {
  191. return mtd->priv;
  192. }
  193. #ifndef CONFIG_SPI_FLASH_BAR
  194. static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
  195. {
  196. size_t i;
  197. for (i = 0; i < size; i++)
  198. if (table[i][0] == opcode)
  199. return table[i][1];
  200. /* No conversion found, keep input op code. */
  201. return opcode;
  202. }
  203. static u8 spi_nor_convert_3to4_read(u8 opcode)
  204. {
  205. static const u8 spi_nor_3to4_read[][2] = {
  206. { SPINOR_OP_READ, SPINOR_OP_READ_4B },
  207. { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
  208. { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
  209. { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
  210. { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
  211. { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
  212. { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
  213. { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
  214. { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
  215. { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
  216. { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
  217. };
  218. return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
  219. ARRAY_SIZE(spi_nor_3to4_read));
  220. }
  221. static u8 spi_nor_convert_3to4_program(u8 opcode)
  222. {
  223. static const u8 spi_nor_3to4_program[][2] = {
  224. { SPINOR_OP_PP, SPINOR_OP_PP_4B },
  225. { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
  226. { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
  227. { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
  228. { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
  229. };
  230. return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
  231. ARRAY_SIZE(spi_nor_3to4_program));
  232. }
  233. static u8 spi_nor_convert_3to4_erase(u8 opcode)
  234. {
  235. static const u8 spi_nor_3to4_erase[][2] = {
  236. { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
  237. { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
  238. { SPINOR_OP_SE, SPINOR_OP_SE_4B },
  239. };
  240. return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
  241. ARRAY_SIZE(spi_nor_3to4_erase));
  242. }
  243. static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
  244. const struct flash_info *info)
  245. {
  246. /* Do some manufacturer fixups first */
  247. switch (JEDEC_MFR(info)) {
  248. case SNOR_MFR_SPANSION:
  249. /* No small sector erase for 4-byte command set */
  250. nor->erase_opcode = SPINOR_OP_SE;
  251. nor->mtd.erasesize = info->sector_size;
  252. break;
  253. default:
  254. break;
  255. }
  256. nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
  257. nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
  258. nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
  259. }
  260. #endif /* !CONFIG_SPI_FLASH_BAR */
  261. /* Enable/disable 4-byte addressing mode. */
  262. static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
  263. int enable)
  264. {
  265. int status;
  266. bool need_wren = false;
  267. u8 cmd;
  268. switch (JEDEC_MFR(info)) {
  269. case SNOR_MFR_ST:
  270. case SNOR_MFR_MICRON:
  271. /* Some Micron need WREN command; all will accept it */
  272. need_wren = true;
  273. case SNOR_MFR_ISSI:
  274. case SNOR_MFR_MACRONIX:
  275. case SNOR_MFR_WINBOND:
  276. if (need_wren)
  277. write_enable(nor);
  278. cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
  279. status = nor->write_reg(nor, cmd, NULL, 0);
  280. if (need_wren)
  281. write_disable(nor);
  282. if (!status && !enable &&
  283. JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
  284. /*
  285. * On Winbond W25Q256FV, leaving 4byte mode causes
  286. * the Extended Address Register to be set to 1, so all
  287. * 3-byte-address reads come from the second 16M.
  288. * We must clear the register to enable normal behavior.
  289. */
  290. write_enable(nor);
  291. nor->cmd_buf[0] = 0;
  292. nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
  293. write_disable(nor);
  294. }
  295. return status;
  296. default:
  297. /* Spansion style */
  298. nor->cmd_buf[0] = enable << 7;
  299. return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
  300. }
  301. }
  302. static int spi_nor_sr_ready(struct spi_nor *nor)
  303. {
  304. int sr = read_sr(nor);
  305. if (sr < 0)
  306. return sr;
  307. if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
  308. if (sr & SR_E_ERR)
  309. dev_dbg(nor->dev, "Erase Error occurred\n");
  310. else
  311. dev_dbg(nor->dev, "Programming Error occurred\n");
  312. nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
  313. return -EIO;
  314. }
  315. return !(sr & SR_WIP);
  316. }
  317. static int spi_nor_fsr_ready(struct spi_nor *nor)
  318. {
  319. int fsr = read_fsr(nor);
  320. if (fsr < 0)
  321. return fsr;
  322. if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
  323. if (fsr & FSR_E_ERR)
  324. dev_err(nor->dev, "Erase operation failed.\n");
  325. else
  326. dev_err(nor->dev, "Program operation failed.\n");
  327. if (fsr & FSR_PT_ERR)
  328. dev_err(nor->dev,
  329. "Attempted to modify a protected sector.\n");
  330. nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
  331. return -EIO;
  332. }
  333. return fsr & FSR_READY;
  334. }
  335. static int spi_nor_ready(struct spi_nor *nor)
  336. {
  337. int sr, fsr;
  338. sr = spi_nor_sr_ready(nor);
  339. if (sr < 0)
  340. return sr;
  341. fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
  342. if (fsr < 0)
  343. return fsr;
  344. return sr && fsr;
  345. }
  346. /*
  347. * Service routine to read status register until ready, or timeout occurs.
  348. * Returns non-zero if error.
  349. */
  350. static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
  351. unsigned long timeout)
  352. {
  353. unsigned long timebase;
  354. int ret;
  355. timebase = get_timer(0);
  356. while (get_timer(timebase) < timeout) {
  357. ret = spi_nor_ready(nor);
  358. if (ret < 0)
  359. return ret;
  360. if (ret)
  361. return 0;
  362. }
  363. dev_err(nor->dev, "flash operation timed out\n");
  364. return -ETIMEDOUT;
  365. }
  366. static int spi_nor_wait_till_ready(struct spi_nor *nor)
  367. {
  368. return spi_nor_wait_till_ready_with_timeout(nor,
  369. DEFAULT_READY_WAIT_JIFFIES);
  370. }
  371. #ifdef CONFIG_SPI_FLASH_BAR
  372. /*
  373. * This "clean_bar" is necessary in a situation when one was accessing
  374. * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
  375. *
  376. * After it the BA24 bit shall be cleared to allow access to correct
  377. * memory region after SW reset (by calling "reset" command).
  378. *
  379. * Otherwise, the BA24 bit may be left set and then after reset, the
  380. * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
  381. */
  382. static int clean_bar(struct spi_nor *nor)
  383. {
  384. u8 cmd, bank_sel = 0;
  385. if (nor->bank_curr == 0)
  386. return 0;
  387. cmd = nor->bank_write_cmd;
  388. nor->bank_curr = 0;
  389. write_enable(nor);
  390. return nor->write_reg(nor, cmd, &bank_sel, 1);
  391. }
  392. static int write_bar(struct spi_nor *nor, u32 offset)
  393. {
  394. u8 cmd, bank_sel;
  395. int ret;
  396. bank_sel = offset / SZ_16M;
  397. if (bank_sel == nor->bank_curr)
  398. goto bar_end;
  399. cmd = nor->bank_write_cmd;
  400. write_enable(nor);
  401. ret = nor->write_reg(nor, cmd, &bank_sel, 1);
  402. if (ret < 0) {
  403. debug("SF: fail to write bank register\n");
  404. return ret;
  405. }
  406. bar_end:
  407. nor->bank_curr = bank_sel;
  408. return nor->bank_curr;
  409. }
  410. static int read_bar(struct spi_nor *nor, const struct flash_info *info)
  411. {
  412. u8 curr_bank = 0;
  413. int ret;
  414. switch (JEDEC_MFR(info)) {
  415. case SNOR_MFR_SPANSION:
  416. nor->bank_read_cmd = SPINOR_OP_BRRD;
  417. nor->bank_write_cmd = SPINOR_OP_BRWR;
  418. break;
  419. default:
  420. nor->bank_read_cmd = SPINOR_OP_RDEAR;
  421. nor->bank_write_cmd = SPINOR_OP_WREAR;
  422. }
  423. ret = nor->read_reg(nor, nor->bank_read_cmd,
  424. &curr_bank, 1);
  425. if (ret) {
  426. debug("SF: fail to read bank addr register\n");
  427. return ret;
  428. }
  429. nor->bank_curr = curr_bank;
  430. return 0;
  431. }
  432. #endif
  433. /*
  434. * Initiate the erasure of a single sector
  435. */
  436. static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
  437. {
  438. struct spi_mem_op op =
  439. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1),
  440. SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
  441. SPI_MEM_OP_NO_DUMMY,
  442. SPI_MEM_OP_NO_DATA);
  443. if (nor->erase)
  444. return nor->erase(nor, addr);
  445. /*
  446. * Default implementation, if driver doesn't have a specialized HW
  447. * control
  448. */
  449. return spi_mem_exec_op(nor->spi, &op);
  450. }
  451. /*
  452. * Erase an address range on the nor chip. The address range may extend
  453. * one or more erase sectors. Return an error is there is a problem erasing.
  454. */
  455. static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
  456. {
  457. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  458. u32 addr, len, rem;
  459. int ret;
  460. dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
  461. (long long)instr->len);
  462. if (!instr->len)
  463. return 0;
  464. div_u64_rem(instr->len, mtd->erasesize, &rem);
  465. if (rem)
  466. return -EINVAL;
  467. addr = instr->addr;
  468. len = instr->len;
  469. while (len) {
  470. #ifdef CONFIG_SPI_FLASH_BAR
  471. ret = write_bar(nor, addr);
  472. if (ret < 0)
  473. return ret;
  474. #endif
  475. write_enable(nor);
  476. ret = spi_nor_erase_sector(nor, addr);
  477. if (ret)
  478. goto erase_err;
  479. addr += mtd->erasesize;
  480. len -= mtd->erasesize;
  481. ret = spi_nor_wait_till_ready(nor);
  482. if (ret)
  483. goto erase_err;
  484. }
  485. erase_err:
  486. #ifdef CONFIG_SPI_FLASH_BAR
  487. ret = clean_bar(nor);
  488. #endif
  489. write_disable(nor);
  490. return ret;
  491. }
  492. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  493. /* Write status register and ensure bits in mask match written values */
  494. static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
  495. {
  496. int ret;
  497. write_enable(nor);
  498. ret = write_sr(nor, status_new);
  499. if (ret)
  500. return ret;
  501. ret = spi_nor_wait_till_ready(nor);
  502. if (ret)
  503. return ret;
  504. ret = read_sr(nor);
  505. if (ret < 0)
  506. return ret;
  507. return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
  508. }
  509. static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
  510. uint64_t *len)
  511. {
  512. struct mtd_info *mtd = &nor->mtd;
  513. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  514. int shift = ffs(mask) - 1;
  515. int pow;
  516. if (!(sr & mask)) {
  517. /* No protection */
  518. *ofs = 0;
  519. *len = 0;
  520. } else {
  521. pow = ((sr & mask) ^ mask) >> shift;
  522. *len = mtd->size >> pow;
  523. if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
  524. *ofs = 0;
  525. else
  526. *ofs = mtd->size - *len;
  527. }
  528. }
  529. /*
  530. * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
  531. * @locked is false); 0 otherwise
  532. */
  533. static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
  534. u8 sr, bool locked)
  535. {
  536. loff_t lock_offs;
  537. uint64_t lock_len;
  538. if (!len)
  539. return 1;
  540. stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
  541. if (locked)
  542. /* Requested range is a sub-range of locked range */
  543. return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
  544. else
  545. /* Requested range does not overlap with locked range */
  546. return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
  547. }
  548. static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  549. u8 sr)
  550. {
  551. return stm_check_lock_status_sr(nor, ofs, len, sr, true);
  552. }
  553. static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  554. u8 sr)
  555. {
  556. return stm_check_lock_status_sr(nor, ofs, len, sr, false);
  557. }
  558. /*
  559. * Lock a region of the flash. Compatible with ST Micro and similar flash.
  560. * Supports the block protection bits BP{0,1,2} in the status register
  561. * (SR). Does not support these features found in newer SR bitfields:
  562. * - SEC: sector/block protect - only handle SEC=0 (block protect)
  563. * - CMP: complement protect - only support CMP=0 (range is not complemented)
  564. *
  565. * Support for the following is provided conditionally for some flash:
  566. * - TB: top/bottom protect
  567. *
  568. * Sample table portion for 8MB flash (Winbond w25q64fw):
  569. *
  570. * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
  571. * --------------------------------------------------------------------------
  572. * X | X | 0 | 0 | 0 | NONE | NONE
  573. * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
  574. * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
  575. * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
  576. * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
  577. * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
  578. * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
  579. * X | X | 1 | 1 | 1 | 8 MB | ALL
  580. * ------|-------|-------|-------|-------|---------------|-------------------
  581. * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
  582. * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
  583. * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
  584. * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
  585. * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
  586. * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
  587. *
  588. * Returns negative on errors, 0 on success.
  589. */
  590. static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  591. {
  592. struct mtd_info *mtd = &nor->mtd;
  593. int status_old, status_new;
  594. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  595. u8 shift = ffs(mask) - 1, pow, val;
  596. loff_t lock_len;
  597. bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
  598. bool use_top;
  599. status_old = read_sr(nor);
  600. if (status_old < 0)
  601. return status_old;
  602. /* If nothing in our range is unlocked, we don't need to do anything */
  603. if (stm_is_locked_sr(nor, ofs, len, status_old))
  604. return 0;
  605. /* If anything below us is unlocked, we can't use 'bottom' protection */
  606. if (!stm_is_locked_sr(nor, 0, ofs, status_old))
  607. can_be_bottom = false;
  608. /* If anything above us is unlocked, we can't use 'top' protection */
  609. if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
  610. status_old))
  611. can_be_top = false;
  612. if (!can_be_bottom && !can_be_top)
  613. return -EINVAL;
  614. /* Prefer top, if both are valid */
  615. use_top = can_be_top;
  616. /* lock_len: length of region that should end up locked */
  617. if (use_top)
  618. lock_len = mtd->size - ofs;
  619. else
  620. lock_len = ofs + len;
  621. /*
  622. * Need smallest pow such that:
  623. *
  624. * 1 / (2^pow) <= (len / size)
  625. *
  626. * so (assuming power-of-2 size) we do:
  627. *
  628. * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
  629. */
  630. pow = ilog2(mtd->size) - ilog2(lock_len);
  631. val = mask - (pow << shift);
  632. if (val & ~mask)
  633. return -EINVAL;
  634. /* Don't "lock" with no region! */
  635. if (!(val & mask))
  636. return -EINVAL;
  637. status_new = (status_old & ~mask & ~SR_TB) | val;
  638. /* Disallow further writes if WP pin is asserted */
  639. status_new |= SR_SRWD;
  640. if (!use_top)
  641. status_new |= SR_TB;
  642. /* Don't bother if they're the same */
  643. if (status_new == status_old)
  644. return 0;
  645. /* Only modify protection if it will not unlock other areas */
  646. if ((status_new & mask) < (status_old & mask))
  647. return -EINVAL;
  648. return write_sr_and_check(nor, status_new, mask);
  649. }
  650. /*
  651. * Unlock a region of the flash. See stm_lock() for more info
  652. *
  653. * Returns negative on errors, 0 on success.
  654. */
  655. static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  656. {
  657. struct mtd_info *mtd = &nor->mtd;
  658. int status_old, status_new;
  659. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  660. u8 shift = ffs(mask) - 1, pow, val;
  661. loff_t lock_len;
  662. bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
  663. bool use_top;
  664. status_old = read_sr(nor);
  665. if (status_old < 0)
  666. return status_old;
  667. /* If nothing in our range is locked, we don't need to do anything */
  668. if (stm_is_unlocked_sr(nor, ofs, len, status_old))
  669. return 0;
  670. /* If anything below us is locked, we can't use 'top' protection */
  671. if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
  672. can_be_top = false;
  673. /* If anything above us is locked, we can't use 'bottom' protection */
  674. if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
  675. status_old))
  676. can_be_bottom = false;
  677. if (!can_be_bottom && !can_be_top)
  678. return -EINVAL;
  679. /* Prefer top, if both are valid */
  680. use_top = can_be_top;
  681. /* lock_len: length of region that should remain locked */
  682. if (use_top)
  683. lock_len = mtd->size - (ofs + len);
  684. else
  685. lock_len = ofs;
  686. /*
  687. * Need largest pow such that:
  688. *
  689. * 1 / (2^pow) >= (len / size)
  690. *
  691. * so (assuming power-of-2 size) we do:
  692. *
  693. * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
  694. */
  695. pow = ilog2(mtd->size) - order_base_2(lock_len);
  696. if (lock_len == 0) {
  697. val = 0; /* fully unlocked */
  698. } else {
  699. val = mask - (pow << shift);
  700. /* Some power-of-two sizes are not supported */
  701. if (val & ~mask)
  702. return -EINVAL;
  703. }
  704. status_new = (status_old & ~mask & ~SR_TB) | val;
  705. /* Don't protect status register if we're fully unlocked */
  706. if (lock_len == 0)
  707. status_new &= ~SR_SRWD;
  708. if (!use_top)
  709. status_new |= SR_TB;
  710. /* Don't bother if they're the same */
  711. if (status_new == status_old)
  712. return 0;
  713. /* Only modify protection if it will not lock other areas */
  714. if ((status_new & mask) > (status_old & mask))
  715. return -EINVAL;
  716. return write_sr_and_check(nor, status_new, mask);
  717. }
  718. /*
  719. * Check if a region of the flash is (completely) locked. See stm_lock() for
  720. * more info.
  721. *
  722. * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
  723. * negative on errors.
  724. */
  725. static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  726. {
  727. int status;
  728. status = read_sr(nor);
  729. if (status < 0)
  730. return status;
  731. return stm_is_locked_sr(nor, ofs, len, status);
  732. }
  733. #endif /* CONFIG_SPI_FLASH_STMICRO */
  734. static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
  735. {
  736. int tmp;
  737. u8 id[SPI_NOR_MAX_ID_LEN];
  738. const struct flash_info *info;
  739. tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
  740. if (tmp < 0) {
  741. dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
  742. return ERR_PTR(tmp);
  743. }
  744. info = spi_nor_ids;
  745. for (; info->name; info++) {
  746. if (info->id_len) {
  747. if (!memcmp(info->id, id, info->id_len))
  748. return info;
  749. }
  750. }
  751. dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
  752. id[0], id[1], id[2]);
  753. return ERR_PTR(-ENODEV);
  754. }
  755. static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
  756. size_t *retlen, u_char *buf)
  757. {
  758. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  759. int ret;
  760. dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
  761. while (len) {
  762. loff_t addr = from;
  763. size_t read_len = len;
  764. #ifdef CONFIG_SPI_FLASH_BAR
  765. u32 remain_len;
  766. ret = write_bar(nor, addr);
  767. if (ret < 0)
  768. return log_ret(ret);
  769. remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
  770. if (len < remain_len)
  771. read_len = len;
  772. else
  773. read_len = remain_len;
  774. #endif
  775. ret = nor->read(nor, addr, read_len, buf);
  776. if (ret == 0) {
  777. /* We shouldn't see 0-length reads */
  778. ret = -EIO;
  779. goto read_err;
  780. }
  781. if (ret < 0)
  782. goto read_err;
  783. *retlen += ret;
  784. buf += ret;
  785. from += ret;
  786. len -= ret;
  787. }
  788. ret = 0;
  789. read_err:
  790. #ifdef CONFIG_SPI_FLASH_BAR
  791. ret = clean_bar(nor);
  792. #endif
  793. return ret;
  794. }
  795. #ifdef CONFIG_SPI_FLASH_SST
  796. /*
  797. * sst26 flash series has its own block protection implementation:
  798. * 4x - 8 KByte blocks - read & write protection bits - upper addresses
  799. * 1x - 32 KByte blocks - write protection bits
  800. * rest - 64 KByte blocks - write protection bits
  801. * 1x - 32 KByte blocks - write protection bits
  802. * 4x - 8 KByte blocks - read & write protection bits - lower addresses
  803. *
  804. * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
  805. * will be treated as single block.
  806. */
  807. #define SST26_BPR_8K_NUM 4
  808. #define SST26_MAX_BPR_REG_LEN (18 + 1)
  809. #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
  810. enum lock_ctl {
  811. SST26_CTL_LOCK,
  812. SST26_CTL_UNLOCK,
  813. SST26_CTL_CHECK
  814. };
  815. static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
  816. {
  817. switch (ctl) {
  818. case SST26_CTL_LOCK:
  819. cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
  820. break;
  821. case SST26_CTL_UNLOCK:
  822. cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
  823. break;
  824. case SST26_CTL_CHECK:
  825. return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
  826. }
  827. return false;
  828. }
  829. /*
  830. * Lock, unlock or check lock status of the flash region of the flash (depending
  831. * on the lock_ctl value)
  832. */
  833. static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
  834. {
  835. struct mtd_info *mtd = &nor->mtd;
  836. u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
  837. bool lower_64k = false, upper_64k = false;
  838. u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
  839. int ret;
  840. /* Check length and offset for 64k alignment */
  841. if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
  842. dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
  843. return -EINVAL;
  844. }
  845. if (ofs + len > mtd->size) {
  846. dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
  847. ofs, len, mtd->size);
  848. return -EINVAL;
  849. }
  850. /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
  851. if (mtd->size != SZ_2M &&
  852. mtd->size != SZ_4M &&
  853. mtd->size != SZ_8M)
  854. return -EINVAL;
  855. bpr_size = 2 + (mtd->size / SZ_64K / 8);
  856. ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
  857. if (ret < 0) {
  858. dev_err(nor->dev, "fail to read block-protection register\n");
  859. return ret;
  860. }
  861. rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
  862. lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
  863. upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
  864. lower_64k = (ofs < SST26_BOUND_REG_SIZE);
  865. /* Lower bits in block-protection register are about 64k region */
  866. bpr_ptr = lptr_64k / SZ_64K - 1;
  867. /* Process 64K blocks region */
  868. while (lptr_64k < rptr_64k) {
  869. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  870. return EACCES;
  871. bpr_ptr++;
  872. lptr_64k += SZ_64K;
  873. }
  874. /* 32K and 8K region bits in BPR are after 64k region bits */
  875. bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
  876. /* Process lower 32K block region */
  877. if (lower_64k)
  878. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  879. return EACCES;
  880. bpr_ptr++;
  881. /* Process upper 32K block region */
  882. if (upper_64k)
  883. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  884. return EACCES;
  885. bpr_ptr++;
  886. /* Process lower 8K block regions */
  887. for (i = 0; i < SST26_BPR_8K_NUM; i++) {
  888. if (lower_64k)
  889. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  890. return EACCES;
  891. /* In 8K area BPR has both read and write protection bits */
  892. bpr_ptr += 2;
  893. }
  894. /* Process upper 8K block regions */
  895. for (i = 0; i < SST26_BPR_8K_NUM; i++) {
  896. if (upper_64k)
  897. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  898. return EACCES;
  899. /* In 8K area BPR has both read and write protection bits */
  900. bpr_ptr += 2;
  901. }
  902. /* If we check region status we don't need to write BPR back */
  903. if (ctl == SST26_CTL_CHECK)
  904. return 0;
  905. ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
  906. if (ret < 0) {
  907. dev_err(nor->dev, "fail to write block-protection register\n");
  908. return ret;
  909. }
  910. return 0;
  911. }
  912. static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  913. {
  914. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
  915. }
  916. static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  917. {
  918. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
  919. }
  920. /*
  921. * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
  922. * and negative on errors.
  923. */
  924. static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  925. {
  926. /*
  927. * is_locked function is used for check before reading or erasing flash
  928. * region, so offset and length might be not 64k allighned, so adjust
  929. * them to be 64k allighned as sst26_lock_ctl works only with 64k
  930. * allighned regions.
  931. */
  932. ofs -= ofs & (SZ_64K - 1);
  933. len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
  934. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
  935. }
  936. static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
  937. size_t *retlen, const u_char *buf)
  938. {
  939. size_t actual;
  940. int ret = 0;
  941. for (actual = 0; actual < len; actual++) {
  942. nor->program_opcode = SPINOR_OP_BP;
  943. write_enable(nor);
  944. /* write one byte. */
  945. ret = nor->write(nor, to, 1, buf + actual);
  946. if (ret < 0)
  947. goto sst_write_err;
  948. ret = spi_nor_wait_till_ready(nor);
  949. if (ret)
  950. goto sst_write_err;
  951. to++;
  952. }
  953. sst_write_err:
  954. write_disable(nor);
  955. return ret;
  956. }
  957. static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
  958. size_t *retlen, const u_char *buf)
  959. {
  960. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  961. struct spi_slave *spi = nor->spi;
  962. size_t actual;
  963. int ret;
  964. dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
  965. if (spi->mode & SPI_TX_BYTE)
  966. return sst_write_byteprogram(nor, to, len, retlen, buf);
  967. write_enable(nor);
  968. nor->sst_write_second = false;
  969. actual = to % 2;
  970. /* Start write from odd address. */
  971. if (actual) {
  972. nor->program_opcode = SPINOR_OP_BP;
  973. /* write one byte. */
  974. ret = nor->write(nor, to, 1, buf);
  975. if (ret < 0)
  976. goto sst_write_err;
  977. ret = spi_nor_wait_till_ready(nor);
  978. if (ret)
  979. goto sst_write_err;
  980. }
  981. to += actual;
  982. /* Write out most of the data here. */
  983. for (; actual < len - 1; actual += 2) {
  984. nor->program_opcode = SPINOR_OP_AAI_WP;
  985. /* write two bytes. */
  986. ret = nor->write(nor, to, 2, buf + actual);
  987. if (ret < 0)
  988. goto sst_write_err;
  989. ret = spi_nor_wait_till_ready(nor);
  990. if (ret)
  991. goto sst_write_err;
  992. to += 2;
  993. nor->sst_write_second = true;
  994. }
  995. nor->sst_write_second = false;
  996. write_disable(nor);
  997. ret = spi_nor_wait_till_ready(nor);
  998. if (ret)
  999. goto sst_write_err;
  1000. /* Write out trailing byte if it exists. */
  1001. if (actual != len) {
  1002. write_enable(nor);
  1003. nor->program_opcode = SPINOR_OP_BP;
  1004. ret = nor->write(nor, to, 1, buf + actual);
  1005. if (ret < 0)
  1006. goto sst_write_err;
  1007. ret = spi_nor_wait_till_ready(nor);
  1008. if (ret)
  1009. goto sst_write_err;
  1010. write_disable(nor);
  1011. actual += 1;
  1012. }
  1013. sst_write_err:
  1014. *retlen += actual;
  1015. return ret;
  1016. }
  1017. #endif
  1018. /*
  1019. * Write an address range to the nor chip. Data must be written in
  1020. * FLASH_PAGESIZE chunks. The address range may be any size provided
  1021. * it is within the physical boundaries.
  1022. */
  1023. static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
  1024. size_t *retlen, const u_char *buf)
  1025. {
  1026. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1027. size_t page_offset, page_remain, i;
  1028. ssize_t ret;
  1029. dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
  1030. if (!len)
  1031. return 0;
  1032. for (i = 0; i < len; ) {
  1033. ssize_t written;
  1034. loff_t addr = to + i;
  1035. /*
  1036. * If page_size is a power of two, the offset can be quickly
  1037. * calculated with an AND operation. On the other cases we
  1038. * need to do a modulus operation (more expensive).
  1039. */
  1040. if (is_power_of_2(nor->page_size)) {
  1041. page_offset = addr & (nor->page_size - 1);
  1042. } else {
  1043. u64 aux = addr;
  1044. page_offset = do_div(aux, nor->page_size);
  1045. }
  1046. /* the size of data remaining on the first page */
  1047. page_remain = min_t(size_t,
  1048. nor->page_size - page_offset, len - i);
  1049. #ifdef CONFIG_SPI_FLASH_BAR
  1050. ret = write_bar(nor, addr);
  1051. if (ret < 0)
  1052. return ret;
  1053. #endif
  1054. write_enable(nor);
  1055. ret = nor->write(nor, addr, page_remain, buf + i);
  1056. if (ret < 0)
  1057. goto write_err;
  1058. written = ret;
  1059. ret = spi_nor_wait_till_ready(nor);
  1060. if (ret)
  1061. goto write_err;
  1062. *retlen += written;
  1063. i += written;
  1064. }
  1065. write_err:
  1066. #ifdef CONFIG_SPI_FLASH_BAR
  1067. ret = clean_bar(nor);
  1068. #endif
  1069. return ret;
  1070. }
  1071. #ifdef CONFIG_SPI_FLASH_MACRONIX
  1072. /**
  1073. * macronix_quad_enable() - set QE bit in Status Register.
  1074. * @nor: pointer to a 'struct spi_nor'
  1075. *
  1076. * Set the Quad Enable (QE) bit in the Status Register.
  1077. *
  1078. * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
  1079. *
  1080. * Return: 0 on success, -errno otherwise.
  1081. */
  1082. static int macronix_quad_enable(struct spi_nor *nor)
  1083. {
  1084. int ret, val;
  1085. val = read_sr(nor);
  1086. if (val < 0)
  1087. return val;
  1088. if (val & SR_QUAD_EN_MX)
  1089. return 0;
  1090. write_enable(nor);
  1091. write_sr(nor, val | SR_QUAD_EN_MX);
  1092. ret = spi_nor_wait_till_ready(nor);
  1093. if (ret)
  1094. return ret;
  1095. ret = read_sr(nor);
  1096. if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
  1097. dev_err(nor->dev, "Macronix Quad bit not set\n");
  1098. return -EINVAL;
  1099. }
  1100. return 0;
  1101. }
  1102. #endif
  1103. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1104. /*
  1105. * Write status Register and configuration register with 2 bytes
  1106. * The first byte will be written to the status register, while the
  1107. * second byte will be written to the configuration register.
  1108. * Return negative if error occurred.
  1109. */
  1110. static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
  1111. {
  1112. int ret;
  1113. write_enable(nor);
  1114. ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
  1115. if (ret < 0) {
  1116. dev_dbg(nor->dev,
  1117. "error while writing configuration register\n");
  1118. return -EINVAL;
  1119. }
  1120. ret = spi_nor_wait_till_ready(nor);
  1121. if (ret) {
  1122. dev_dbg(nor->dev,
  1123. "timeout while writing configuration register\n");
  1124. return ret;
  1125. }
  1126. return 0;
  1127. }
  1128. /**
  1129. * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
  1130. * @nor: pointer to a 'struct spi_nor'
  1131. *
  1132. * Set the Quad Enable (QE) bit in the Configuration Register.
  1133. * This function should be used with QSPI memories supporting the Read
  1134. * Configuration Register (35h) instruction.
  1135. *
  1136. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  1137. * memories.
  1138. *
  1139. * Return: 0 on success, -errno otherwise.
  1140. */
  1141. static int spansion_read_cr_quad_enable(struct spi_nor *nor)
  1142. {
  1143. u8 sr_cr[2];
  1144. int ret;
  1145. /* Check current Quad Enable bit value. */
  1146. ret = read_cr(nor);
  1147. if (ret < 0) {
  1148. dev_dbg(nor->dev,
  1149. "error while reading configuration register\n");
  1150. return -EINVAL;
  1151. }
  1152. if (ret & CR_QUAD_EN_SPAN)
  1153. return 0;
  1154. sr_cr[1] = ret | CR_QUAD_EN_SPAN;
  1155. /* Keep the current value of the Status Register. */
  1156. ret = read_sr(nor);
  1157. if (ret < 0) {
  1158. dev_dbg(nor->dev, "error while reading status register\n");
  1159. return -EINVAL;
  1160. }
  1161. sr_cr[0] = ret;
  1162. ret = write_sr_cr(nor, sr_cr);
  1163. if (ret)
  1164. return ret;
  1165. /* Read back and check it. */
  1166. ret = read_cr(nor);
  1167. if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
  1168. dev_dbg(nor->dev, "Spansion Quad bit not set\n");
  1169. return -EINVAL;
  1170. }
  1171. return 0;
  1172. }
  1173. #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
  1174. /**
  1175. * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
  1176. * @nor: pointer to a 'struct spi_nor'
  1177. *
  1178. * Set the Quad Enable (QE) bit in the Configuration Register.
  1179. * This function should be used with QSPI memories not supporting the Read
  1180. * Configuration Register (35h) instruction.
  1181. *
  1182. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  1183. * memories.
  1184. *
  1185. * Return: 0 on success, -errno otherwise.
  1186. */
  1187. static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
  1188. {
  1189. u8 sr_cr[2];
  1190. int ret;
  1191. /* Keep the current value of the Status Register. */
  1192. ret = read_sr(nor);
  1193. if (ret < 0) {
  1194. dev_dbg(nor->dev, "error while reading status register\n");
  1195. return -EINVAL;
  1196. }
  1197. sr_cr[0] = ret;
  1198. sr_cr[1] = CR_QUAD_EN_SPAN;
  1199. return write_sr_cr(nor, sr_cr);
  1200. }
  1201. #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
  1202. #endif /* CONFIG_SPI_FLASH_SPANSION */
  1203. struct spi_nor_read_command {
  1204. u8 num_mode_clocks;
  1205. u8 num_wait_states;
  1206. u8 opcode;
  1207. enum spi_nor_protocol proto;
  1208. };
  1209. struct spi_nor_pp_command {
  1210. u8 opcode;
  1211. enum spi_nor_protocol proto;
  1212. };
  1213. enum spi_nor_read_command_index {
  1214. SNOR_CMD_READ,
  1215. SNOR_CMD_READ_FAST,
  1216. SNOR_CMD_READ_1_1_1_DTR,
  1217. /* Dual SPI */
  1218. SNOR_CMD_READ_1_1_2,
  1219. SNOR_CMD_READ_1_2_2,
  1220. SNOR_CMD_READ_2_2_2,
  1221. SNOR_CMD_READ_1_2_2_DTR,
  1222. /* Quad SPI */
  1223. SNOR_CMD_READ_1_1_4,
  1224. SNOR_CMD_READ_1_4_4,
  1225. SNOR_CMD_READ_4_4_4,
  1226. SNOR_CMD_READ_1_4_4_DTR,
  1227. /* Octo SPI */
  1228. SNOR_CMD_READ_1_1_8,
  1229. SNOR_CMD_READ_1_8_8,
  1230. SNOR_CMD_READ_8_8_8,
  1231. SNOR_CMD_READ_1_8_8_DTR,
  1232. SNOR_CMD_READ_MAX
  1233. };
  1234. enum spi_nor_pp_command_index {
  1235. SNOR_CMD_PP,
  1236. /* Quad SPI */
  1237. SNOR_CMD_PP_1_1_4,
  1238. SNOR_CMD_PP_1_4_4,
  1239. SNOR_CMD_PP_4_4_4,
  1240. /* Octo SPI */
  1241. SNOR_CMD_PP_1_1_8,
  1242. SNOR_CMD_PP_1_8_8,
  1243. SNOR_CMD_PP_8_8_8,
  1244. SNOR_CMD_PP_MAX
  1245. };
  1246. struct spi_nor_flash_parameter {
  1247. u64 size;
  1248. u32 page_size;
  1249. struct spi_nor_hwcaps hwcaps;
  1250. struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
  1251. struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
  1252. int (*quad_enable)(struct spi_nor *nor);
  1253. };
  1254. static void
  1255. spi_nor_set_read_settings(struct spi_nor_read_command *read,
  1256. u8 num_mode_clocks,
  1257. u8 num_wait_states,
  1258. u8 opcode,
  1259. enum spi_nor_protocol proto)
  1260. {
  1261. read->num_mode_clocks = num_mode_clocks;
  1262. read->num_wait_states = num_wait_states;
  1263. read->opcode = opcode;
  1264. read->proto = proto;
  1265. }
  1266. static void
  1267. spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
  1268. u8 opcode,
  1269. enum spi_nor_protocol proto)
  1270. {
  1271. pp->opcode = opcode;
  1272. pp->proto = proto;
  1273. }
  1274. #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
  1275. /*
  1276. * Serial Flash Discoverable Parameters (SFDP) parsing.
  1277. */
  1278. /**
  1279. * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
  1280. * @nor: pointer to a 'struct spi_nor'
  1281. * @addr: offset in the SFDP area to start reading data from
  1282. * @len: number of bytes to read
  1283. * @buf: buffer where the SFDP data are copied into (dma-safe memory)
  1284. *
  1285. * Whatever the actual numbers of bytes for address and dummy cycles are
  1286. * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
  1287. * followed by a 3-byte address and 8 dummy clock cycles.
  1288. *
  1289. * Return: 0 on success, -errno otherwise.
  1290. */
  1291. static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
  1292. size_t len, void *buf)
  1293. {
  1294. u8 addr_width, read_opcode, read_dummy;
  1295. int ret;
  1296. read_opcode = nor->read_opcode;
  1297. addr_width = nor->addr_width;
  1298. read_dummy = nor->read_dummy;
  1299. nor->read_opcode = SPINOR_OP_RDSFDP;
  1300. nor->addr_width = 3;
  1301. nor->read_dummy = 8;
  1302. while (len) {
  1303. ret = nor->read(nor, addr, len, (u8 *)buf);
  1304. if (!ret || ret > len) {
  1305. ret = -EIO;
  1306. goto read_err;
  1307. }
  1308. if (ret < 0)
  1309. goto read_err;
  1310. buf += ret;
  1311. addr += ret;
  1312. len -= ret;
  1313. }
  1314. ret = 0;
  1315. read_err:
  1316. nor->read_opcode = read_opcode;
  1317. nor->addr_width = addr_width;
  1318. nor->read_dummy = read_dummy;
  1319. return ret;
  1320. }
  1321. struct sfdp_parameter_header {
  1322. u8 id_lsb;
  1323. u8 minor;
  1324. u8 major;
  1325. u8 length; /* in double words */
  1326. u8 parameter_table_pointer[3]; /* byte address */
  1327. u8 id_msb;
  1328. };
  1329. #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
  1330. #define SFDP_PARAM_HEADER_PTP(p) \
  1331. (((p)->parameter_table_pointer[2] << 16) | \
  1332. ((p)->parameter_table_pointer[1] << 8) | \
  1333. ((p)->parameter_table_pointer[0] << 0))
  1334. #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
  1335. #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
  1336. #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
  1337. #define SFDP_SIGNATURE 0x50444653U
  1338. #define SFDP_JESD216_MAJOR 1
  1339. #define SFDP_JESD216_MINOR 0
  1340. #define SFDP_JESD216A_MINOR 5
  1341. #define SFDP_JESD216B_MINOR 6
  1342. struct sfdp_header {
  1343. u32 signature; /* Ox50444653U <=> "SFDP" */
  1344. u8 minor;
  1345. u8 major;
  1346. u8 nph; /* 0-base number of parameter headers */
  1347. u8 unused;
  1348. /* Basic Flash Parameter Table. */
  1349. struct sfdp_parameter_header bfpt_header;
  1350. };
  1351. /* Basic Flash Parameter Table */
  1352. /*
  1353. * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
  1354. * They are indexed from 1 but C arrays are indexed from 0.
  1355. */
  1356. #define BFPT_DWORD(i) ((i) - 1)
  1357. #define BFPT_DWORD_MAX 16
  1358. /* The first version of JESB216 defined only 9 DWORDs. */
  1359. #define BFPT_DWORD_MAX_JESD216 9
  1360. /* 1st DWORD. */
  1361. #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
  1362. #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
  1363. #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
  1364. #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
  1365. #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
  1366. #define BFPT_DWORD1_DTR BIT(19)
  1367. #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
  1368. #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
  1369. #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
  1370. /* 5th DWORD. */
  1371. #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
  1372. #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
  1373. /* 11th DWORD. */
  1374. #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
  1375. #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
  1376. /* 15th DWORD. */
  1377. /*
  1378. * (from JESD216 rev B)
  1379. * Quad Enable Requirements (QER):
  1380. * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
  1381. * reads based on instruction. DQ3/HOLD# functions are hold during
  1382. * instruction phase.
  1383. * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
  1384. * two data bytes where bit 1 of the second byte is one.
  1385. * [...]
  1386. * Writing only one byte to the status register has the side-effect of
  1387. * clearing status register 2, including the QE bit. The 100b code is
  1388. * used if writing one byte to the status register does not modify
  1389. * status register 2.
  1390. * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
  1391. * one data byte where bit 6 is one.
  1392. * [...]
  1393. * - 011b: QE is bit 7 of status register 2. It is set via Write status
  1394. * register 2 instruction 3Eh with one data byte where bit 7 is one.
  1395. * [...]
  1396. * The status register 2 is read using instruction 3Fh.
  1397. * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
  1398. * two data bytes where bit 1 of the second byte is one.
  1399. * [...]
  1400. * In contrast to the 001b code, writing one byte to the status
  1401. * register does not modify status register 2.
  1402. * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
  1403. * Read Status instruction 05h. Status register2 is read using
  1404. * instruction 35h. QE is set via Writ Status instruction 01h with
  1405. * two data bytes where bit 1 of the second byte is one.
  1406. * [...]
  1407. */
  1408. #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
  1409. #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
  1410. #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
  1411. #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
  1412. #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
  1413. #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
  1414. #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
  1415. struct sfdp_bfpt {
  1416. u32 dwords[BFPT_DWORD_MAX];
  1417. };
  1418. /* Fast Read settings. */
  1419. static void
  1420. spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
  1421. u16 half,
  1422. enum spi_nor_protocol proto)
  1423. {
  1424. read->num_mode_clocks = (half >> 5) & 0x07;
  1425. read->num_wait_states = (half >> 0) & 0x1f;
  1426. read->opcode = (half >> 8) & 0xff;
  1427. read->proto = proto;
  1428. }
  1429. struct sfdp_bfpt_read {
  1430. /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
  1431. u32 hwcaps;
  1432. /*
  1433. * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
  1434. * whether the Fast Read x-y-z command is supported.
  1435. */
  1436. u32 supported_dword;
  1437. u32 supported_bit;
  1438. /*
  1439. * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
  1440. * encodes the op code, the number of mode clocks and the number of wait
  1441. * states to be used by Fast Read x-y-z command.
  1442. */
  1443. u32 settings_dword;
  1444. u32 settings_shift;
  1445. /* The SPI protocol for this Fast Read x-y-z command. */
  1446. enum spi_nor_protocol proto;
  1447. };
  1448. static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
  1449. /* Fast Read 1-1-2 */
  1450. {
  1451. SNOR_HWCAPS_READ_1_1_2,
  1452. BFPT_DWORD(1), BIT(16), /* Supported bit */
  1453. BFPT_DWORD(4), 0, /* Settings */
  1454. SNOR_PROTO_1_1_2,
  1455. },
  1456. /* Fast Read 1-2-2 */
  1457. {
  1458. SNOR_HWCAPS_READ_1_2_2,
  1459. BFPT_DWORD(1), BIT(20), /* Supported bit */
  1460. BFPT_DWORD(4), 16, /* Settings */
  1461. SNOR_PROTO_1_2_2,
  1462. },
  1463. /* Fast Read 2-2-2 */
  1464. {
  1465. SNOR_HWCAPS_READ_2_2_2,
  1466. BFPT_DWORD(5), BIT(0), /* Supported bit */
  1467. BFPT_DWORD(6), 16, /* Settings */
  1468. SNOR_PROTO_2_2_2,
  1469. },
  1470. /* Fast Read 1-1-4 */
  1471. {
  1472. SNOR_HWCAPS_READ_1_1_4,
  1473. BFPT_DWORD(1), BIT(22), /* Supported bit */
  1474. BFPT_DWORD(3), 16, /* Settings */
  1475. SNOR_PROTO_1_1_4,
  1476. },
  1477. /* Fast Read 1-4-4 */
  1478. {
  1479. SNOR_HWCAPS_READ_1_4_4,
  1480. BFPT_DWORD(1), BIT(21), /* Supported bit */
  1481. BFPT_DWORD(3), 0, /* Settings */
  1482. SNOR_PROTO_1_4_4,
  1483. },
  1484. /* Fast Read 4-4-4 */
  1485. {
  1486. SNOR_HWCAPS_READ_4_4_4,
  1487. BFPT_DWORD(5), BIT(4), /* Supported bit */
  1488. BFPT_DWORD(7), 16, /* Settings */
  1489. SNOR_PROTO_4_4_4,
  1490. },
  1491. };
  1492. struct sfdp_bfpt_erase {
  1493. /*
  1494. * The half-word at offset <shift> in DWORD <dwoard> encodes the
  1495. * op code and erase sector size to be used by Sector Erase commands.
  1496. */
  1497. u32 dword;
  1498. u32 shift;
  1499. };
  1500. static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
  1501. /* Erase Type 1 in DWORD8 bits[15:0] */
  1502. {BFPT_DWORD(8), 0},
  1503. /* Erase Type 2 in DWORD8 bits[31:16] */
  1504. {BFPT_DWORD(8), 16},
  1505. /* Erase Type 3 in DWORD9 bits[15:0] */
  1506. {BFPT_DWORD(9), 0},
  1507. /* Erase Type 4 in DWORD9 bits[31:16] */
  1508. {BFPT_DWORD(9), 16},
  1509. };
  1510. static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
  1511. /**
  1512. * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
  1513. * @nor: pointer to a 'struct spi_nor'
  1514. * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
  1515. * the Basic Flash Parameter Table length and version
  1516. * @params: pointer to the 'struct spi_nor_flash_parameter' to be
  1517. * filled
  1518. *
  1519. * The Basic Flash Parameter Table is the main and only mandatory table as
  1520. * defined by the SFDP (JESD216) specification.
  1521. * It provides us with the total size (memory density) of the data array and
  1522. * the number of address bytes for Fast Read, Page Program and Sector Erase
  1523. * commands.
  1524. * For Fast READ commands, it also gives the number of mode clock cycles and
  1525. * wait states (regrouped in the number of dummy clock cycles) for each
  1526. * supported instruction op code.
  1527. * For Page Program, the page size is now available since JESD216 rev A, however
  1528. * the supported instruction op codes are still not provided.
  1529. * For Sector Erase commands, this table stores the supported instruction op
  1530. * codes and the associated sector sizes.
  1531. * Finally, the Quad Enable Requirements (QER) are also available since JESD216
  1532. * rev A. The QER bits encode the manufacturer dependent procedure to be
  1533. * executed to set the Quad Enable (QE) bit in some internal register of the
  1534. * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
  1535. * sending any Quad SPI command to the memory. Actually, setting the QE bit
  1536. * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
  1537. * and IO3 hence enabling 4 (Quad) I/O lines.
  1538. *
  1539. * Return: 0 on success, -errno otherwise.
  1540. */
  1541. static int spi_nor_parse_bfpt(struct spi_nor *nor,
  1542. const struct sfdp_parameter_header *bfpt_header,
  1543. struct spi_nor_flash_parameter *params)
  1544. {
  1545. struct mtd_info *mtd = &nor->mtd;
  1546. struct sfdp_bfpt bfpt;
  1547. size_t len;
  1548. int i, cmd, err;
  1549. u32 addr;
  1550. u16 half;
  1551. /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
  1552. if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
  1553. return -EINVAL;
  1554. /* Read the Basic Flash Parameter Table. */
  1555. len = min_t(size_t, sizeof(bfpt),
  1556. bfpt_header->length * sizeof(u32));
  1557. addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
  1558. memset(&bfpt, 0, sizeof(bfpt));
  1559. err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
  1560. if (err < 0)
  1561. return err;
  1562. /* Fix endianness of the BFPT DWORDs. */
  1563. for (i = 0; i < BFPT_DWORD_MAX; i++)
  1564. bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
  1565. /* Number of address bytes. */
  1566. switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
  1567. case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
  1568. nor->addr_width = 3;
  1569. break;
  1570. case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
  1571. nor->addr_width = 4;
  1572. break;
  1573. default:
  1574. break;
  1575. }
  1576. /* Flash Memory Density (in bits). */
  1577. params->size = bfpt.dwords[BFPT_DWORD(2)];
  1578. if (params->size & BIT(31)) {
  1579. params->size &= ~BIT(31);
  1580. /*
  1581. * Prevent overflows on params->size. Anyway, a NOR of 2^64
  1582. * bits is unlikely to exist so this error probably means
  1583. * the BFPT we are reading is corrupted/wrong.
  1584. */
  1585. if (params->size > 63)
  1586. return -EINVAL;
  1587. params->size = 1ULL << params->size;
  1588. } else {
  1589. params->size++;
  1590. }
  1591. params->size >>= 3; /* Convert to bytes. */
  1592. /* Fast Read settings. */
  1593. for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
  1594. const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
  1595. struct spi_nor_read_command *read;
  1596. if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
  1597. params->hwcaps.mask &= ~rd->hwcaps;
  1598. continue;
  1599. }
  1600. params->hwcaps.mask |= rd->hwcaps;
  1601. cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
  1602. read = &params->reads[cmd];
  1603. half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
  1604. spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
  1605. }
  1606. /* Sector Erase settings. */
  1607. for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
  1608. const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
  1609. u32 erasesize;
  1610. u8 opcode;
  1611. half = bfpt.dwords[er->dword] >> er->shift;
  1612. erasesize = half & 0xff;
  1613. /* erasesize == 0 means this Erase Type is not supported. */
  1614. if (!erasesize)
  1615. continue;
  1616. erasesize = 1U << erasesize;
  1617. opcode = (half >> 8) & 0xff;
  1618. #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  1619. if (erasesize == SZ_4K) {
  1620. nor->erase_opcode = opcode;
  1621. mtd->erasesize = erasesize;
  1622. break;
  1623. }
  1624. #endif
  1625. if (!mtd->erasesize || mtd->erasesize < erasesize) {
  1626. nor->erase_opcode = opcode;
  1627. mtd->erasesize = erasesize;
  1628. }
  1629. }
  1630. /* Stop here if not JESD216 rev A or later. */
  1631. if (bfpt_header->length < BFPT_DWORD_MAX)
  1632. return 0;
  1633. /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
  1634. params->page_size = bfpt.dwords[BFPT_DWORD(11)];
  1635. params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
  1636. params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
  1637. params->page_size = 1U << params->page_size;
  1638. /* Quad Enable Requirements. */
  1639. switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
  1640. case BFPT_DWORD15_QER_NONE:
  1641. params->quad_enable = NULL;
  1642. break;
  1643. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1644. case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
  1645. case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
  1646. params->quad_enable = spansion_no_read_cr_quad_enable;
  1647. break;
  1648. #endif
  1649. #ifdef CONFIG_SPI_FLASH_MACRONIX
  1650. case BFPT_DWORD15_QER_SR1_BIT6:
  1651. params->quad_enable = macronix_quad_enable;
  1652. break;
  1653. #endif
  1654. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1655. case BFPT_DWORD15_QER_SR2_BIT1:
  1656. params->quad_enable = spansion_read_cr_quad_enable;
  1657. break;
  1658. #endif
  1659. default:
  1660. return -EINVAL;
  1661. }
  1662. return 0;
  1663. }
  1664. /**
  1665. * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
  1666. * SFDP table.
  1667. * @nor: pointer to a 'struct spi_nor'.
  1668. * @param_header: pointer to the SFDP parameter header.
  1669. *
  1670. * Return: 0 on success, -errno otherwise.
  1671. */
  1672. static int
  1673. spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
  1674. const struct sfdp_parameter_header *param_header)
  1675. {
  1676. size_t size;
  1677. u32 addr;
  1678. int ret;
  1679. size = param_header->length * sizeof(u32);
  1680. addr = SFDP_PARAM_HEADER_PTP(param_header);
  1681. nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
  1682. if (!nor->manufacturer_sfdp)
  1683. return -ENOMEM;
  1684. ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
  1685. return ret;
  1686. }
  1687. /**
  1688. * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
  1689. * @nor: pointer to a 'struct spi_nor'
  1690. * @params: pointer to the 'struct spi_nor_flash_parameter' to be
  1691. * filled
  1692. *
  1693. * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
  1694. * specification. This is a standard which tends to supported by almost all
  1695. * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
  1696. * runtime the main parameters needed to perform basic SPI flash operations such
  1697. * as Fast Read, Page Program or Sector Erase commands.
  1698. *
  1699. * Return: 0 on success, -errno otherwise.
  1700. */
  1701. static int spi_nor_parse_sfdp(struct spi_nor *nor,
  1702. struct spi_nor_flash_parameter *params)
  1703. {
  1704. const struct sfdp_parameter_header *param_header, *bfpt_header;
  1705. struct sfdp_parameter_header *param_headers = NULL;
  1706. struct sfdp_header header;
  1707. size_t psize;
  1708. int i, err;
  1709. /* Get the SFDP header. */
  1710. err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
  1711. if (err < 0)
  1712. return err;
  1713. /* Check the SFDP header version. */
  1714. if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
  1715. header.major != SFDP_JESD216_MAJOR)
  1716. return -EINVAL;
  1717. /*
  1718. * Verify that the first and only mandatory parameter header is a
  1719. * Basic Flash Parameter Table header as specified in JESD216.
  1720. */
  1721. bfpt_header = &header.bfpt_header;
  1722. if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
  1723. bfpt_header->major != SFDP_JESD216_MAJOR)
  1724. return -EINVAL;
  1725. /*
  1726. * Allocate memory then read all parameter headers with a single
  1727. * Read SFDP command. These parameter headers will actually be parsed
  1728. * twice: a first time to get the latest revision of the basic flash
  1729. * parameter table, then a second time to handle the supported optional
  1730. * tables.
  1731. * Hence we read the parameter headers once for all to reduce the
  1732. * processing time. Also we use kmalloc() instead of devm_kmalloc()
  1733. * because we don't need to keep these parameter headers: the allocated
  1734. * memory is always released with kfree() before exiting this function.
  1735. */
  1736. if (header.nph) {
  1737. psize = header.nph * sizeof(*param_headers);
  1738. param_headers = kmalloc(psize, GFP_KERNEL);
  1739. if (!param_headers)
  1740. return -ENOMEM;
  1741. err = spi_nor_read_sfdp(nor, sizeof(header),
  1742. psize, param_headers);
  1743. if (err < 0) {
  1744. dev_err(nor->dev,
  1745. "failed to read SFDP parameter headers\n");
  1746. goto exit;
  1747. }
  1748. }
  1749. /*
  1750. * Check other parameter headers to get the latest revision of
  1751. * the basic flash parameter table.
  1752. */
  1753. for (i = 0; i < header.nph; i++) {
  1754. param_header = &param_headers[i];
  1755. if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
  1756. param_header->major == SFDP_JESD216_MAJOR &&
  1757. (param_header->minor > bfpt_header->minor ||
  1758. (param_header->minor == bfpt_header->minor &&
  1759. param_header->length > bfpt_header->length)))
  1760. bfpt_header = param_header;
  1761. }
  1762. err = spi_nor_parse_bfpt(nor, bfpt_header, params);
  1763. if (err)
  1764. goto exit;
  1765. /* Parse other parameter headers. */
  1766. for (i = 0; i < header.nph; i++) {
  1767. param_header = &param_headers[i];
  1768. switch (SFDP_PARAM_HEADER_ID(param_header)) {
  1769. case SFDP_SECTOR_MAP_ID:
  1770. dev_info(nor->dev,
  1771. "non-uniform erase sector maps are not supported yet.\n");
  1772. break;
  1773. case SFDP_SST_ID:
  1774. err = spi_nor_parse_microchip_sfdp(nor, param_header);
  1775. break;
  1776. default:
  1777. break;
  1778. }
  1779. if (err) {
  1780. dev_warn(nor->dev,
  1781. "Failed to parse optional parameter table: %04x\n",
  1782. SFDP_PARAM_HEADER_ID(param_header));
  1783. /*
  1784. * Let's not drop all information we extracted so far
  1785. * if optional table parsers fail. In case of failing,
  1786. * each optional parser is responsible to roll back to
  1787. * the previously known spi_nor data.
  1788. */
  1789. err = 0;
  1790. }
  1791. }
  1792. exit:
  1793. kfree(param_headers);
  1794. return err;
  1795. }
  1796. #else
  1797. static int spi_nor_parse_sfdp(struct spi_nor *nor,
  1798. struct spi_nor_flash_parameter *params)
  1799. {
  1800. return -EINVAL;
  1801. }
  1802. #endif /* SPI_FLASH_SFDP_SUPPORT */
  1803. static int spi_nor_init_params(struct spi_nor *nor,
  1804. const struct flash_info *info,
  1805. struct spi_nor_flash_parameter *params)
  1806. {
  1807. /* Set legacy flash parameters as default. */
  1808. memset(params, 0, sizeof(*params));
  1809. /* Set SPI NOR sizes. */
  1810. params->size = info->sector_size * info->n_sectors;
  1811. params->page_size = info->page_size;
  1812. /* (Fast) Read settings. */
  1813. params->hwcaps.mask |= SNOR_HWCAPS_READ;
  1814. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
  1815. 0, 0, SPINOR_OP_READ,
  1816. SNOR_PROTO_1_1_1);
  1817. if (!(info->flags & SPI_NOR_NO_FR)) {
  1818. params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
  1819. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
  1820. 0, 8, SPINOR_OP_READ_FAST,
  1821. SNOR_PROTO_1_1_1);
  1822. }
  1823. if (info->flags & SPI_NOR_DUAL_READ) {
  1824. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
  1825. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
  1826. 0, 8, SPINOR_OP_READ_1_1_2,
  1827. SNOR_PROTO_1_1_2);
  1828. }
  1829. if (info->flags & SPI_NOR_QUAD_READ) {
  1830. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  1831. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
  1832. 0, 8, SPINOR_OP_READ_1_1_4,
  1833. SNOR_PROTO_1_1_4);
  1834. }
  1835. if (info->flags & SPI_NOR_OCTAL_READ) {
  1836. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
  1837. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
  1838. 0, 8, SPINOR_OP_READ_1_1_8,
  1839. SNOR_PROTO_1_1_8);
  1840. }
  1841. /* Page Program settings. */
  1842. params->hwcaps.mask |= SNOR_HWCAPS_PP;
  1843. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
  1844. SPINOR_OP_PP, SNOR_PROTO_1_1_1);
  1845. if (info->flags & SPI_NOR_QUAD_READ) {
  1846. params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
  1847. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_1_4],
  1848. SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
  1849. }
  1850. /* Select the procedure to set the Quad Enable bit. */
  1851. if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
  1852. SNOR_HWCAPS_PP_QUAD)) {
  1853. switch (JEDEC_MFR(info)) {
  1854. #ifdef CONFIG_SPI_FLASH_MACRONIX
  1855. case SNOR_MFR_MACRONIX:
  1856. params->quad_enable = macronix_quad_enable;
  1857. break;
  1858. #endif
  1859. case SNOR_MFR_ST:
  1860. case SNOR_MFR_MICRON:
  1861. break;
  1862. default:
  1863. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1864. /* Kept only for backward compatibility purpose. */
  1865. params->quad_enable = spansion_read_cr_quad_enable;
  1866. #endif
  1867. break;
  1868. }
  1869. }
  1870. /* Override the parameters with data read from SFDP tables. */
  1871. nor->addr_width = 0;
  1872. nor->mtd.erasesize = 0;
  1873. if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
  1874. !(info->flags & SPI_NOR_SKIP_SFDP)) {
  1875. struct spi_nor_flash_parameter sfdp_params;
  1876. memcpy(&sfdp_params, params, sizeof(sfdp_params));
  1877. if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
  1878. nor->addr_width = 0;
  1879. nor->mtd.erasesize = 0;
  1880. } else {
  1881. memcpy(params, &sfdp_params, sizeof(*params));
  1882. }
  1883. }
  1884. return 0;
  1885. }
  1886. static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
  1887. {
  1888. size_t i;
  1889. for (i = 0; i < size; i++)
  1890. if (table[i][0] == (int)hwcaps)
  1891. return table[i][1];
  1892. return -EINVAL;
  1893. }
  1894. static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
  1895. {
  1896. static const int hwcaps_read2cmd[][2] = {
  1897. { SNOR_HWCAPS_READ, SNOR_CMD_READ },
  1898. { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
  1899. { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
  1900. { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
  1901. { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
  1902. { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
  1903. { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
  1904. { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
  1905. { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
  1906. { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
  1907. { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
  1908. { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
  1909. { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
  1910. { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
  1911. { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
  1912. };
  1913. return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
  1914. ARRAY_SIZE(hwcaps_read2cmd));
  1915. }
  1916. static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
  1917. {
  1918. static const int hwcaps_pp2cmd[][2] = {
  1919. { SNOR_HWCAPS_PP, SNOR_CMD_PP },
  1920. { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
  1921. { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
  1922. { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
  1923. { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
  1924. { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
  1925. { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
  1926. };
  1927. return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
  1928. ARRAY_SIZE(hwcaps_pp2cmd));
  1929. }
  1930. static int spi_nor_select_read(struct spi_nor *nor,
  1931. const struct spi_nor_flash_parameter *params,
  1932. u32 shared_hwcaps)
  1933. {
  1934. int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
  1935. const struct spi_nor_read_command *read;
  1936. if (best_match < 0)
  1937. return -EINVAL;
  1938. cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
  1939. if (cmd < 0)
  1940. return -EINVAL;
  1941. read = &params->reads[cmd];
  1942. nor->read_opcode = read->opcode;
  1943. nor->read_proto = read->proto;
  1944. /*
  1945. * In the spi-nor framework, we don't need to make the difference
  1946. * between mode clock cycles and wait state clock cycles.
  1947. * Indeed, the value of the mode clock cycles is used by a QSPI
  1948. * flash memory to know whether it should enter or leave its 0-4-4
  1949. * (Continuous Read / XIP) mode.
  1950. * eXecution In Place is out of the scope of the mtd sub-system.
  1951. * Hence we choose to merge both mode and wait state clock cycles
  1952. * into the so called dummy clock cycles.
  1953. */
  1954. nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
  1955. return 0;
  1956. }
  1957. static int spi_nor_select_pp(struct spi_nor *nor,
  1958. const struct spi_nor_flash_parameter *params,
  1959. u32 shared_hwcaps)
  1960. {
  1961. int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
  1962. const struct spi_nor_pp_command *pp;
  1963. if (best_match < 0)
  1964. return -EINVAL;
  1965. cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
  1966. if (cmd < 0)
  1967. return -EINVAL;
  1968. pp = &params->page_programs[cmd];
  1969. nor->program_opcode = pp->opcode;
  1970. nor->write_proto = pp->proto;
  1971. return 0;
  1972. }
  1973. static int spi_nor_select_erase(struct spi_nor *nor,
  1974. const struct flash_info *info)
  1975. {
  1976. struct mtd_info *mtd = &nor->mtd;
  1977. /* Do nothing if already configured from SFDP. */
  1978. if (mtd->erasesize)
  1979. return 0;
  1980. #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  1981. /* prefer "small sector" erase if possible */
  1982. if (info->flags & SECT_4K) {
  1983. nor->erase_opcode = SPINOR_OP_BE_4K;
  1984. mtd->erasesize = 4096;
  1985. } else if (info->flags & SECT_4K_PMC) {
  1986. nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
  1987. mtd->erasesize = 4096;
  1988. } else
  1989. #endif
  1990. {
  1991. nor->erase_opcode = SPINOR_OP_SE;
  1992. mtd->erasesize = info->sector_size;
  1993. }
  1994. return 0;
  1995. }
  1996. static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
  1997. const struct spi_nor_flash_parameter *params,
  1998. const struct spi_nor_hwcaps *hwcaps)
  1999. {
  2000. u32 ignored_mask, shared_mask;
  2001. bool enable_quad_io;
  2002. int err;
  2003. /*
  2004. * Keep only the hardware capabilities supported by both the SPI
  2005. * controller and the SPI flash memory.
  2006. */
  2007. shared_mask = hwcaps->mask & params->hwcaps.mask;
  2008. /* SPI n-n-n protocols are not supported yet. */
  2009. ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
  2010. SNOR_HWCAPS_READ_4_4_4 |
  2011. SNOR_HWCAPS_READ_8_8_8 |
  2012. SNOR_HWCAPS_PP_4_4_4 |
  2013. SNOR_HWCAPS_PP_8_8_8);
  2014. if (shared_mask & ignored_mask) {
  2015. dev_dbg(nor->dev,
  2016. "SPI n-n-n protocols are not supported yet.\n");
  2017. shared_mask &= ~ignored_mask;
  2018. }
  2019. /* Select the (Fast) Read command. */
  2020. err = spi_nor_select_read(nor, params, shared_mask);
  2021. if (err) {
  2022. dev_dbg(nor->dev,
  2023. "can't select read settings supported by both the SPI controller and memory.\n");
  2024. return err;
  2025. }
  2026. /* Select the Page Program command. */
  2027. err = spi_nor_select_pp(nor, params, shared_mask);
  2028. if (err) {
  2029. dev_dbg(nor->dev,
  2030. "can't select write settings supported by both the SPI controller and memory.\n");
  2031. return err;
  2032. }
  2033. /* Select the Sector Erase command. */
  2034. err = spi_nor_select_erase(nor, info);
  2035. if (err) {
  2036. dev_dbg(nor->dev,
  2037. "can't select erase settings supported by both the SPI controller and memory.\n");
  2038. return err;
  2039. }
  2040. /* Enable Quad I/O if needed. */
  2041. enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
  2042. spi_nor_get_protocol_width(nor->write_proto) == 4);
  2043. if (enable_quad_io && params->quad_enable)
  2044. nor->quad_enable = params->quad_enable;
  2045. else
  2046. nor->quad_enable = NULL;
  2047. return 0;
  2048. }
  2049. static int spi_nor_init(struct spi_nor *nor)
  2050. {
  2051. int err;
  2052. /*
  2053. * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
  2054. * with the software protection bits set
  2055. */
  2056. if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
  2057. JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
  2058. JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
  2059. nor->info->flags & SPI_NOR_HAS_LOCK) {
  2060. write_enable(nor);
  2061. write_sr(nor, 0);
  2062. spi_nor_wait_till_ready(nor);
  2063. }
  2064. if (nor->quad_enable) {
  2065. err = nor->quad_enable(nor);
  2066. if (err) {
  2067. dev_dbg(nor->dev, "quad mode not supported\n");
  2068. return err;
  2069. }
  2070. }
  2071. if (nor->addr_width == 4 &&
  2072. (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
  2073. !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
  2074. /*
  2075. * If the RESET# pin isn't hooked up properly, or the system
  2076. * otherwise doesn't perform a reset command in the boot
  2077. * sequence, it's impossible to 100% protect against unexpected
  2078. * reboots (e.g., crashes). Warn the user (or hopefully, system
  2079. * designer) that this is bad.
  2080. */
  2081. if (nor->flags & SNOR_F_BROKEN_RESET)
  2082. printf("enabling reset hack; may not recover from unexpected reboots\n");
  2083. set_4byte(nor, nor->info, 1);
  2084. }
  2085. return 0;
  2086. }
  2087. int spi_nor_scan(struct spi_nor *nor)
  2088. {
  2089. struct spi_nor_flash_parameter params;
  2090. const struct flash_info *info = NULL;
  2091. struct mtd_info *mtd = &nor->mtd;
  2092. struct spi_nor_hwcaps hwcaps = {
  2093. .mask = SNOR_HWCAPS_READ |
  2094. SNOR_HWCAPS_READ_FAST |
  2095. SNOR_HWCAPS_PP,
  2096. };
  2097. struct spi_slave *spi = nor->spi;
  2098. int ret;
  2099. /* Reset SPI protocol for all commands. */
  2100. nor->reg_proto = SNOR_PROTO_1_1_1;
  2101. nor->read_proto = SNOR_PROTO_1_1_1;
  2102. nor->write_proto = SNOR_PROTO_1_1_1;
  2103. nor->read = spi_nor_read_data;
  2104. nor->write = spi_nor_write_data;
  2105. nor->read_reg = spi_nor_read_reg;
  2106. nor->write_reg = spi_nor_write_reg;
  2107. if (spi->mode & SPI_RX_OCTAL) {
  2108. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
  2109. if (spi->mode & SPI_TX_OCTAL)
  2110. hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
  2111. SNOR_HWCAPS_PP_1_1_8 |
  2112. SNOR_HWCAPS_PP_1_8_8);
  2113. } else if (spi->mode & SPI_RX_QUAD) {
  2114. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  2115. if (spi->mode & SPI_TX_QUAD)
  2116. hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
  2117. SNOR_HWCAPS_PP_1_1_4 |
  2118. SNOR_HWCAPS_PP_1_4_4);
  2119. } else if (spi->mode & SPI_RX_DUAL) {
  2120. hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
  2121. if (spi->mode & SPI_TX_DUAL)
  2122. hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
  2123. }
  2124. info = spi_nor_read_id(nor);
  2125. if (IS_ERR_OR_NULL(info))
  2126. return -ENOENT;
  2127. /* Parse the Serial Flash Discoverable Parameters table. */
  2128. ret = spi_nor_init_params(nor, info, &params);
  2129. if (ret)
  2130. return ret;
  2131. if (!mtd->name)
  2132. mtd->name = info->name;
  2133. mtd->priv = nor;
  2134. mtd->type = MTD_NORFLASH;
  2135. mtd->writesize = 1;
  2136. mtd->flags = MTD_CAP_NORFLASH;
  2137. mtd->size = params.size;
  2138. mtd->_erase = spi_nor_erase;
  2139. mtd->_read = spi_nor_read;
  2140. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  2141. /* NOR protection support for STmicro/Micron chips and similar */
  2142. if (JEDEC_MFR(info) == SNOR_MFR_ST ||
  2143. JEDEC_MFR(info) == SNOR_MFR_MICRON ||
  2144. JEDEC_MFR(info) == SNOR_MFR_SST ||
  2145. info->flags & SPI_NOR_HAS_LOCK) {
  2146. nor->flash_lock = stm_lock;
  2147. nor->flash_unlock = stm_unlock;
  2148. nor->flash_is_locked = stm_is_locked;
  2149. }
  2150. #endif
  2151. #ifdef CONFIG_SPI_FLASH_SST
  2152. /*
  2153. * sst26 series block protection implementation differs from other
  2154. * series.
  2155. */
  2156. if (info->flags & SPI_NOR_HAS_SST26LOCK) {
  2157. nor->flash_lock = sst26_lock;
  2158. nor->flash_unlock = sst26_unlock;
  2159. nor->flash_is_locked = sst26_is_locked;
  2160. }
  2161. /* sst nor chips use AAI word program */
  2162. if (info->flags & SST_WRITE)
  2163. mtd->_write = sst_write;
  2164. else
  2165. #endif
  2166. mtd->_write = spi_nor_write;
  2167. if (info->flags & USE_FSR)
  2168. nor->flags |= SNOR_F_USE_FSR;
  2169. if (info->flags & SPI_NOR_HAS_TB)
  2170. nor->flags |= SNOR_F_HAS_SR_TB;
  2171. if (info->flags & NO_CHIP_ERASE)
  2172. nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
  2173. if (info->flags & USE_CLSR)
  2174. nor->flags |= SNOR_F_USE_CLSR;
  2175. if (info->flags & SPI_NOR_NO_ERASE)
  2176. mtd->flags |= MTD_NO_ERASE;
  2177. nor->page_size = params.page_size;
  2178. mtd->writebufsize = nor->page_size;
  2179. /* Some devices cannot do fast-read, no matter what DT tells us */
  2180. if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
  2181. params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
  2182. /*
  2183. * Configure the SPI memory:
  2184. * - select op codes for (Fast) Read, Page Program and Sector Erase.
  2185. * - set the number of dummy cycles (mode cycles + wait states).
  2186. * - set the SPI protocols for register and memory accesses.
  2187. * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
  2188. */
  2189. ret = spi_nor_setup(nor, info, &params, &hwcaps);
  2190. if (ret)
  2191. return ret;
  2192. if (nor->addr_width) {
  2193. /* already configured from SFDP */
  2194. } else if (info->addr_width) {
  2195. nor->addr_width = info->addr_width;
  2196. } else if (mtd->size > SZ_16M) {
  2197. #ifndef CONFIG_SPI_FLASH_BAR
  2198. /* enable 4-byte addressing if the device exceeds 16MiB */
  2199. nor->addr_width = 4;
  2200. if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
  2201. info->flags & SPI_NOR_4B_OPCODES)
  2202. spi_nor_set_4byte_opcodes(nor, info);
  2203. #else
  2204. /* Configure the BAR - discover bank cmds and read current bank */
  2205. nor->addr_width = 3;
  2206. ret = read_bar(nor, info);
  2207. if (ret < 0)
  2208. return ret;
  2209. #endif
  2210. } else {
  2211. nor->addr_width = 3;
  2212. }
  2213. if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
  2214. dev_dbg(nor->dev, "address width is too large: %u\n",
  2215. nor->addr_width);
  2216. return -EINVAL;
  2217. }
  2218. /* Send all the required SPI flash commands to initialize device */
  2219. nor->info = info;
  2220. ret = spi_nor_init(nor);
  2221. if (ret)
  2222. return ret;
  2223. nor->name = mtd->name;
  2224. nor->size = mtd->size;
  2225. nor->erase_size = mtd->erasesize;
  2226. nor->sector_size = mtd->erasesize;
  2227. #ifndef CONFIG_SPL_BUILD
  2228. printf("SF: Detected %s with page size ", nor->name);
  2229. print_size(nor->page_size, ", erase size ");
  2230. print_size(nor->erase_size, ", total ");
  2231. print_size(nor->size, "");
  2232. puts("\n");
  2233. #endif
  2234. return 0;
  2235. }
  2236. /* U-Boot specific functions, need to extend MTD to support these */
  2237. int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
  2238. {
  2239. int sr = read_sr(nor);
  2240. if (sr < 0)
  2241. return sr;
  2242. return (sr >> 2) & 7;
  2243. }