fsl_ifc_spl.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NAND boot for Freescale Integrated Flash Controller, NAND FCM
  4. *
  5. * Copyright 2011 Freescale Semiconductor, Inc.
  6. * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <asm/io.h>
  11. #include <fsl_ifc.h>
  12. #include <part.h>
  13. #include <linux/mtd/rawnand.h>
  14. #ifdef CONFIG_CHAIN_OF_TRUST
  15. #include <fsl_validate.h>
  16. #endif
  17. static inline int is_blank(uchar *addr, int page_size)
  18. {
  19. int i;
  20. for (i = 0; i < page_size; i++) {
  21. if (__raw_readb(&addr[i]) != 0xff)
  22. return 0;
  23. }
  24. /*
  25. * For the SPL, don't worry about uncorrectable errors
  26. * where the main area is all FFs but shouldn't be.
  27. */
  28. return 1;
  29. }
  30. /* returns nonzero if entire page is blank */
  31. static inline int check_read_ecc(uchar *buf, u32 *eccstat,
  32. unsigned int bufnum, int page_size)
  33. {
  34. u32 reg = eccstat[bufnum / 4];
  35. int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
  36. if (errors == 0xf) { /* uncorrectable */
  37. /* Blank pages fail hw ECC checks */
  38. if (is_blank(buf, page_size))
  39. return 1;
  40. puts("ecc error\n");
  41. for (;;)
  42. ;
  43. }
  44. return 0;
  45. }
  46. static inline struct fsl_ifc_runtime *runtime_regs_address(void)
  47. {
  48. struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
  49. int ver = 0;
  50. ver = ifc_in32(&regs.gregs->ifc_rev);
  51. if (ver >= FSL_IFC_V2_0_0)
  52. regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
  53. else
  54. regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
  55. return regs.rregs;
  56. }
  57. static inline void nand_wait(uchar *buf, int bufnum, int page_size)
  58. {
  59. struct fsl_ifc_runtime *ifc = runtime_regs_address();
  60. u32 status;
  61. u32 eccstat[8];
  62. int bufperpage = page_size / 512;
  63. int bufnum_end, i;
  64. bufnum *= bufperpage;
  65. bufnum_end = bufnum + bufperpage - 1;
  66. do {
  67. status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  68. } while (!(status & IFC_NAND_EVTER_STAT_OPC));
  69. if (status & IFC_NAND_EVTER_STAT_FTOER) {
  70. puts("flash time out error\n");
  71. for (;;)
  72. ;
  73. }
  74. for (i = bufnum / 4; i <= bufnum_end / 4; i++)
  75. eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
  76. for (i = bufnum; i <= bufnum_end; i++) {
  77. if (check_read_ecc(buf, eccstat, i, page_size))
  78. break;
  79. }
  80. ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
  81. }
  82. static inline int bad_block(uchar *marker, int port_size)
  83. {
  84. if (port_size == 8)
  85. return __raw_readb(marker) != 0xff;
  86. else
  87. return __raw_readw((u16 *)marker) != 0xffff;
  88. }
  89. int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
  90. {
  91. struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
  92. struct fsl_ifc_runtime *ifc = NULL;
  93. uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
  94. int page_size;
  95. int port_size;
  96. int pages_per_blk;
  97. int blk_size;
  98. int bad_marker = 0;
  99. int bufnum_mask, bufnum, ver = 0;
  100. int csor, cspr;
  101. int pos = 0;
  102. int j = 0;
  103. int sram_addr;
  104. int pg_no;
  105. uchar *dst = vdst;
  106. ifc = runtime_regs_address();
  107. /* Get NAND Flash configuration */
  108. csor = CONFIG_SYS_NAND_CSOR;
  109. cspr = CONFIG_SYS_NAND_CSPR;
  110. port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
  111. if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
  112. page_size = 8192;
  113. bufnum_mask = 0x0;
  114. } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
  115. page_size = 4096;
  116. bufnum_mask = 0x1;
  117. } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
  118. page_size = 2048;
  119. bufnum_mask = 0x3;
  120. } else {
  121. page_size = 512;
  122. bufnum_mask = 0xf;
  123. if (port_size == 8)
  124. bad_marker = 5;
  125. }
  126. ver = ifc_in32(&gregs->ifc_rev);
  127. if (ver >= FSL_IFC_V2_0_0)
  128. bufnum_mask = (bufnum_mask * 2) + 1;
  129. pages_per_blk =
  130. 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
  131. blk_size = pages_per_blk * page_size;
  132. /* Open Full SRAM mapping for spare are access */
  133. ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
  134. /* Clear Boot events */
  135. ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
  136. /* Program FIR/FCR for Large/Small page */
  137. if (page_size > 512) {
  138. ifc_out32(&ifc->ifc_nand.nand_fir0,
  139. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  140. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  141. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  142. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
  143. (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
  144. ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  145. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  146. (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
  147. (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
  148. } else {
  149. ifc_out32(&ifc->ifc_nand.nand_fir0,
  150. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  151. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  152. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  153. (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
  154. ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  155. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  156. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
  157. }
  158. /* Program FBCR = 0 for full page read */
  159. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  160. /* Read and copy u-boot on SDRAM from NAND device, In parallel
  161. * check for Bad block if found skip it and read continue to
  162. * next Block
  163. */
  164. while (pos < uboot_size) {
  165. int i = 0;
  166. do {
  167. pg_no = offs / page_size;
  168. bufnum = pg_no & bufnum_mask;
  169. sram_addr = bufnum * page_size * 2;
  170. ifc_out32(&ifc->ifc_nand.row0, pg_no);
  171. ifc_out32(&ifc->ifc_nand.col0, 0);
  172. /* start read */
  173. ifc_out32(&ifc->ifc_nand.nandseq_strt,
  174. IFC_NAND_SEQ_STRT_FIR_STRT);
  175. /* wait for read to complete */
  176. nand_wait(&buf[sram_addr], bufnum, page_size);
  177. /*
  178. * If either of the first two pages are marked bad,
  179. * continue to the next block.
  180. */
  181. if (i++ < 2 &&
  182. bad_block(&buf[sram_addr + page_size + bad_marker],
  183. port_size)) {
  184. puts("skipping\n");
  185. offs = (offs + blk_size) & ~(blk_size - 1);
  186. pos &= ~(blk_size - 1);
  187. break;
  188. }
  189. for (j = 0; j < page_size; j++)
  190. dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
  191. pos += page_size;
  192. offs += page_size;
  193. } while ((offs & (blk_size - 1)) && (pos < uboot_size));
  194. }
  195. return 0;
  196. }
  197. /*
  198. * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
  199. * configured and available since this code loads the main U-Boot image
  200. * from NAND into SDRAM and starts from there.
  201. */
  202. void nand_boot(void)
  203. {
  204. __attribute__((noreturn)) void (*uboot)(void);
  205. /*
  206. * Load U-Boot image from NAND into RAM
  207. */
  208. nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
  209. CONFIG_SYS_NAND_U_BOOT_SIZE,
  210. (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
  211. #ifdef CONFIG_NAND_ENV_DST
  212. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  213. (uchar *)CONFIG_NAND_ENV_DST);
  214. #ifdef CONFIG_ENV_OFFSET_REDUND
  215. nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
  216. (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
  217. #endif
  218. #endif
  219. /*
  220. * Jump to U-Boot image
  221. */
  222. #ifdef CONFIG_SPL_FLUSH_IMAGE
  223. /*
  224. * Clean d-cache and invalidate i-cache, to
  225. * make sure that no stale data is executed.
  226. */
  227. flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
  228. #endif
  229. #ifdef CONFIG_CHAIN_OF_TRUST
  230. /*
  231. * U-Boot header is appended at end of U-boot image, so
  232. * calculate U-boot header address using U-boot header size.
  233. */
  234. #define CONFIG_U_BOOT_HDR_ADDR \
  235. ((CONFIG_SYS_NAND_U_BOOT_START + \
  236. CONFIG_SYS_NAND_U_BOOT_SIZE) - \
  237. CONFIG_U_BOOT_HDR_SIZE)
  238. spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
  239. CONFIG_SYS_NAND_U_BOOT_START);
  240. /*
  241. * In case of failure in validation, spl_validate_uboot would
  242. * not return back in case of Production environment with ITS=1.
  243. * Thus U-Boot will not start.
  244. * In Development environment (ITS=0 and SB_EN=1), the function
  245. * may return back in case of non-fatal failures.
  246. */
  247. #endif
  248. uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
  249. uboot();
  250. }
  251. #ifndef CONFIG_SPL_NAND_INIT
  252. void nand_init(void)
  253. {
  254. }
  255. void nand_deselect(void)
  256. {
  257. }
  258. #endif