altera_qspi.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
  4. */
  5. #include <common.h>
  6. #include <console.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <fdt_support.h>
  10. #include <flash.h>
  11. #include <mtd.h>
  12. #include <asm/io.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. /* The STATUS register */
  15. #define QUADSPI_SR_BP0 BIT(2)
  16. #define QUADSPI_SR_BP1 BIT(3)
  17. #define QUADSPI_SR_BP2 BIT(4)
  18. #define QUADSPI_SR_BP2_0 GENMASK(4, 2)
  19. #define QUADSPI_SR_BP3 BIT(6)
  20. #define QUADSPI_SR_TB BIT(5)
  21. /*
  22. * The QUADSPI_MEM_OP register is used to do memory protect and erase operations
  23. */
  24. #define QUADSPI_MEM_OP_BULK_ERASE 0x00000001
  25. #define QUADSPI_MEM_OP_SECTOR_ERASE 0x00000002
  26. #define QUADSPI_MEM_OP_SECTOR_PROTECT 0x00000003
  27. /*
  28. * The QUADSPI_ISR register is used to determine whether an invalid write or
  29. * erase operation trigerred an interrupt
  30. */
  31. #define QUADSPI_ISR_ILLEGAL_ERASE BIT(0)
  32. #define QUADSPI_ISR_ILLEGAL_WRITE BIT(1)
  33. struct altera_qspi_regs {
  34. u32 rd_status;
  35. u32 rd_sid;
  36. u32 rd_rdid;
  37. u32 mem_op;
  38. u32 isr;
  39. u32 imr;
  40. u32 chip_select;
  41. };
  42. struct altera_qspi_platdata {
  43. struct altera_qspi_regs *regs;
  44. void *base;
  45. unsigned long size;
  46. };
  47. static uint flash_verbose;
  48. flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
  49. static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
  50. uint64_t *len);
  51. void flash_print_info(flash_info_t *info)
  52. {
  53. struct mtd_info *mtd = info->mtd;
  54. loff_t ofs;
  55. u64 len;
  56. printf("Altera QSPI flash Size: %ld MB in %d Sectors\n",
  57. info->size >> 20, info->sector_count);
  58. altera_qspi_get_locked_range(mtd, &ofs, &len);
  59. printf(" %08lX +%lX", info->start[0], info->size);
  60. if (len) {
  61. printf(", protected %08llX +%llX",
  62. info->start[0] + ofs, len);
  63. }
  64. putc('\n');
  65. }
  66. void flash_set_verbose(uint v)
  67. {
  68. flash_verbose = v;
  69. }
  70. int flash_erase(flash_info_t *info, int s_first, int s_last)
  71. {
  72. struct mtd_info *mtd = info->mtd;
  73. struct erase_info instr;
  74. int ret;
  75. memset(&instr, 0, sizeof(instr));
  76. instr.mtd = mtd;
  77. instr.addr = mtd->erasesize * s_first;
  78. instr.len = mtd->erasesize * (s_last + 1 - s_first);
  79. flash_set_verbose(1);
  80. ret = mtd_erase(mtd, &instr);
  81. flash_set_verbose(0);
  82. if (ret)
  83. return ERR_PROTECTED;
  84. puts(" done\n");
  85. return 0;
  86. }
  87. int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  88. {
  89. struct mtd_info *mtd = info->mtd;
  90. struct udevice *dev = mtd->dev;
  91. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  92. ulong base = (ulong)pdata->base;
  93. loff_t to = addr - base;
  94. size_t retlen;
  95. int ret;
  96. ret = mtd_write(mtd, to, cnt, &retlen, src);
  97. if (ret)
  98. return ERR_PROTECTED;
  99. return 0;
  100. }
  101. unsigned long flash_init(void)
  102. {
  103. struct udevice *dev;
  104. /* probe every MTD device */
  105. for (uclass_first_device(UCLASS_MTD, &dev);
  106. dev;
  107. uclass_next_device(&dev)) {
  108. }
  109. return flash_info[0].size;
  110. }
  111. static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info *instr)
  112. {
  113. struct udevice *dev = mtd->dev;
  114. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  115. struct altera_qspi_regs *regs = pdata->regs;
  116. size_t addr = instr->addr;
  117. size_t len = instr->len;
  118. size_t end = addr + len;
  119. u32 sect;
  120. u32 stat;
  121. u32 *flash, *last;
  122. instr->state = MTD_ERASING;
  123. addr &= ~(mtd->erasesize - 1); /* get lower aligned address */
  124. while (addr < end) {
  125. if (ctrlc()) {
  126. if (flash_verbose)
  127. putc('\n');
  128. instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
  129. instr->state = MTD_ERASE_FAILED;
  130. mtd_erase_callback(instr);
  131. return -EIO;
  132. }
  133. flash = pdata->base + addr;
  134. last = pdata->base + addr + mtd->erasesize;
  135. /* skip erase if sector is blank */
  136. while (flash < last) {
  137. if (readl(flash) != 0xffffffff)
  138. break;
  139. flash++;
  140. }
  141. if (flash < last) {
  142. sect = addr / mtd->erasesize;
  143. sect <<= 8;
  144. sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
  145. debug("erase %08x\n", sect);
  146. writel(sect, &regs->mem_op);
  147. stat = readl(&regs->isr);
  148. if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
  149. /* erase failed, sector might be protected */
  150. debug("erase %08x fail %x\n", sect, stat);
  151. writel(stat, &regs->isr); /* clear isr */
  152. instr->fail_addr = addr;
  153. instr->state = MTD_ERASE_FAILED;
  154. mtd_erase_callback(instr);
  155. return -EIO;
  156. }
  157. if (flash_verbose)
  158. putc('.');
  159. } else {
  160. if (flash_verbose)
  161. putc(',');
  162. }
  163. addr += mtd->erasesize;
  164. }
  165. instr->state = MTD_ERASE_DONE;
  166. mtd_erase_callback(instr);
  167. return 0;
  168. }
  169. static int altera_qspi_read(struct mtd_info *mtd, loff_t from, size_t len,
  170. size_t *retlen, u_char *buf)
  171. {
  172. struct udevice *dev = mtd->dev;
  173. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  174. memcpy_fromio(buf, pdata->base + from, len);
  175. *retlen = len;
  176. return 0;
  177. }
  178. static int altera_qspi_write(struct mtd_info *mtd, loff_t to, size_t len,
  179. size_t *retlen, const u_char *buf)
  180. {
  181. struct udevice *dev = mtd->dev;
  182. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  183. struct altera_qspi_regs *regs = pdata->regs;
  184. u32 stat;
  185. memcpy_toio(pdata->base + to, buf, len);
  186. /* check whether write triggered a illegal write interrupt */
  187. stat = readl(&regs->isr);
  188. if (stat & QUADSPI_ISR_ILLEGAL_WRITE) {
  189. /* write failed, sector might be protected */
  190. debug("write fail %x\n", stat);
  191. writel(stat, &regs->isr); /* clear isr */
  192. return -EIO;
  193. }
  194. *retlen = len;
  195. return 0;
  196. }
  197. static void altera_qspi_sync(struct mtd_info *mtd)
  198. {
  199. }
  200. static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
  201. uint64_t *len)
  202. {
  203. struct udevice *dev = mtd->dev;
  204. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  205. struct altera_qspi_regs *regs = pdata->regs;
  206. int shift0 = ffs(QUADSPI_SR_BP2_0) - 1;
  207. int shift3 = ffs(QUADSPI_SR_BP3) - 1 - 3;
  208. u32 stat = readl(&regs->rd_status);
  209. unsigned pow = ((stat & QUADSPI_SR_BP2_0) >> shift0) |
  210. ((stat & QUADSPI_SR_BP3) >> shift3);
  211. *ofs = 0;
  212. *len = 0;
  213. if (pow) {
  214. *len = mtd->erasesize << (pow - 1);
  215. if (*len > mtd->size)
  216. *len = mtd->size;
  217. if (!(stat & QUADSPI_SR_TB))
  218. *ofs = mtd->size - *len;
  219. }
  220. }
  221. static int altera_qspi_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  222. {
  223. struct udevice *dev = mtd->dev;
  224. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  225. struct altera_qspi_regs *regs = pdata->regs;
  226. u32 sector_start, sector_end;
  227. u32 num_sectors;
  228. u32 mem_op;
  229. u32 sr_bp;
  230. u32 sr_tb;
  231. num_sectors = mtd->size / mtd->erasesize;
  232. sector_start = ofs / mtd->erasesize;
  233. sector_end = (ofs + len) / mtd->erasesize;
  234. if (sector_start >= num_sectors / 2) {
  235. sr_bp = fls(num_sectors - 1 - sector_start) + 1;
  236. sr_tb = 0;
  237. } else if (sector_end < num_sectors / 2) {
  238. sr_bp = fls(sector_end) + 1;
  239. sr_tb = 1;
  240. } else {
  241. sr_bp = 15;
  242. sr_tb = 0;
  243. }
  244. mem_op = (sr_tb << 12) | (sr_bp << 8);
  245. mem_op |= QUADSPI_MEM_OP_SECTOR_PROTECT;
  246. debug("lock %08x\n", mem_op);
  247. writel(mem_op, &regs->mem_op);
  248. return 0;
  249. }
  250. static int altera_qspi_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  251. {
  252. struct udevice *dev = mtd->dev;
  253. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  254. struct altera_qspi_regs *regs = pdata->regs;
  255. u32 mem_op;
  256. mem_op = QUADSPI_MEM_OP_SECTOR_PROTECT;
  257. debug("unlock %08x\n", mem_op);
  258. writel(mem_op, &regs->mem_op);
  259. return 0;
  260. }
  261. static int altera_qspi_probe(struct udevice *dev)
  262. {
  263. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  264. struct altera_qspi_regs *regs = pdata->regs;
  265. unsigned long base = (unsigned long)pdata->base;
  266. struct mtd_info *mtd;
  267. flash_info_t *flash = &flash_info[0];
  268. u32 rdid;
  269. int i;
  270. rdid = readl(&regs->rd_rdid);
  271. debug("rdid %x\n", rdid);
  272. mtd = dev_get_uclass_priv(dev);
  273. mtd->dev = dev;
  274. mtd->name = "nor0";
  275. mtd->type = MTD_NORFLASH;
  276. mtd->flags = MTD_CAP_NORFLASH;
  277. mtd->size = 1 << ((rdid & 0xff) - 6);
  278. mtd->writesize = 1;
  279. mtd->writebufsize = mtd->writesize;
  280. mtd->_erase = altera_qspi_erase;
  281. mtd->_read = altera_qspi_read;
  282. mtd->_write = altera_qspi_write;
  283. mtd->_sync = altera_qspi_sync;
  284. mtd->_lock = altera_qspi_lock;
  285. mtd->_unlock = altera_qspi_unlock;
  286. mtd->numeraseregions = 0;
  287. mtd->erasesize = 0x10000;
  288. if (add_mtd_device(mtd))
  289. return -ENOMEM;
  290. flash->mtd = mtd;
  291. flash->size = mtd->size;
  292. flash->sector_count = mtd->size / mtd->erasesize;
  293. flash->flash_id = rdid;
  294. flash->start[0] = base;
  295. for (i = 1; i < flash->sector_count; i++)
  296. flash->start[i] = flash->start[i - 1] + mtd->erasesize;
  297. gd->bd->bi_flashstart = base;
  298. return 0;
  299. }
  300. static int altera_qspi_ofdata_to_platdata(struct udevice *dev)
  301. {
  302. struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
  303. void *blob = (void *)gd->fdt_blob;
  304. int node = dev_of_offset(dev);
  305. const char *list, *end;
  306. const fdt32_t *cell;
  307. void *base;
  308. unsigned long addr, size;
  309. int parent, addrc, sizec;
  310. int len, idx;
  311. /*
  312. * decode regs. there are multiple reg tuples, and they need to
  313. * match with reg-names.
  314. */
  315. parent = fdt_parent_offset(blob, node);
  316. fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
  317. list = fdt_getprop(blob, node, "reg-names", &len);
  318. if (!list)
  319. return -ENOENT;
  320. end = list + len;
  321. cell = fdt_getprop(blob, node, "reg", &len);
  322. if (!cell)
  323. return -ENOENT;
  324. idx = 0;
  325. while (list < end) {
  326. addr = fdt_translate_address((void *)blob,
  327. node, cell + idx);
  328. size = fdt_addr_to_cpu(cell[idx + addrc]);
  329. base = map_physmem(addr, size, MAP_NOCACHE);
  330. len = strlen(list);
  331. if (strcmp(list, "avl_csr") == 0) {
  332. pdata->regs = base;
  333. } else if (strcmp(list, "avl_mem") == 0) {
  334. pdata->base = base;
  335. pdata->size = size;
  336. }
  337. idx += addrc + sizec;
  338. list += (len + 1);
  339. }
  340. return 0;
  341. }
  342. static const struct udevice_id altera_qspi_ids[] = {
  343. { .compatible = "altr,quadspi-1.0" },
  344. {}
  345. };
  346. U_BOOT_DRIVER(altera_qspi) = {
  347. .name = "altera_qspi",
  348. .id = UCLASS_MTD,
  349. .of_match = altera_qspi_ids,
  350. .ofdata_to_platdata = altera_qspi_ofdata_to_platdata,
  351. .platdata_auto_alloc_size = sizeof(struct altera_qspi_platdata),
  352. .probe = altera_qspi_probe,
  353. };