xenon_sdhci.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Marvell SOC Platform Group Xenon SDHC as a platform device
  4. *
  5. * Copyright (C) 2016 Marvell, All Rights Reserved.
  6. *
  7. * Author: Victor Gu <xigu@marvell.com>
  8. * Date: 2016-8-24
  9. *
  10. * Included parts of the Linux driver version which was written by:
  11. * Hu Ziji <huziji@marvell.com>
  12. *
  13. * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
  14. * Stefan Roese <sr@denx.de>
  15. */
  16. #include <common.h>
  17. #include <dm.h>
  18. #include <fdtdec.h>
  19. #include <linux/libfdt.h>
  20. #include <malloc.h>
  21. #include <sdhci.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. /* Register Offset of SD Host Controller SOCP self-defined register */
  24. #define SDHC_SYS_CFG_INFO 0x0104
  25. #define SLOT_TYPE_SDIO_SHIFT 24
  26. #define SLOT_TYPE_EMMC_MASK 0xFF
  27. #define SLOT_TYPE_EMMC_SHIFT 16
  28. #define SLOT_TYPE_SD_SDIO_MMC_MASK 0xFF
  29. #define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8
  30. #define NR_SUPPORTED_SLOT_MASK 0x7
  31. #define SDHC_SYS_OP_CTRL 0x0108
  32. #define AUTO_CLKGATE_DISABLE_MASK BIT(20)
  33. #define SDCLK_IDLEOFF_ENABLE_SHIFT 8
  34. #define SLOT_ENABLE_SHIFT 0
  35. #define SDHC_SYS_EXT_OP_CTRL 0x010C
  36. #define MASK_CMD_CONFLICT_ERROR BIT(8)
  37. #define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144
  38. /* retuning compatible */
  39. #define RETUNING_COMPATIBLE 0x1
  40. /* Xenon specific Mode Select value */
  41. #define XENON_SDHCI_CTRL_HS200 0x5
  42. #define XENON_SDHCI_CTRL_HS400 0x6
  43. #define EMMC_PHY_REG_BASE 0x170
  44. #define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE
  45. #define OUTPUT_QSN_PHASE_SELECT BIT(17)
  46. #define SAMPL_INV_QSP_PHASE_SELECT BIT(18)
  47. #define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18
  48. #define EMMC_PHY_SLOW_MODE BIT(29)
  49. #define PHY_INITIALIZAION BIT(31)
  50. #define WAIT_CYCLE_BEFORE_USING_MASK 0xf
  51. #define WAIT_CYCLE_BEFORE_USING_SHIFT 12
  52. #define FC_SYNC_EN_DURATION_MASK 0xf
  53. #define FC_SYNC_EN_DURATION_SHIFT 8
  54. #define FC_SYNC_RST_EN_DURATION_MASK 0xf
  55. #define FC_SYNC_RST_EN_DURATION_SHIFT 4
  56. #define FC_SYNC_RST_DURATION_MASK 0xf
  57. #define FC_SYNC_RST_DURATION_SHIFT 0
  58. #define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4)
  59. #define DQ_ASYNC_MODE BIT(4)
  60. #define DQ_DDR_MODE_SHIFT 8
  61. #define DQ_DDR_MODE_MASK 0xff
  62. #define CMD_DDR_MODE BIT(16)
  63. #define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8)
  64. #define REC_EN_SHIFT 24
  65. #define REC_EN_MASK 0xf
  66. #define FC_DQ_RECEN BIT(24)
  67. #define FC_CMD_RECEN BIT(25)
  68. #define FC_QSP_RECEN BIT(26)
  69. #define FC_QSN_RECEN BIT(27)
  70. #define OEN_QSN BIT(28)
  71. #define AUTO_RECEN_CTRL BIT(30)
  72. #define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc)
  73. #define EMMC5_1_FC_QSP_PD BIT(9)
  74. #define EMMC5_1_FC_QSP_PU BIT(25)
  75. #define EMMC5_1_FC_CMD_PD BIT(8)
  76. #define EMMC5_1_FC_CMD_PU BIT(24)
  77. #define EMMC5_1_FC_DQ_PD 0xff
  78. #define EMMC5_1_FC_DQ_PU (0xff << 16)
  79. #define SDHCI_RETUNE_EVT_INTSIG 0x00001000
  80. /* Hyperion only have one slot 0 */
  81. #define XENON_MMC_SLOT_ID_HYPERION 0
  82. #define MMC_TIMING_LEGACY 0
  83. #define MMC_TIMING_MMC_HS 1
  84. #define MMC_TIMING_SD_HS 2
  85. #define MMC_TIMING_UHS_SDR12 3
  86. #define MMC_TIMING_UHS_SDR25 4
  87. #define MMC_TIMING_UHS_SDR50 5
  88. #define MMC_TIMING_UHS_SDR104 6
  89. #define MMC_TIMING_UHS_DDR50 7
  90. #define MMC_TIMING_MMC_DDR52 8
  91. #define MMC_TIMING_MMC_HS200 9
  92. #define MMC_TIMING_MMC_HS400 10
  93. #define XENON_MMC_MAX_CLK 400000000
  94. enum soc_pad_ctrl_type {
  95. SOC_PAD_SD,
  96. SOC_PAD_FIXED_1_8V,
  97. };
  98. struct xenon_sdhci_plat {
  99. struct mmc_config cfg;
  100. struct mmc mmc;
  101. };
  102. struct xenon_sdhci_priv {
  103. struct sdhci_host host;
  104. u8 timing;
  105. unsigned int clock;
  106. void *pad_ctrl_reg;
  107. int pad_type;
  108. };
  109. static int xenon_mmc_phy_init(struct sdhci_host *host)
  110. {
  111. struct xenon_sdhci_priv *priv = host->mmc->priv;
  112. u32 clock = priv->clock;
  113. u32 time;
  114. u32 var;
  115. /* Enable QSP PHASE SELECT */
  116. var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
  117. var |= SAMPL_INV_QSP_PHASE_SELECT;
  118. if ((priv->timing == MMC_TIMING_UHS_SDR50) ||
  119. (priv->timing == MMC_TIMING_UHS_SDR25) ||
  120. (priv->timing == MMC_TIMING_UHS_SDR12) ||
  121. (priv->timing == MMC_TIMING_SD_HS) ||
  122. (priv->timing == MMC_TIMING_LEGACY))
  123. var |= EMMC_PHY_SLOW_MODE;
  124. sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
  125. /* Poll for host MMC PHY clock init to be stable */
  126. /* Wait up to 10ms */
  127. time = 100;
  128. while (time--) {
  129. var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
  130. if (var & SDHCI_CLOCK_INT_STABLE)
  131. break;
  132. udelay(100);
  133. }
  134. if (time <= 0) {
  135. pr_err("Failed to enable MMC internal clock in time\n");
  136. return -ETIMEDOUT;
  137. }
  138. /* Init PHY */
  139. var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
  140. var |= PHY_INITIALIZAION;
  141. sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
  142. if (clock == 0) {
  143. /* Use the possibly slowest bus frequency value */
  144. clock = 100000;
  145. }
  146. /* Poll for host eMMC PHY init to complete */
  147. /* Wait up to 10ms */
  148. time = 100;
  149. while (time--) {
  150. var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
  151. var &= PHY_INITIALIZAION;
  152. if (!var)
  153. break;
  154. /* wait for host eMMC PHY init to complete */
  155. udelay(100);
  156. }
  157. if (time <= 0) {
  158. pr_err("Failed to init MMC PHY in time\n");
  159. return -ETIMEDOUT;
  160. }
  161. return 0;
  162. }
  163. #define ARMADA_3700_SOC_PAD_1_8V 0x1
  164. #define ARMADA_3700_SOC_PAD_3_3V 0x0
  165. static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host)
  166. {
  167. struct xenon_sdhci_priv *priv = host->mmc->priv;
  168. if (priv->pad_type == SOC_PAD_FIXED_1_8V)
  169. writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg);
  170. else if (priv->pad_type == SOC_PAD_SD)
  171. writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
  172. }
  173. static void xenon_mmc_phy_set(struct sdhci_host *host)
  174. {
  175. struct xenon_sdhci_priv *priv = host->mmc->priv;
  176. u32 var;
  177. /* Setup pad, set bit[30], bit[28] and bits[26:24] */
  178. var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL);
  179. var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN |
  180. FC_CMD_RECEN | FC_DQ_RECEN;
  181. sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL);
  182. /* Set CMD and DQ Pull Up */
  183. var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1);
  184. var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU);
  185. var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);
  186. sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1);
  187. /*
  188. * If timing belongs to high speed, set bit[17] of
  189. * EMMC_PHY_TIMING_ADJUST register
  190. */
  191. if ((priv->timing == MMC_TIMING_MMC_HS400) ||
  192. (priv->timing == MMC_TIMING_MMC_HS200) ||
  193. (priv->timing == MMC_TIMING_UHS_SDR50) ||
  194. (priv->timing == MMC_TIMING_UHS_SDR104) ||
  195. (priv->timing == MMC_TIMING_UHS_DDR50) ||
  196. (priv->timing == MMC_TIMING_UHS_SDR25) ||
  197. (priv->timing == MMC_TIMING_MMC_DDR52)) {
  198. var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
  199. var |= OUTPUT_QSN_PHASE_SELECT;
  200. sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
  201. }
  202. /*
  203. * When setting EMMC_PHY_FUNC_CONTROL register,
  204. * SD clock should be disabled
  205. */
  206. var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
  207. var &= ~SDHCI_CLOCK_CARD_EN;
  208. sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
  209. var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);
  210. if (host->mmc->ddr_mode) {
  211. var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
  212. } else {
  213. var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |
  214. CMD_DDR_MODE);
  215. }
  216. sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL);
  217. /* Enable bus clock */
  218. var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
  219. var |= SDHCI_CLOCK_CARD_EN;
  220. sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
  221. xenon_mmc_phy_init(host);
  222. }
  223. /* Enable/Disable the Auto Clock Gating function of this slot */
  224. static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable)
  225. {
  226. u32 var;
  227. var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
  228. if (enable)
  229. var &= ~AUTO_CLKGATE_DISABLE_MASK;
  230. else
  231. var |= AUTO_CLKGATE_DISABLE_MASK;
  232. sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
  233. }
  234. #define SLOT_MASK(slot) BIT(slot)
  235. /* Enable specific slot */
  236. static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot)
  237. {
  238. u32 var;
  239. var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
  240. var |= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT;
  241. sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
  242. }
  243. /* Enable Parallel Transfer Mode */
  244. static void xenon_mmc_enable_parallel_tran(struct sdhci_host *host, u8 slot)
  245. {
  246. u32 var;
  247. var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
  248. var |= SLOT_MASK(slot);
  249. sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL);
  250. }
  251. static void xenon_mmc_disable_tuning(struct sdhci_host *host, u8 slot)
  252. {
  253. u32 var;
  254. /* Clear the Re-Tuning Request functionality */
  255. var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL);
  256. var &= ~RETUNING_COMPATIBLE;
  257. sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL);
  258. /* Clear the Re-tuning Event Signal Enable */
  259. var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
  260. var &= ~SDHCI_RETUNE_EVT_INTSIG;
  261. sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE);
  262. }
  263. /* Mask command conflict error */
  264. static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
  265. {
  266. u32 reg;
  267. reg = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
  268. reg |= MASK_CMD_CONFLICT_ERROR;
  269. sdhci_writel(host, reg, SDHC_SYS_EXT_OP_CTRL);
  270. }
  271. /* Platform specific function for post set_ios configuration */
  272. static int xenon_sdhci_set_ios_post(struct sdhci_host *host)
  273. {
  274. struct xenon_sdhci_priv *priv = host->mmc->priv;
  275. uint speed = host->mmc->tran_speed;
  276. int pwr_18v = 0;
  277. if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
  278. SDHCI_POWER_180)
  279. pwr_18v = 1;
  280. /* Set timing variable according to the configured speed */
  281. if (IS_SD(host->mmc)) {
  282. /* SD/SDIO */
  283. if (pwr_18v) {
  284. if (host->mmc->ddr_mode)
  285. priv->timing = MMC_TIMING_UHS_DDR50;
  286. else if (speed <= 25000000)
  287. priv->timing = MMC_TIMING_UHS_SDR25;
  288. else
  289. priv->timing = MMC_TIMING_UHS_SDR50;
  290. } else {
  291. if (speed <= 25000000)
  292. priv->timing = MMC_TIMING_LEGACY;
  293. else
  294. priv->timing = MMC_TIMING_SD_HS;
  295. }
  296. } else {
  297. /* eMMC */
  298. if (host->mmc->ddr_mode)
  299. priv->timing = MMC_TIMING_MMC_DDR52;
  300. else if (speed <= 26000000)
  301. priv->timing = MMC_TIMING_LEGACY;
  302. else
  303. priv->timing = MMC_TIMING_MMC_HS;
  304. }
  305. /* Re-init the PHY */
  306. xenon_mmc_phy_set(host);
  307. return 0;
  308. }
  309. /* Install a driver specific handler for post set_ios configuration */
  310. static const struct sdhci_ops xenon_sdhci_ops = {
  311. .set_ios_post = xenon_sdhci_set_ios_post
  312. };
  313. static int xenon_sdhci_probe(struct udevice *dev)
  314. {
  315. struct xenon_sdhci_plat *plat = dev_get_platdata(dev);
  316. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  317. struct xenon_sdhci_priv *priv = dev_get_priv(dev);
  318. struct sdhci_host *host = dev_get_priv(dev);
  319. int ret;
  320. host->mmc = &plat->mmc;
  321. host->mmc->priv = host;
  322. host->mmc->dev = dev;
  323. upriv->mmc = host->mmc;
  324. /* Set quirks */
  325. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;
  326. /* Set default timing */
  327. priv->timing = MMC_TIMING_LEGACY;
  328. /* Disable auto clock gating during init */
  329. xenon_mmc_set_acg(host, false);
  330. /* Enable slot */
  331. xenon_mmc_enable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
  332. /*
  333. * Set default power on SoC PHY PAD register (currently only
  334. * available on the Armada 3700)
  335. */
  336. if (priv->pad_ctrl_reg)
  337. armada_3700_soc_pad_voltage_set(host);
  338. host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;
  339. switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
  340. 1)) {
  341. case 8:
  342. host->host_caps |= MMC_MODE_8BIT;
  343. break;
  344. case 4:
  345. host->host_caps |= MMC_MODE_4BIT;
  346. break;
  347. case 1:
  348. break;
  349. default:
  350. printf("Invalid \"bus-width\" value\n");
  351. return -EINVAL;
  352. }
  353. host->ops = &xenon_sdhci_ops;
  354. host->max_clk = XENON_MMC_MAX_CLK;
  355. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
  356. if (ret)
  357. return ret;
  358. ret = sdhci_probe(dev);
  359. if (ret)
  360. return ret;
  361. /* Enable parallel transfer */
  362. xenon_mmc_enable_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION);
  363. /* Disable tuning functionality of this slot */
  364. xenon_mmc_disable_tuning(host, XENON_MMC_SLOT_ID_HYPERION);
  365. /* Enable auto clock gating after init */
  366. xenon_mmc_set_acg(host, true);
  367. xenon_mask_cmd_conflict_err(host);
  368. return ret;
  369. }
  370. static int xenon_sdhci_ofdata_to_platdata(struct udevice *dev)
  371. {
  372. struct sdhci_host *host = dev_get_priv(dev);
  373. struct xenon_sdhci_priv *priv = dev_get_priv(dev);
  374. const char *name;
  375. host->name = dev->name;
  376. host->ioaddr = (void *)devfdt_get_addr(dev);
  377. if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
  378. priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
  379. name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
  380. NULL);
  381. if (name) {
  382. if (0 == strncmp(name, "sd", 2)) {
  383. priv->pad_type = SOC_PAD_SD;
  384. } else if (0 == strncmp(name, "fixed-1-8v", 10)) {
  385. priv->pad_type = SOC_PAD_FIXED_1_8V;
  386. } else {
  387. printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
  388. return -EINVAL;
  389. }
  390. }
  391. return 0;
  392. }
  393. static int xenon_sdhci_bind(struct udevice *dev)
  394. {
  395. struct xenon_sdhci_plat *plat = dev_get_platdata(dev);
  396. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  397. }
  398. static const struct udevice_id xenon_sdhci_ids[] = {
  399. { .compatible = "marvell,armada-8k-sdhci",},
  400. { .compatible = "marvell,armada-3700-sdhci",},
  401. { }
  402. };
  403. U_BOOT_DRIVER(xenon_sdhci_drv) = {
  404. .name = "xenon_sdhci",
  405. .id = UCLASS_MMC,
  406. .of_match = xenon_sdhci_ids,
  407. .ofdata_to_platdata = xenon_sdhci_ofdata_to_platdata,
  408. .ops = &sdhci_ops,
  409. .bind = xenon_sdhci_bind,
  410. .probe = xenon_sdhci_probe,
  411. .priv_auto_alloc_size = sizeof(struct xenon_sdhci_priv),
  412. .platdata_auto_alloc_size = sizeof(struct xenon_sdhci_plat),
  413. };