socfpga_dw_mmc.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <asm/arch/clock_manager.h>
  7. #include <asm/arch/system_manager.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <dwmmc.h>
  11. #include <errno.h>
  12. #include <fdtdec.h>
  13. #include <dm/device_compat.h>
  14. #include <linux/libfdt.h>
  15. #include <linux/err.h>
  16. #include <malloc.h>
  17. #include <reset.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. struct socfpga_dwmci_plat {
  20. struct mmc_config cfg;
  21. struct mmc mmc;
  22. };
  23. /* socfpga implmentation specific driver private data */
  24. struct dwmci_socfpga_priv_data {
  25. struct dwmci_host host;
  26. unsigned int drvsel;
  27. unsigned int smplsel;
  28. };
  29. static void socfpga_dwmci_reset(struct udevice *dev)
  30. {
  31. struct reset_ctl_bulk reset_bulk;
  32. int ret;
  33. ret = reset_get_bulk(dev, &reset_bulk);
  34. if (ret) {
  35. dev_warn(dev, "Can't get reset: %d\n", ret);
  36. return;
  37. }
  38. reset_deassert_bulk(&reset_bulk);
  39. }
  40. static void socfpga_dwmci_clksel(struct dwmci_host *host)
  41. {
  42. struct dwmci_socfpga_priv_data *priv = host->priv;
  43. u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
  44. ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
  45. /* Disable SDMMC clock. */
  46. clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
  47. CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  48. debug("%s: drvsel %d smplsel %d\n", __func__,
  49. priv->drvsel, priv->smplsel);
  50. writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
  51. debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
  52. readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
  53. /* Enable SDMMC clock */
  54. setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
  55. CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  56. }
  57. static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
  58. {
  59. struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  60. struct dwmci_host *host = &priv->host;
  61. #if CONFIG_IS_ENABLED(CLK)
  62. struct clk clk;
  63. int ret;
  64. ret = clk_get_by_index(dev, 1, &clk);
  65. if (ret)
  66. return ret;
  67. host->bus_hz = clk_get_rate(&clk);
  68. clk_free(&clk);
  69. #else
  70. /* Fixed clock divide by 4 which due to the SDMMC wrapper */
  71. host->bus_hz = cm_get_mmc_controller_clk_hz();
  72. #endif
  73. if (host->bus_hz == 0) {
  74. printf("DWMMC: MMC clock is zero!");
  75. return -EINVAL;
  76. }
  77. return 0;
  78. }
  79. static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
  80. {
  81. struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  82. struct dwmci_host *host = &priv->host;
  83. int fifo_depth;
  84. fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  85. "fifo-depth", 0);
  86. if (fifo_depth < 0) {
  87. printf("DWMMC: Can't get FIFO depth\n");
  88. return -EINVAL;
  89. }
  90. host->name = dev->name;
  91. host->ioaddr = (void *)devfdt_get_addr(dev);
  92. host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  93. "bus-width", 4);
  94. host->clksel = socfpga_dwmci_clksel;
  95. /*
  96. * TODO(sjg@chromium.org): Remove the need for this hack.
  97. * We only have one dwmmc block on gen5 SoCFPGA.
  98. */
  99. host->dev_index = 0;
  100. host->fifoth_val = MSIZE(0x2) |
  101. RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
  102. priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  103. "drvsel", 3);
  104. priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  105. "smplsel", 0);
  106. host->priv = priv;
  107. return 0;
  108. }
  109. static int socfpga_dwmmc_probe(struct udevice *dev)
  110. {
  111. #ifdef CONFIG_BLK
  112. struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
  113. #endif
  114. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  115. struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
  116. struct dwmci_host *host = &priv->host;
  117. int ret;
  118. ret = socfpga_dwmmc_get_clk_rate(dev);
  119. if (ret)
  120. return ret;
  121. socfpga_dwmci_reset(dev);
  122. #ifdef CONFIG_BLK
  123. dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
  124. host->mmc = &plat->mmc;
  125. #else
  126. ret = add_dwmci(host, host->bus_hz, 400000);
  127. if (ret)
  128. return ret;
  129. #endif
  130. host->mmc->priv = &priv->host;
  131. upriv->mmc = host->mmc;
  132. host->mmc->dev = dev;
  133. return dwmci_probe(dev);
  134. }
  135. static int socfpga_dwmmc_bind(struct udevice *dev)
  136. {
  137. #ifdef CONFIG_BLK
  138. struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
  139. int ret;
  140. ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
  141. if (ret)
  142. return ret;
  143. #endif
  144. return 0;
  145. }
  146. static const struct udevice_id socfpga_dwmmc_ids[] = {
  147. { .compatible = "altr,socfpga-dw-mshc" },
  148. { }
  149. };
  150. U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
  151. .name = "socfpga_dwmmc",
  152. .id = UCLASS_MMC,
  153. .of_match = socfpga_dwmmc_ids,
  154. .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
  155. .ops = &dm_dwmci_ops,
  156. .bind = socfpga_dwmmc_bind,
  157. .probe = socfpga_dwmmc_probe,
  158. .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
  159. .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
  160. };