sh_mmcif.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MMCIF driver.
  4. *
  5. * Copyright (C) 2011 Renesas Solutions Corp.
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <watchdog.h>
  10. #include <command.h>
  11. #include <mmc.h>
  12. #include <clk.h>
  13. #include <dm.h>
  14. #include <malloc.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/errno.h>
  17. #include <linux/compat.h>
  18. #include <linux/io.h>
  19. #include <linux/sizes.h>
  20. #include "sh_mmcif.h"
  21. #define DRIVER_NAME "sh_mmcif"
  22. static int sh_mmcif_intr(void *dev_id)
  23. {
  24. struct sh_mmcif_host *host = dev_id;
  25. u32 state = 0;
  26. state = sh_mmcif_read(&host->regs->ce_int);
  27. state &= sh_mmcif_read(&host->regs->ce_int_mask);
  28. if (state & INT_RBSYE) {
  29. sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
  30. sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
  31. goto end;
  32. } else if (state & INT_CRSPE) {
  33. sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
  34. sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
  35. /* one more interrupt (INT_RBSYE) */
  36. if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
  37. return -EAGAIN;
  38. goto end;
  39. } else if (state & INT_BUFREN) {
  40. sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
  41. sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
  42. goto end;
  43. } else if (state & INT_BUFWEN) {
  44. sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
  45. sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
  46. goto end;
  47. } else if (state & INT_CMD12DRE) {
  48. sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
  49. INT_BUFRE), &host->regs->ce_int);
  50. sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
  51. goto end;
  52. } else if (state & INT_BUFRE) {
  53. sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
  54. sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
  55. goto end;
  56. } else if (state & INT_DTRANE) {
  57. sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
  58. sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
  59. goto end;
  60. } else if (state & INT_CMD12RBE) {
  61. sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
  62. &host->regs->ce_int);
  63. sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
  64. goto end;
  65. } else if (state & INT_ERR_STS) {
  66. /* err interrupts */
  67. sh_mmcif_write(~state, &host->regs->ce_int);
  68. sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
  69. goto err;
  70. } else
  71. return -EAGAIN;
  72. err:
  73. host->sd_error = 1;
  74. debug("%s: int err state = %08x\n", DRIVER_NAME, state);
  75. end:
  76. host->wait_int = 1;
  77. return 0;
  78. }
  79. static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
  80. {
  81. int timeout = 10000000;
  82. while (1) {
  83. timeout--;
  84. if (timeout < 0) {
  85. printf("timeout\n");
  86. return 0;
  87. }
  88. if (!sh_mmcif_intr(host))
  89. break;
  90. udelay(1); /* 1 usec */
  91. }
  92. return 1; /* Return value: NOT 0 = complete waiting */
  93. }
  94. static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
  95. {
  96. sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
  97. sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
  98. if (!clk)
  99. return;
  100. if (clk == CLKDEV_EMMC_DATA)
  101. sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
  102. else
  103. sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
  104. clk) - 1) - 1) << 16,
  105. &host->regs->ce_clk_ctrl);
  106. sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
  107. }
  108. static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
  109. {
  110. u32 tmp;
  111. tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
  112. CLK_CLEAR);
  113. sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
  114. sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
  115. sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
  116. &host->regs->ce_clk_ctrl);
  117. /* byte swap on */
  118. sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
  119. }
  120. static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
  121. {
  122. u32 state1, state2;
  123. int ret, timeout = 10000000;
  124. host->sd_error = 0;
  125. host->wait_int = 0;
  126. state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
  127. state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
  128. debug("%s: ERR HOST_STS1 = %08x\n", \
  129. DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
  130. debug("%s: ERR HOST_STS2 = %08x\n", \
  131. DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
  132. if (state1 & STS1_CMDSEQ) {
  133. debug("%s: Forced end of command sequence\n", DRIVER_NAME);
  134. sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
  135. sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
  136. while (1) {
  137. timeout--;
  138. if (timeout < 0) {
  139. printf(DRIVER_NAME": Forceed end of " \
  140. "command sequence timeout err\n");
  141. return -EILSEQ;
  142. }
  143. if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
  144. & STS1_CMDSEQ))
  145. break;
  146. }
  147. sh_mmcif_sync_reset(host);
  148. return -EILSEQ;
  149. }
  150. if (state2 & STS2_CRC_ERR)
  151. ret = -EILSEQ;
  152. else if (state2 & STS2_TIMEOUT_ERR)
  153. ret = -ETIMEDOUT;
  154. else
  155. ret = -EILSEQ;
  156. return ret;
  157. }
  158. static int sh_mmcif_single_read(struct sh_mmcif_host *host,
  159. struct mmc_data *data)
  160. {
  161. long time;
  162. u32 blocksize, i;
  163. unsigned long *p = (unsigned long *)data->dest;
  164. if ((unsigned long)p & 0x00000001) {
  165. printf("%s: The data pointer is unaligned.", __func__);
  166. return -EIO;
  167. }
  168. host->wait_int = 0;
  169. /* buf read enable */
  170. sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
  171. time = mmcif_wait_interrupt_flag(host);
  172. if (time == 0 || host->sd_error != 0)
  173. return sh_mmcif_error_manage(host);
  174. host->wait_int = 0;
  175. blocksize = (BLOCK_SIZE_MASK &
  176. sh_mmcif_read(&host->regs->ce_block_set)) + 3;
  177. for (i = 0; i < blocksize / 4; i++)
  178. *p++ = sh_mmcif_read(&host->regs->ce_data);
  179. /* buffer read end */
  180. sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
  181. time = mmcif_wait_interrupt_flag(host);
  182. if (time == 0 || host->sd_error != 0)
  183. return sh_mmcif_error_manage(host);
  184. host->wait_int = 0;
  185. return 0;
  186. }
  187. static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
  188. struct mmc_data *data)
  189. {
  190. long time;
  191. u32 blocksize, i, j;
  192. unsigned long *p = (unsigned long *)data->dest;
  193. if ((unsigned long)p & 0x00000001) {
  194. printf("%s: The data pointer is unaligned.", __func__);
  195. return -EIO;
  196. }
  197. host->wait_int = 0;
  198. blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
  199. for (j = 0; j < data->blocks; j++) {
  200. sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
  201. time = mmcif_wait_interrupt_flag(host);
  202. if (time == 0 || host->sd_error != 0)
  203. return sh_mmcif_error_manage(host);
  204. host->wait_int = 0;
  205. for (i = 0; i < blocksize / 4; i++)
  206. *p++ = sh_mmcif_read(&host->regs->ce_data);
  207. WATCHDOG_RESET();
  208. }
  209. return 0;
  210. }
  211. static int sh_mmcif_single_write(struct sh_mmcif_host *host,
  212. struct mmc_data *data)
  213. {
  214. long time;
  215. u32 blocksize, i;
  216. const unsigned long *p = (unsigned long *)data->dest;
  217. if ((unsigned long)p & 0x00000001) {
  218. printf("%s: The data pointer is unaligned.", __func__);
  219. return -EIO;
  220. }
  221. host->wait_int = 0;
  222. sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
  223. time = mmcif_wait_interrupt_flag(host);
  224. if (time == 0 || host->sd_error != 0)
  225. return sh_mmcif_error_manage(host);
  226. host->wait_int = 0;
  227. blocksize = (BLOCK_SIZE_MASK &
  228. sh_mmcif_read(&host->regs->ce_block_set)) + 3;
  229. for (i = 0; i < blocksize / 4; i++)
  230. sh_mmcif_write(*p++, &host->regs->ce_data);
  231. /* buffer write end */
  232. sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
  233. time = mmcif_wait_interrupt_flag(host);
  234. if (time == 0 || host->sd_error != 0)
  235. return sh_mmcif_error_manage(host);
  236. host->wait_int = 0;
  237. return 0;
  238. }
  239. static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
  240. struct mmc_data *data)
  241. {
  242. long time;
  243. u32 i, j, blocksize;
  244. const unsigned long *p = (unsigned long *)data->dest;
  245. if ((unsigned long)p & 0x00000001) {
  246. printf("%s: The data pointer is unaligned.", __func__);
  247. return -EIO;
  248. }
  249. host->wait_int = 0;
  250. blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
  251. for (j = 0; j < data->blocks; j++) {
  252. sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
  253. time = mmcif_wait_interrupt_flag(host);
  254. if (time == 0 || host->sd_error != 0)
  255. return sh_mmcif_error_manage(host);
  256. host->wait_int = 0;
  257. for (i = 0; i < blocksize / 4; i++)
  258. sh_mmcif_write(*p++, &host->regs->ce_data);
  259. WATCHDOG_RESET();
  260. }
  261. return 0;
  262. }
  263. static void sh_mmcif_get_response(struct sh_mmcif_host *host,
  264. struct mmc_cmd *cmd)
  265. {
  266. if (cmd->resp_type & MMC_RSP_136) {
  267. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
  268. cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
  269. cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
  270. cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
  271. debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
  272. cmd->response[1], cmd->response[2], cmd->response[3]);
  273. } else {
  274. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
  275. }
  276. }
  277. static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
  278. struct mmc_cmd *cmd)
  279. {
  280. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
  281. }
  282. static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
  283. struct mmc_data *data, struct mmc_cmd *cmd)
  284. {
  285. u32 tmp = 0;
  286. u32 opc = cmd->cmdidx;
  287. /* Response Type check */
  288. switch (cmd->resp_type) {
  289. case MMC_RSP_NONE:
  290. tmp |= CMD_SET_RTYP_NO;
  291. break;
  292. case MMC_RSP_R1:
  293. case MMC_RSP_R1b:
  294. case MMC_RSP_R3:
  295. tmp |= CMD_SET_RTYP_6B;
  296. break;
  297. case MMC_RSP_R2:
  298. tmp |= CMD_SET_RTYP_17B;
  299. break;
  300. default:
  301. printf(DRIVER_NAME": Not support type response.\n");
  302. break;
  303. }
  304. /* RBSY */
  305. if (opc == MMC_CMD_SWITCH)
  306. tmp |= CMD_SET_RBSY;
  307. /* WDAT / DATW */
  308. if (host->data) {
  309. tmp |= CMD_SET_WDAT;
  310. switch (host->bus_width) {
  311. case MMC_BUS_WIDTH_1:
  312. tmp |= CMD_SET_DATW_1;
  313. break;
  314. case MMC_BUS_WIDTH_4:
  315. tmp |= CMD_SET_DATW_4;
  316. break;
  317. case MMC_BUS_WIDTH_8:
  318. tmp |= CMD_SET_DATW_8;
  319. break;
  320. default:
  321. printf(DRIVER_NAME": Not support bus width.\n");
  322. break;
  323. }
  324. }
  325. /* DWEN */
  326. if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
  327. opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
  328. tmp |= CMD_SET_DWEN;
  329. /* CMLTE/CMD12EN */
  330. if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
  331. opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
  332. tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
  333. sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
  334. }
  335. /* RIDXC[1:0] check bits */
  336. if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
  337. opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
  338. tmp |= CMD_SET_RIDXC_BITS;
  339. /* RCRC7C[1:0] check bits */
  340. if (opc == MMC_CMD_SEND_OP_COND)
  341. tmp |= CMD_SET_CRC7C_BITS;
  342. /* RCRC7C[1:0] internal CRC7 */
  343. if (opc == MMC_CMD_ALL_SEND_CID ||
  344. opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
  345. tmp |= CMD_SET_CRC7C_INTERNAL;
  346. return opc = ((opc << 24) | tmp);
  347. }
  348. static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
  349. struct mmc_data *data, u16 opc)
  350. {
  351. u32 ret;
  352. switch (opc) {
  353. case MMC_CMD_READ_MULTIPLE_BLOCK:
  354. ret = sh_mmcif_multi_read(host, data);
  355. break;
  356. case MMC_CMD_WRITE_MULTIPLE_BLOCK:
  357. ret = sh_mmcif_multi_write(host, data);
  358. break;
  359. case MMC_CMD_WRITE_SINGLE_BLOCK:
  360. ret = sh_mmcif_single_write(host, data);
  361. break;
  362. case MMC_CMD_READ_SINGLE_BLOCK:
  363. case MMC_CMD_SEND_EXT_CSD:
  364. ret = sh_mmcif_single_read(host, data);
  365. break;
  366. default:
  367. printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
  368. ret = -EINVAL;
  369. break;
  370. }
  371. return ret;
  372. }
  373. static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
  374. struct mmc_data *data, struct mmc_cmd *cmd)
  375. {
  376. long time;
  377. int ret = 0, mask = 0;
  378. u32 opc = cmd->cmdidx;
  379. if (opc == MMC_CMD_STOP_TRANSMISSION) {
  380. /* MMCIF sends the STOP command automatically */
  381. if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
  382. sh_mmcif_bitset(MASK_MCMD12DRE,
  383. &host->regs->ce_int_mask);
  384. else
  385. sh_mmcif_bitset(MASK_MCMD12RBE,
  386. &host->regs->ce_int_mask);
  387. time = mmcif_wait_interrupt_flag(host);
  388. if (time == 0 || host->sd_error != 0)
  389. return sh_mmcif_error_manage(host);
  390. sh_mmcif_get_cmd12response(host, cmd);
  391. return 0;
  392. }
  393. if (opc == MMC_CMD_SWITCH)
  394. mask = MASK_MRBSYE;
  395. else
  396. mask = MASK_MCRSPE;
  397. mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
  398. MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
  399. MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
  400. MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
  401. if (host->data) {
  402. sh_mmcif_write(0, &host->regs->ce_block_set);
  403. sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
  404. }
  405. opc = sh_mmcif_set_cmd(host, data, cmd);
  406. sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
  407. sh_mmcif_write(mask, &host->regs->ce_int_mask);
  408. debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
  409. /* set arg */
  410. sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
  411. host->wait_int = 0;
  412. /* set cmd */
  413. sh_mmcif_write(opc, &host->regs->ce_cmd_set);
  414. time = mmcif_wait_interrupt_flag(host);
  415. if (time == 0)
  416. return sh_mmcif_error_manage(host);
  417. if (host->sd_error) {
  418. switch (cmd->cmdidx) {
  419. case MMC_CMD_ALL_SEND_CID:
  420. case MMC_CMD_SELECT_CARD:
  421. case MMC_CMD_APP_CMD:
  422. ret = -ETIMEDOUT;
  423. break;
  424. default:
  425. printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
  426. ret = sh_mmcif_error_manage(host);
  427. break;
  428. }
  429. host->sd_error = 0;
  430. host->wait_int = 0;
  431. return ret;
  432. }
  433. /* if no response */
  434. if (!(opc & 0x00C00000))
  435. return 0;
  436. if (host->wait_int == 1) {
  437. sh_mmcif_get_response(host, cmd);
  438. host->wait_int = 0;
  439. }
  440. if (host->data)
  441. ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
  442. host->last_cmd = cmd->cmdidx;
  443. return ret;
  444. }
  445. static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
  446. struct mmc_cmd *cmd, struct mmc_data *data)
  447. {
  448. int ret;
  449. WATCHDOG_RESET();
  450. switch (cmd->cmdidx) {
  451. case MMC_CMD_APP_CMD:
  452. return -ETIMEDOUT;
  453. case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
  454. if (data)
  455. /* ext_csd */
  456. break;
  457. else
  458. /* send_if_cond cmd (not support) */
  459. return -ETIMEDOUT;
  460. default:
  461. break;
  462. }
  463. host->sd_error = 0;
  464. host->data = data;
  465. ret = sh_mmcif_start_cmd(host, data, cmd);
  466. host->data = NULL;
  467. return ret;
  468. }
  469. static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc)
  470. {
  471. if (mmc->clock)
  472. sh_mmcif_clock_control(host, mmc->clock);
  473. if (mmc->bus_width == 8)
  474. host->bus_width = MMC_BUS_WIDTH_8;
  475. else if (mmc->bus_width == 4)
  476. host->bus_width = MMC_BUS_WIDTH_4;
  477. else
  478. host->bus_width = MMC_BUS_WIDTH_1;
  479. debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
  480. return 0;
  481. }
  482. static int sh_mmcif_initialize_common(struct sh_mmcif_host *host)
  483. {
  484. sh_mmcif_sync_reset(host);
  485. sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
  486. return 0;
  487. }
  488. #ifndef CONFIG_DM_MMC
  489. static void *mmc_priv(struct mmc *mmc)
  490. {
  491. return (void *)mmc->priv;
  492. }
  493. static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  494. struct mmc_data *data)
  495. {
  496. struct sh_mmcif_host *host = mmc_priv(mmc);
  497. return sh_mmcif_send_cmd_common(host, cmd, data);
  498. }
  499. static int sh_mmcif_set_ios(struct mmc *mmc)
  500. {
  501. struct sh_mmcif_host *host = mmc_priv(mmc);
  502. return sh_mmcif_set_ios_common(host, mmc);
  503. }
  504. static int sh_mmcif_initialize(struct mmc *mmc)
  505. {
  506. struct sh_mmcif_host *host = mmc_priv(mmc);
  507. return sh_mmcif_initialize_common(host);
  508. }
  509. static const struct mmc_ops sh_mmcif_ops = {
  510. .send_cmd = sh_mmcif_send_cmd,
  511. .set_ios = sh_mmcif_set_ios,
  512. .init = sh_mmcif_initialize,
  513. };
  514. static struct mmc_config sh_mmcif_cfg = {
  515. .name = DRIVER_NAME,
  516. .ops = &sh_mmcif_ops,
  517. .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
  518. MMC_MODE_8BIT,
  519. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  520. .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  521. };
  522. int mmcif_mmc_init(void)
  523. {
  524. struct mmc *mmc;
  525. struct sh_mmcif_host *host = NULL;
  526. host = malloc(sizeof(struct sh_mmcif_host));
  527. if (!host)
  528. return -ENOMEM;
  529. memset(host, 0, sizeof(*host));
  530. host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
  531. host->clk = CONFIG_SH_MMCIF_CLK;
  532. sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
  533. sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
  534. mmc = mmc_create(&sh_mmcif_cfg, host);
  535. if (mmc == NULL) {
  536. free(host);
  537. return -ENOMEM;
  538. }
  539. return 0;
  540. }
  541. #else
  542. struct sh_mmcif_plat {
  543. struct mmc_config cfg;
  544. struct mmc mmc;
  545. };
  546. int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  547. struct mmc_data *data)
  548. {
  549. struct sh_mmcif_host *host = dev_get_priv(dev);
  550. return sh_mmcif_send_cmd_common(host, cmd, data);
  551. }
  552. int sh_mmcif_dm_set_ios(struct udevice *dev)
  553. {
  554. struct sh_mmcif_host *host = dev_get_priv(dev);
  555. struct mmc *mmc = mmc_get_mmc_dev(dev);
  556. return sh_mmcif_set_ios_common(host, mmc);
  557. }
  558. static const struct dm_mmc_ops sh_mmcif_dm_ops = {
  559. .send_cmd = sh_mmcif_dm_send_cmd,
  560. .set_ios = sh_mmcif_dm_set_ios,
  561. };
  562. static int sh_mmcif_dm_bind(struct udevice *dev)
  563. {
  564. struct sh_mmcif_plat *plat = dev_get_platdata(dev);
  565. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  566. }
  567. static int sh_mmcif_dm_probe(struct udevice *dev)
  568. {
  569. struct sh_mmcif_plat *plat = dev_get_platdata(dev);
  570. struct sh_mmcif_host *host = dev_get_priv(dev);
  571. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  572. struct clk sh_mmcif_clk;
  573. fdt_addr_t base;
  574. int ret;
  575. base = devfdt_get_addr(dev);
  576. if (base == FDT_ADDR_T_NONE)
  577. return -EINVAL;
  578. host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K);
  579. if (!host->regs)
  580. return -ENOMEM;
  581. ret = clk_get_by_index(dev, 0, &sh_mmcif_clk);
  582. if (ret) {
  583. debug("failed to get clock, ret=%d\n", ret);
  584. return ret;
  585. }
  586. ret = clk_enable(&sh_mmcif_clk);
  587. if (ret) {
  588. debug("failed to enable clock, ret=%d\n", ret);
  589. return ret;
  590. }
  591. host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
  592. plat->cfg.name = dev->name;
  593. plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
  594. switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
  595. 1)) {
  596. case 8:
  597. plat->cfg.host_caps |= MMC_MODE_8BIT;
  598. break;
  599. case 4:
  600. plat->cfg.host_caps |= MMC_MODE_4BIT;
  601. break;
  602. case 1:
  603. break;
  604. default:
  605. dev_err(dev, "Invalid \"bus-width\" value\n");
  606. return -EINVAL;
  607. }
  608. sh_mmcif_initialize_common(host);
  609. plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
  610. plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
  611. plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
  612. plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  613. upriv->mmc = &plat->mmc;
  614. return 0;
  615. }
  616. static const struct udevice_id sh_mmcif_sd_match[] = {
  617. { .compatible = "renesas,sh-mmcif" },
  618. { /* sentinel */ }
  619. };
  620. U_BOOT_DRIVER(sh_mmcif_mmc) = {
  621. .name = "sh-mmcif",
  622. .id = UCLASS_MMC,
  623. .of_match = sh_mmcif_sd_match,
  624. .bind = sh_mmcif_dm_bind,
  625. .probe = sh_mmcif_dm_probe,
  626. .priv_auto_alloc_size = sizeof(struct sh_mmcif_host),
  627. .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat),
  628. .ops = &sh_mmcif_dm_ops,
  629. };
  630. #endif