mxsmmc.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 SSP MMC driver
  4. *
  5. * Copyright (C) 2019 DENX Software Engineering
  6. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  7. *
  8. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  9. * on behalf of DENX Software Engineering GmbH
  10. *
  11. * Based on code from LTIB:
  12. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  13. * Terry Lv
  14. *
  15. * Copyright 2007, Freescale Semiconductor, Inc
  16. * Andy Fleming
  17. *
  18. * Based vaguely on the pxa mmc code:
  19. * (C) Copyright 2003
  20. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  21. */
  22. #include <common.h>
  23. #include <malloc.h>
  24. #include <mmc.h>
  25. #include <linux/errno.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/clock.h>
  28. #include <asm/arch/imx-regs.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/mach-imx/dma.h>
  31. #include <bouncebuf.h>
  32. #define MXSMMC_MAX_TIMEOUT 10000
  33. #define MXSMMC_SMALL_TRANSFER 512
  34. #if !CONFIG_IS_ENABLED(DM_MMC)
  35. struct mxsmmc_priv {
  36. int id;
  37. int (*mmc_is_wp)(int);
  38. int (*mmc_cd)(int);
  39. struct mmc_config cfg; /* mmc configuration */
  40. struct mxs_dma_desc *desc;
  41. uint32_t buswidth;
  42. struct mxs_ssp_regs *regs;
  43. };
  44. #else /* CONFIG_IS_ENABLED(DM_MMC) */
  45. #include <dm/device.h>
  46. #include <dm/read.h>
  47. #include <dt-structs.h>
  48. #ifdef CONFIG_MX28
  49. #define dtd_fsl_imx_mmc dtd_fsl_imx28_mmc
  50. #else /* CONFIG_MX23 */
  51. #define dtd_fsl_imx_mmc dtd_fsl_imx23_mmc
  52. #endif
  53. struct mxsmmc_platdata {
  54. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  55. struct dtd_fsl_imx_mmc dtplat;
  56. #endif
  57. struct mmc_config cfg;
  58. struct mmc mmc;
  59. fdt_addr_t base;
  60. int non_removable;
  61. int buswidth;
  62. int dma_id;
  63. int clk_id;
  64. };
  65. struct mxsmmc_priv {
  66. int clkid;
  67. struct mxs_dma_desc *desc;
  68. u32 buswidth;
  69. struct mxs_ssp_regs *regs;
  70. unsigned int dma_channel;
  71. };
  72. #endif
  73. #if !CONFIG_IS_ENABLED(DM_MMC)
  74. static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  75. struct mmc_data *data);
  76. static int mxsmmc_cd(struct mxsmmc_priv *priv)
  77. {
  78. struct mxs_ssp_regs *ssp_regs = priv->regs;
  79. if (priv->mmc_cd)
  80. return priv->mmc_cd(priv->id);
  81. return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
  82. }
  83. static int mxsmmc_set_ios(struct mmc *mmc)
  84. {
  85. struct mxsmmc_priv *priv = mmc->priv;
  86. struct mxs_ssp_regs *ssp_regs = priv->regs;
  87. /* Set the clock speed */
  88. if (mmc->clock)
  89. mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
  90. switch (mmc->bus_width) {
  91. case 1:
  92. priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
  93. break;
  94. case 4:
  95. priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
  96. break;
  97. case 8:
  98. priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
  99. break;
  100. }
  101. /* Set the bus width */
  102. clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
  103. SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
  104. debug("MMC%d: Set %d bits bus width\n",
  105. mmc->block_dev.devnum, mmc->bus_width);
  106. return 0;
  107. }
  108. static int mxsmmc_init(struct mmc *mmc)
  109. {
  110. struct mxsmmc_priv *priv = mmc->priv;
  111. struct mxs_ssp_regs *ssp_regs = priv->regs;
  112. /* Reset SSP */
  113. mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
  114. /* Reconfigure the SSP block for MMC operation */
  115. writel(SSP_CTRL1_SSP_MODE_SD_MMC |
  116. SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
  117. SSP_CTRL1_DMA_ENABLE |
  118. SSP_CTRL1_POLARITY |
  119. SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
  120. SSP_CTRL1_DATA_CRC_IRQ_EN |
  121. SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
  122. SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
  123. SSP_CTRL1_RESP_ERR_IRQ_EN,
  124. &ssp_regs->hw_ssp_ctrl1_set);
  125. /* Set initial bit clock 400 KHz */
  126. mxs_set_ssp_busclock(priv->id, 400);
  127. /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
  128. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
  129. udelay(200);
  130. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
  131. return 0;
  132. }
  133. static const struct mmc_ops mxsmmc_ops = {
  134. .send_cmd = mxsmmc_send_cmd,
  135. .set_ios = mxsmmc_set_ios,
  136. .init = mxsmmc_init,
  137. };
  138. int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
  139. {
  140. struct mmc *mmc = NULL;
  141. struct mxsmmc_priv *priv = NULL;
  142. int ret;
  143. const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
  144. if (!mxs_ssp_bus_id_valid(id))
  145. return -ENODEV;
  146. priv = malloc(sizeof(struct mxsmmc_priv));
  147. if (!priv)
  148. return -ENOMEM;
  149. priv->desc = mxs_dma_desc_alloc();
  150. if (!priv->desc) {
  151. free(priv);
  152. return -ENOMEM;
  153. }
  154. ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
  155. if (ret)
  156. return ret;
  157. priv->mmc_is_wp = wp;
  158. priv->mmc_cd = cd;
  159. priv->id = id;
  160. priv->regs = mxs_ssp_regs_by_bus(id);
  161. priv->cfg.name = "MXS MMC";
  162. priv->cfg.ops = &mxsmmc_ops;
  163. priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  164. priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
  165. MMC_MODE_HS_52MHz | MMC_MODE_HS;
  166. /*
  167. * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
  168. * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
  169. * CLOCK_DIVIDE has to be an even value from 2 to 254, and
  170. * CLOCK_RATE could be any integer from 0 to 255.
  171. */
  172. priv->cfg.f_min = 400000;
  173. priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id)
  174. * 1000 / 2;
  175. priv->cfg.b_max = 0x20;
  176. mmc = mmc_create(&priv->cfg, priv);
  177. if (!mmc) {
  178. mxs_dma_desc_free(priv->desc);
  179. free(priv);
  180. return -ENOMEM;
  181. }
  182. return 0;
  183. }
  184. #endif /* CONFIG_IS_ENABLED(DM_MMC) */
  185. static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
  186. {
  187. struct mxs_ssp_regs *ssp_regs = priv->regs;
  188. uint32_t *data_ptr;
  189. int timeout = MXSMMC_MAX_TIMEOUT;
  190. uint32_t reg;
  191. uint32_t data_count = data->blocksize * data->blocks;
  192. if (data->flags & MMC_DATA_READ) {
  193. data_ptr = (uint32_t *)data->dest;
  194. while (data_count && --timeout) {
  195. reg = readl(&ssp_regs->hw_ssp_status);
  196. if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
  197. *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
  198. data_count -= 4;
  199. timeout = MXSMMC_MAX_TIMEOUT;
  200. } else
  201. udelay(1000);
  202. }
  203. } else {
  204. data_ptr = (uint32_t *)data->src;
  205. timeout *= 100;
  206. while (data_count && --timeout) {
  207. reg = readl(&ssp_regs->hw_ssp_status);
  208. if (!(reg & SSP_STATUS_FIFO_FULL)) {
  209. writel(*data_ptr++, &ssp_regs->hw_ssp_data);
  210. data_count -= 4;
  211. timeout = MXSMMC_MAX_TIMEOUT;
  212. } else
  213. udelay(1000);
  214. }
  215. }
  216. return timeout ? 0 : -ECOMM;
  217. }
  218. static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
  219. {
  220. uint32_t data_count = data->blocksize * data->blocks;
  221. int dmach;
  222. struct mxs_dma_desc *desc = priv->desc;
  223. void *addr;
  224. unsigned int flags;
  225. struct bounce_buffer bbstate;
  226. memset(desc, 0, sizeof(struct mxs_dma_desc));
  227. desc->address = (dma_addr_t)desc;
  228. if (data->flags & MMC_DATA_READ) {
  229. priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
  230. addr = data->dest;
  231. flags = GEN_BB_WRITE;
  232. } else {
  233. priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
  234. addr = (void *)data->src;
  235. flags = GEN_BB_READ;
  236. }
  237. bounce_buffer_start(&bbstate, addr, data_count, flags);
  238. priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
  239. priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
  240. (data_count << MXS_DMA_DESC_BYTES_OFFSET);
  241. #if !CONFIG_IS_ENABLED(DM_MMC)
  242. dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
  243. #else
  244. dmach = priv->dma_channel;
  245. #endif
  246. mxs_dma_desc_append(dmach, priv->desc);
  247. if (mxs_dma_go(dmach)) {
  248. bounce_buffer_stop(&bbstate);
  249. return -ECOMM;
  250. }
  251. bounce_buffer_stop(&bbstate);
  252. return 0;
  253. }
  254. #if !CONFIG_IS_ENABLED(DM_MMC)
  255. /*
  256. * Sends a command out on the bus. Takes the mmc pointer,
  257. * a command pointer, and an optional data pointer.
  258. */
  259. static int
  260. mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  261. {
  262. struct mxsmmc_priv *priv = mmc->priv;
  263. struct mxs_ssp_regs *ssp_regs = priv->regs;
  264. #else
  265. static int
  266. mxsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
  267. {
  268. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  269. struct mxsmmc_priv *priv = dev_get_priv(dev);
  270. struct mxs_ssp_regs *ssp_regs = priv->regs;
  271. struct mmc *mmc = &plat->mmc;
  272. #endif
  273. uint32_t reg;
  274. int timeout;
  275. uint32_t ctrl0;
  276. int ret;
  277. #if !CONFIG_IS_ENABLED(DM_MMC)
  278. int devnum = mmc->block_dev.devnum;
  279. #else
  280. int devnum = mmc_get_blk_desc(mmc)->devnum;
  281. #endif
  282. debug("MMC%d: CMD%d\n", devnum, cmd->cmdidx);
  283. /* Check bus busy */
  284. timeout = MXSMMC_MAX_TIMEOUT;
  285. while (--timeout) {
  286. udelay(1000);
  287. reg = readl(&ssp_regs->hw_ssp_status);
  288. if (!(reg &
  289. (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
  290. SSP_STATUS_CMD_BUSY))) {
  291. break;
  292. }
  293. }
  294. if (!timeout) {
  295. printf("MMC%d: Bus busy timeout!\n", devnum);
  296. return -ETIMEDOUT;
  297. }
  298. #if !CONFIG_IS_ENABLED(DM_MMC)
  299. /* See if card is present */
  300. if (!mxsmmc_cd(priv)) {
  301. printf("MMC%d: No card detected!\n", devnum);
  302. return -ENOMEDIUM;
  303. }
  304. #endif
  305. /* Start building CTRL0 contents */
  306. ctrl0 = priv->buswidth;
  307. /* Set up command */
  308. if (!(cmd->resp_type & MMC_RSP_CRC))
  309. ctrl0 |= SSP_CTRL0_IGNORE_CRC;
  310. if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
  311. ctrl0 |= SSP_CTRL0_GET_RESP;
  312. if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
  313. ctrl0 |= SSP_CTRL0_LONG_RESP;
  314. if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
  315. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
  316. else
  317. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
  318. /* Command index */
  319. reg = readl(&ssp_regs->hw_ssp_cmd0);
  320. reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
  321. reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
  322. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  323. reg |= SSP_CMD0_APPEND_8CYC;
  324. writel(reg, &ssp_regs->hw_ssp_cmd0);
  325. /* Command argument */
  326. writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
  327. /* Set up data */
  328. if (data) {
  329. /* READ or WRITE */
  330. if (data->flags & MMC_DATA_READ) {
  331. ctrl0 |= SSP_CTRL0_READ;
  332. #if !CONFIG_IS_ENABLED(DM_MMC)
  333. } else if (priv->mmc_is_wp &&
  334. priv->mmc_is_wp(devnum)) {
  335. printf("MMC%d: Can not write a locked card!\n", devnum);
  336. return -EOPNOTSUPP;
  337. #endif
  338. }
  339. ctrl0 |= SSP_CTRL0_DATA_XFER;
  340. reg = data->blocksize * data->blocks;
  341. #if defined(CONFIG_MX23)
  342. ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
  343. clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
  344. SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
  345. ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
  346. ((ffs(data->blocksize) - 1) <<
  347. SSP_CMD0_BLOCK_SIZE_OFFSET));
  348. #elif defined(CONFIG_MX28)
  349. writel(reg, &ssp_regs->hw_ssp_xfer_size);
  350. reg = ((data->blocks - 1) <<
  351. SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
  352. ((ffs(data->blocksize) - 1) <<
  353. SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
  354. writel(reg, &ssp_regs->hw_ssp_block_size);
  355. #endif
  356. }
  357. /* Kick off the command */
  358. ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
  359. writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
  360. /* Wait for the command to complete */
  361. timeout = MXSMMC_MAX_TIMEOUT;
  362. while (--timeout) {
  363. udelay(1000);
  364. reg = readl(&ssp_regs->hw_ssp_status);
  365. if (!(reg & SSP_STATUS_CMD_BUSY))
  366. break;
  367. }
  368. if (!timeout) {
  369. printf("MMC%d: Command %d busy\n", devnum, cmd->cmdidx);
  370. return -ETIMEDOUT;
  371. }
  372. /* Check command timeout */
  373. if (reg & SSP_STATUS_RESP_TIMEOUT) {
  374. debug("MMC%d: Command %d timeout (status 0x%08x)\n",
  375. devnum, cmd->cmdidx, reg);
  376. return -ETIMEDOUT;
  377. }
  378. /* Check command errors */
  379. if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
  380. printf("MMC%d: Command %d error (status 0x%08x)!\n",
  381. devnum, cmd->cmdidx, reg);
  382. return -ECOMM;
  383. }
  384. /* Copy response to response buffer */
  385. if (cmd->resp_type & MMC_RSP_136) {
  386. cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
  387. cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
  388. cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
  389. cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
  390. } else
  391. cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
  392. /* Return if no data to process */
  393. if (!data)
  394. return 0;
  395. if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
  396. ret = mxsmmc_send_cmd_pio(priv, data);
  397. if (ret) {
  398. printf("MMC%d: Data timeout with command %d "
  399. "(status 0x%08x)!\n", devnum, cmd->cmdidx, reg);
  400. return ret;
  401. }
  402. } else {
  403. ret = mxsmmc_send_cmd_dma(priv, data);
  404. if (ret) {
  405. printf("MMC%d: DMA transfer failed\n", devnum);
  406. return ret;
  407. }
  408. }
  409. /* Check data errors */
  410. reg = readl(&ssp_regs->hw_ssp_status);
  411. if (reg &
  412. (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
  413. SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
  414. printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
  415. devnum, cmd->cmdidx, reg);
  416. return -ECOMM;
  417. }
  418. return 0;
  419. }
  420. #if CONFIG_IS_ENABLED(DM_MMC)
  421. /* Base numbers of i.MX2[38] clk for ssp0 IP block */
  422. #define MXS_SSP_IMX23_CLKID_SSP0 33
  423. #define MXS_SSP_IMX28_CLKID_SSP0 46
  424. static int mxsmmc_get_cd(struct udevice *dev)
  425. {
  426. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  427. struct mxsmmc_priv *priv = dev_get_priv(dev);
  428. struct mxs_ssp_regs *ssp_regs = priv->regs;
  429. if (plat->non_removable)
  430. return 1;
  431. return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
  432. }
  433. static int mxsmmc_set_ios(struct udevice *dev)
  434. {
  435. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  436. struct mxsmmc_priv *priv = dev_get_priv(dev);
  437. struct mxs_ssp_regs *ssp_regs = priv->regs;
  438. struct mmc *mmc = &plat->mmc;
  439. /* Set the clock speed */
  440. if (mmc->clock)
  441. mxs_set_ssp_busclock(priv->clkid, mmc->clock / 1000);
  442. switch (mmc->bus_width) {
  443. case 1:
  444. priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
  445. break;
  446. case 4:
  447. priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
  448. break;
  449. case 8:
  450. priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
  451. break;
  452. }
  453. /* Set the bus width */
  454. clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
  455. SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
  456. debug("MMC%d: Set %d bits bus width\n", mmc_get_blk_desc(mmc)->devnum,
  457. mmc->bus_width);
  458. return 0;
  459. }
  460. static int mxsmmc_init(struct udevice *dev)
  461. {
  462. struct mxsmmc_priv *priv = dev_get_priv(dev);
  463. struct mxs_ssp_regs *ssp_regs = priv->regs;
  464. /* Reset SSP */
  465. mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
  466. /* Reconfigure the SSP block for MMC operation */
  467. writel(SSP_CTRL1_SSP_MODE_SD_MMC |
  468. SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
  469. SSP_CTRL1_DMA_ENABLE |
  470. SSP_CTRL1_POLARITY |
  471. SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
  472. SSP_CTRL1_DATA_CRC_IRQ_EN |
  473. SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
  474. SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
  475. SSP_CTRL1_RESP_ERR_IRQ_EN,
  476. &ssp_regs->hw_ssp_ctrl1_set);
  477. /* Set initial bit clock 400 KHz */
  478. mxs_set_ssp_busclock(priv->clkid, 400);
  479. /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
  480. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
  481. udelay(200);
  482. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
  483. return 0;
  484. }
  485. static int mxsmmc_probe(struct udevice *dev)
  486. {
  487. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  488. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  489. struct mxsmmc_priv *priv = dev_get_priv(dev);
  490. struct blk_desc *bdesc;
  491. struct mmc *mmc;
  492. int ret, clkid;
  493. debug("%s: probe\n", __func__);
  494. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  495. struct dtd_fsl_imx_mmc *dtplat = &plat->dtplat;
  496. struct phandle_1_arg *p1a = &dtplat->clocks[0];
  497. priv->buswidth = dtplat->bus_width;
  498. priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
  499. priv->dma_channel = dtplat->dmas[1];
  500. clkid = p1a->arg[0];
  501. plat->non_removable = dtplat->non_removable;
  502. debug("OF_PLATDATA: regs: 0x%p bw: %d clkid: %d non_removable: %d\n",
  503. priv->regs, priv->buswidth, clkid, plat->non_removable);
  504. #else
  505. priv->regs = (struct mxs_ssp_regs *)plat->base;
  506. priv->dma_channel = plat->dma_id;
  507. clkid = plat->clk_id;
  508. #endif
  509. #ifdef CONFIG_MX28
  510. priv->clkid = clkid - MXS_SSP_IMX28_CLKID_SSP0;
  511. #else /* CONFIG_MX23 */
  512. priv->clkid = clkid - MXS_SSP_IMX23_CLKID_SSP0;
  513. #endif
  514. mmc = &plat->mmc;
  515. mmc->cfg = &plat->cfg;
  516. mmc->dev = dev;
  517. priv->desc = mxs_dma_desc_alloc();
  518. if (!priv->desc) {
  519. printf("%s: Cannot allocate DMA descriptor\n", __func__);
  520. return -ENOMEM;
  521. }
  522. ret = mxs_dma_init_channel(priv->dma_channel);
  523. if (ret)
  524. return ret;
  525. plat->cfg.name = "MXS MMC";
  526. plat->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  527. plat->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
  528. MMC_MODE_HS_52MHz | MMC_MODE_HS;
  529. /*
  530. * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
  531. * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
  532. * CLOCK_DIVIDE has to be an even value from 2 to 254, and
  533. * CLOCK_RATE could be any integer from 0 to 255.
  534. */
  535. plat->cfg.f_min = 400000;
  536. plat->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + priv->clkid) * 1000 / 2;
  537. plat->cfg.b_max = 0x20;
  538. bdesc = mmc_get_blk_desc(mmc);
  539. if (!bdesc) {
  540. printf("%s: No block device descriptor!\n", __func__);
  541. return -ENODEV;
  542. }
  543. if (plat->non_removable)
  544. bdesc->removable = 0;
  545. ret = mxsmmc_init(dev);
  546. if (ret)
  547. printf("%s: MMC%d init error %d\n", __func__,
  548. bdesc->devnum, ret);
  549. /* Set the initial clock speed */
  550. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  551. upriv->mmc = mmc;
  552. return 0;
  553. };
  554. #if CONFIG_IS_ENABLED(BLK)
  555. static int mxsmmc_bind(struct udevice *dev)
  556. {
  557. struct mxsmmc_platdata *plat = dev_get_platdata(dev);
  558. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  559. }
  560. #endif
  561. static const struct dm_mmc_ops mxsmmc_ops = {
  562. .get_cd = mxsmmc_get_cd,
  563. .send_cmd = mxsmmc_send_cmd,
  564. .set_ios = mxsmmc_set_ios,
  565. };
  566. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  567. static int mxsmmc_ofdata_to_platdata(struct udevice *bus)
  568. {
  569. struct mxsmmc_platdata *plat = bus->platdata;
  570. u32 prop[2];
  571. int ret;
  572. plat->base = dev_read_addr(bus);
  573. plat->buswidth =
  574. dev_read_u32_default(bus, "bus-width", 1);
  575. plat->non_removable = dev_read_bool(bus, "non-removable");
  576. ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
  577. if (ret) {
  578. printf("%s: Reading 'dmas' property failed!\n", __func__);
  579. return ret;
  580. }
  581. plat->dma_id = prop[1];
  582. ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
  583. if (ret) {
  584. printf("%s: Reading 'clocks' property failed!\n", __func__);
  585. return ret;
  586. }
  587. plat->clk_id = prop[1];
  588. debug("%s: base=0x%x, bus_width=%d %s dma_id=%d clk_id=%d\n",
  589. __func__, (uint)plat->base, plat->buswidth,
  590. plat->non_removable ? "non-removable" : NULL,
  591. plat->dma_id, plat->clk_id);
  592. return 0;
  593. }
  594. static const struct udevice_id mxsmmc_ids[] = {
  595. { .compatible = "fsl,imx23-mmc", },
  596. { .compatible = "fsl,imx28-mmc", },
  597. { /* sentinel */ }
  598. };
  599. #endif
  600. U_BOOT_DRIVER(mxsmmc) = {
  601. #ifdef CONFIG_MX28
  602. .name = "fsl_imx28_mmc",
  603. #else /* CONFIG_MX23 */
  604. .name = "fsl_imx23_mmc",
  605. #endif
  606. .id = UCLASS_MMC,
  607. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  608. .of_match = mxsmmc_ids,
  609. .ofdata_to_platdata = mxsmmc_ofdata_to_platdata,
  610. #endif
  611. .ops = &mxsmmc_ops,
  612. #if CONFIG_IS_ENABLED(BLK)
  613. .bind = mxsmmc_bind,
  614. #endif
  615. .probe = mxsmmc_probe,
  616. .priv_auto_alloc_size = sizeof(struct mxsmmc_priv),
  617. .platdata_auto_alloc_size = sizeof(struct mxsmmc_platdata),
  618. };
  619. #endif /* CONFIG_DM_MMC */